mirror of
https://github.com/alangarf/apple-one.git
synced 2024-05-31 22:41:28 +00:00
77 lines
1.8 KiB
Plaintext
77 lines
1.8 KiB
Plaintext
#-- Synopsys, Inc.
|
|
#-- Version L-2016.09L+ice40
|
|
#-- Project file C:\Users\Alan\Desktop\projects\apple1\apple1_syn.prj
|
|
#-- Written on Mon Jan 01 00:45:12 2018
|
|
|
|
|
|
#project files
|
|
|
|
|
|
|
|
add_file -verilog -lib work "rtl/apple1_top.v"
|
|
add_file -verilog -lib work "rtl/chip_6502.v"
|
|
add_file -verilog -lib work "rtl/chip_6502_mux.v"
|
|
add_file -verilog -lib work "rtl/led_and_key.v"
|
|
add_file -verilog -lib work "rtl/tm1638.v"
|
|
add_file -verilog -lib work "rtl/uart.v"
|
|
#implementation: "apple1_Implmnt"
|
|
impl -add apple1_Implmnt -type fpga
|
|
|
|
#
|
|
#implementation attributes
|
|
|
|
set_option -vlog_std v2001
|
|
set_option -project_relative_includes 1
|
|
|
|
#device options
|
|
set_option -technology SBTiCE40
|
|
set_option -part iCE40HX8K
|
|
set_option -package CT256
|
|
set_option -speed_grade
|
|
set_option -part_companion ""
|
|
|
|
#compilation/mapping options
|
|
set_option -top_module "top"
|
|
|
|
# hdl_compiler_options
|
|
set_option -distributed_compile 0
|
|
|
|
# mapper_without_write_options
|
|
set_option -frequency auto
|
|
set_option -srs_instrumentation 1
|
|
|
|
# mapper_options
|
|
set_option -write_verilog 0
|
|
set_option -write_vhdl 0
|
|
|
|
# Lattice iCE40
|
|
set_option -maxfan 10000
|
|
set_option -rw_check_on_ram 0
|
|
set_option -disable_io_insertion 0
|
|
set_option -pipe 1
|
|
set_option -retiming 0
|
|
set_option -update_models_cp 0
|
|
set_option -fix_gated_and_generated_clocks 1
|
|
set_option -run_prop_extract 1
|
|
|
|
# NFilter
|
|
set_option -no_sequential_opt 0
|
|
|
|
# sequential_optimization_options
|
|
set_option -symbolic_fsm_compiler 1
|
|
|
|
# Compiler Options
|
|
set_option -compiler_compatible 0
|
|
set_option -resource_sharing 1
|
|
|
|
# Compiler Options
|
|
set_option -auto_infer_blackbox 0
|
|
|
|
#automatic place and route (vendor) options
|
|
set_option -write_apr_constraint 1
|
|
|
|
#set result format/file last
|
|
project -result_file "apple1_Implmnt/apple1.edf"
|
|
impl -active apple1_Implmnt
|
|
project -run synthesis -clean
|