Apple-1-HW/verilog-apple-one
1
0
Fork 0
mirror of https://github.com/alangarf/apple-one.git synced 2025-01-23 05:30:16 +00:00
Code Issues Projects Releases Wiki Activity
verilog-apple-one/rtl/vga
History
Olof Kindgren 2226afe669 Expose ROM/RAM files as top-level parameters 
This allows file names to be overridden at compile-time.

It also gets rid of the ifdef SIM in the verilog components
2018-02-12 14:04:00 +01:00
..
font_rom.v
Expose ROM/RAM files as top-level parameters
2018-02-12 14:04:00 +01:00
vga.v
Expose ROM/RAM files as top-level parameters
2018-02-12 14:04:00 +01:00
vram.v
Expose ROM/RAM files as top-level parameters
2018-02-12 14:04:00 +01:00