verilog-apple-one/boards/spartan3e_starterkit/webpack_ise/apple1_s3e_starterkit_top.ucf

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#Pin definitions
# clocks
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# ps/2 keyboard
NET "PS2_KBDAT" LOC = G13 | IOSTANDARD = LVCMOS33;
NET "PS2_KBCLK" LOC = G14 | IOSTANDARD = LVCMOS33;
# VGA pins
NET "VGA_R" LOC = H14 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_G" LOC = H15 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_B" LOC = G15 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_HS" LOC = F15 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_VS" LOC = F14 | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
# RS-232 pins
#NET "UART_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
#NET "UART_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "UART_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
NET "UART_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
# RESET BUTTON / SOUTH on the board
NET "BUTTON" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
#Created by Constraints Editor (xc3s500e-fg320-4) - 2018/02/11
NET "CLK_50MHZ" TNM_NET = CLK_50MHZ;
NET "clk25" TNM_NET = clk25;
TIMESPEC TS_CLOCK_50 = PERIOD "CLK_50MHZ" 20 ns HIGH 50%;
TIMESPEC TS_CLOCK_25 = PERIOD "clk25" 40 ns HIGH 50%;