verilog-apple-one/rtl/boards/ice40hx8k/clock_pll_inst.v
2018-01-27 00:21:05 +11:00

5 lines
160 B
Verilog

clock_pll clock_pll_inst(.REFERENCECLK(),
.PLLOUTCORE(),
.PLLOUTGLOBAL(),
.RESET());