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35 lines
679 B
Verilog
35 lines
679 B
Verilog
module clocks (
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input clk,
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output clk25,
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output reg cpu_clken
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);
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// 12MHz up to 25MHz
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clock_pll clock_pll_inst(
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.REFERENCECLK(clk),
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.PLLOUTCORE(),
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.PLLOUTGLOBAL(clk25),
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.RESET(1'b1)
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);
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reg [25:0] clk_div;
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always @(posedge clk25)
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begin
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if (clk_div == 12000000)
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clk_div <= 0;
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else
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clk_div <= clk_div + 1;
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// 1MHz
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cpu_clken <= (clk_div[25:0] == 0);
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// 2MHz
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//cpu_clken <= (clk_div[4] == 0) & (clk_div[2:0] == 0);
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// 4MHz
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//cpu_clken <= (clk_div[4] == 0) & (clk_div[1:0] == 0);
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end
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endmodule
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