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20 lines
285 B
Verilog
20 lines
285 B
Verilog
module rom_wozmon(
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input clk,
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input [7:0] address,
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output reg [7:0] dout
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);
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reg [7:0] rom[0:255];
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initial
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$readmemh("../../../roms/rom.hex", rom, 0, 255);
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always @(posedge clk)
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begin
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dout <= rom[address];
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end
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endmodule
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