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169 lines
5.1 KiB
Verilog
169 lines
5.1 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: A wrapper for the basic UART from fpga4fun.com
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//
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// Author.....: Alan Garfield
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// Niels A. Moseley
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// Date.......: 26-1-2018
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//
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module uart(
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input clk, // clock signal
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input enable, // clock enable strobe
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input rst, // active high reset signal
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input [1:0] address, // address bus
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input w_en, // active high write enable strobe
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input [7:0] din, // 8-bit data bus (input)
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output reg [7:0] dout, // 8-bit data bus (output)
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input uart_rx, // asynchronous serial data input from computer
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output uart_tx, // asynchronous serial data output to computer
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output uart_cts // clear to send flag to computer
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);
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parameter ClkFrequency = 25000000; // 25MHz
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parameter Baud = 115200;
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parameter Oversampling = 8;
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reg uart_tx_stb, uart_tx_init;
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reg [7:0] uart_tx_byte;
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wire uart_tx_status;
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async_transmitter #(ClkFrequency, Baud) my_tx (
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.clk(clk),
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.rst(rst),
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.TxD_start(uart_tx_stb),
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.TxD_data(uart_tx_byte),
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.TxD(uart_tx),
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.TxD_busy(uart_tx_status)
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);
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wire uart_rx_stb, rx_idle, rx_end;
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wire [7:0] rx_data;
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reg uart_rx_status, uart_rx_ack;
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reg [7:0] uart_rx_byte;
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async_receiver #(ClkFrequency, Baud, Oversampling) my_rx(
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.clk(clk),
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.rst(rst),
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.RxD(uart_rx),
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.RxD_data_ready(uart_rx_stb),
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.RxD_data(rx_data),
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.RxD_idle(rx_idle),
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.RxD_endofpacket(rx_end)
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);
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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uart_rx_status <= 'b0;
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uart_rx_byte <= 8'd0;
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end
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else
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begin
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// new byte from RX, check register is clear and CPU has seen
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// previous byte, otherwise we ignore the new data
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if (uart_rx_stb && ~uart_rx_status)
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begin
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uart_rx_status <= 'b1;
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uart_rx_byte <= rx_data;
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end
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// clear the rx status flag on ack from CPU
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if (uart_rx_ack)
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uart_rx_status <= 'b0;
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end
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end
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assign uart_cts = ~rx_idle || uart_rx_status;
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localparam UART_RX = 2'b00;
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localparam UART_RXCR = 2'b01;
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localparam UART_TX = 2'b10;
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// Handle Register
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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begin
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dout <= 8'd0;
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uart_tx_init <= 0; // flag to ignore the DDR setup from Wozmon PIA call
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uart_tx_stb <= 0;
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uart_tx_byte <= 8'd0;
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uart_rx_ack <= 0;
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end
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else
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begin
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uart_tx_stb <= 0;
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uart_rx_ack <= 0;
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case (address)
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UART_TX:
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begin
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// UART TX - 0xD012
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dout <= {uart_tx_status, 7'd0};
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if (w_en)
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begin
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// Apple 1 terminal only uses 7 bits, MSB indicates
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// terminal has ack'd RX
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//
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// uart_tx_init is a flag to stop the first character
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// sent to the UART from being sent. Wozmon initializes
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// the PIA which normally isn't sent to the terminal.
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// This causes the UART to ignore the very first byte sent.
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if (~uart_tx_status && uart_tx_init)
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begin
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`ifdef SIM
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if ((din & 8'h7f) >= 32)
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$write("%c", din & 8'h7f);
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`endif
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uart_tx_byte <= {1'b0, din[6:0]};
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uart_tx_stb <= 1;
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end
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else if (~uart_tx_init)
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uart_tx_init <= 1 && enable;
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end
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end
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UART_RXCR:
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begin
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// UART RX CR - 0xD011
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dout <= {uart_rx_status, 7'b0};
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end
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UART_RX:
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begin
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// UART RX - 0xD010
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dout <= {uart_rx_status, uart_rx_byte[6:0]};
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if (~w_en && ~uart_rx_ack && enable)
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uart_rx_ack <= 1'b1;
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end
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default:
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dout <= 8'b0;
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endcase
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end
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end
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endmodule
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