Apple-1-HW/verilog-apple-one
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9beb3e5f5e
verilog-apple-one/rtl/uart
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Niels Moseley 9beb3e5f5e Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files.
2018-01-26 21:29:12 +01:00
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async_tx_rx.v move things around. 2018-01-27 00:21:05 +11:00
uart.v Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00