78 lines
2.0 KiB
Verilog
78 lines
2.0 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: RAM for ukp
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//
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// Author.....: Alan Garfield
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// Date.......: 11-4-2018
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//
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module ukpram #(
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parameter UKPRAM_FILENAME = "../../../roms/ukp_ram.bin"
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) (
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input clk25, // clock signal
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input clkusb, // USB clock signal
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input [4:0] read_addr, // read address bus
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input [5:0] write_addr, // write address bus
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input r_en, // active high read enable strobe
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input w_en, // active high write enable strobe
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input [3:0] din, // 4-bit data bus (input)
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output reg [7:0] dout // 8-bit data bus (output)
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);
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reg [3:0] ram_data[0:63];
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//initial
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// $readmemb(UKPRAM_FILENAME, ram_data, 0, 63);
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always @(posedge clkusb)
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begin
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if (w_en) ram_data[write_addr] <= din;
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end
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always @(posedge clk25)
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begin
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if (r_en) dout <= {
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ram_data[{read_addr, 1'b1}],
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ram_data[{read_addr, 1'b0}]
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};
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end
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endmodule
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// BANK A
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// 0000 000001
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// 000000
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// 0001 000011
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// 000010
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// 0010
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// 0011
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// 0100
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// 0101
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// 0110
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// 0111
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//
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// BANK B
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// 1000
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// 1001
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// 1010
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// 1011
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// 1100
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// 1101
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// 1110
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// 1111
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