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https://github.com/alangarf/apple-one.git
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145 lines
3.8 KiB
Verilog
145 lines
3.8 KiB
Verilog
module vga(
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input clk,
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input [6:0] in,
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input in_stb,
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output vga_h_sync,
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output vga_v_sync,
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output reg vga_red,
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output reg vga_grn,
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output reg vga_blu
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);
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reg [5:0] v_ram[0:959] /* synthesis syn_ramstyle = "block_ram" */;
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reg [4:0] c_rom[0:447] /* synthesis syn_ramstyle = "block_ram" */;
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initial begin
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$readmemb("../roms/vga_vram.bin", v_ram, 0, 959);
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$readmemb("../roms/vga_font.bin", c_rom, 0, 447);
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end
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// generate 25MHz pixel clock enable
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reg vga_cnt;
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wire vga_clk_en;
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always @(posedge clk)
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begin
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vga_cnt <= vga_cnt + 1;
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end
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assign vga_clk_en = vga_cnt;
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// video structure constants
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parameter hpixels = 800; // horizontal pixels per line
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parameter vlines = 521; // vertical lines per frame
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parameter hpulse = 96; // hsync pulse length
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parameter vpulse = 2; // vsync pulse length
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parameter hbp = 144; // end of horizontal back porch
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parameter hfp = 784; // beginning of horizontal front porch
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parameter vbp = 31; // end of vertical back porch
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parameter vfp = 511; // beginning of vertical front porch
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// registers for storing the horizontal & vertical counters
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reg [9:0] hc;
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reg [9:0] vc;
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reg [5:0] hpos;
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reg [4:0] vpos;
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reg [3:0] hdot;
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reg [4:0] vdot;
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always @(posedge clk)
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begin
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if (vga_clk_en)
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begin
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if (hc < hpixels - 1)
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begin
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hc <= hc + 1;
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// count 16 pixels, so 640px / 16 = 40 characters
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if (vga_h_act)
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begin
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hdot <= hdot + 1;
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if (hdot == 4'hF)
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begin
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hdot <= 0;
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hpos <= hpos + 1;
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end
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end
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end
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else
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begin
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// reset horizontal counters
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hc <= 0;
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hdot <= 0;
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hpos <= 0;
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if (vc < vlines - 1)
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begin
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vc <= vc + 1;
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// count 20 rows, so 480px / 20 = 24 rows
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if (vga_v_act)
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begin
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vdot <= vdot + 1;
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if (vdot == 5'd19)
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begin
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vdot <= 0;
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vpos <= vpos + 1;
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end
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end
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end
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else
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begin
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vc <= 0;
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vdot <= 0;
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vpos <= 0;
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end
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end
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end
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end
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assign vga_h_act = (hc >= hbp && hc < hfp);
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assign vga_v_act = (vc >= vbp && vc < vfp);
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assign vga_h_sync = (hc < hpulse) ? 0 : 1;
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assign vga_v_sync = (vc < vpulse) ? 0 : 1;
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// assign vblank = (vc >= vbp && vc < vfp) ? 0:1;
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always @(posedge clk)
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begin
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if (~(vga_h_act && vga_v_act))
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begin
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// outside display area
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vga_red = 0;
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end else begin
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// inside display area
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if (vdot[4:1] == 0 || vdot[4:1] == 1 || vdot[4:1] == 9 || hdot[3:1] == 0 || hdot[3:1] == 6 || hdot[3:1] == 7)
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vga_red = 0;
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else
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vga_red = c_rom[(v_ram[hpos + (vpos * 40)] * 7) + (vdot[4:1] - 2)][5 - hdot[3:1]];
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end
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vga_grn = vga_red;
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vga_blu = vga_red;
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end
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reg [5:0] cur_pos;
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reg stb;
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always @(posedge clk)
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begin
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if (in_stb & ~stb)
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begin
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v_ram[cur_pos] <= {~in[6], in[4:0]};
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stb <= 1;
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cur_pos <= cur_pos + 1;
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end
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if (~in_stb & stb)
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begin
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stb <= 0;
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end
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end
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endmodule
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