mirror of
https://github.com/alangarf/apple-one.git
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105 lines
2.5 KiB
Verilog
105 lines
2.5 KiB
Verilog
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Top level test bench for apple1_top
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//
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// Author.....: Niels A. Moseley
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// Date.......: 26-1-2018
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//
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`timescale 1ns/1ps
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module ukp_tb;
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reg clk12;
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reg rst, enable;
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reg usb_dm_out, usb_dp_out;
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reg [3:0] kbd_adr;
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inout usb_dm, usb_dp;
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wire usb_dm_in, usb_dp_in;
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wire record_n;
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wire [7:0] kbd_data;
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assign usb_dm = (enable) ? usb_dm_out : 1'bZ;
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assign usb_dp = (enable) ? usb_dp_out : 1'bZ;
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assign usb_dm_in = usb_dm;
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assign usb_dp_in = usb_dp;
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//////////////////////////////////////////////////////////////////////////
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// Setup dumping of data for inspection
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initial begin
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clk12 = 1'b0;
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enable = 1'b1;
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usb_dm_out = 1'b0;
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usb_dp_out = 1'b0;
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kbd_adr = 1'b0;
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rst = 1'b1;
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$display("Starting...");
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$dumpfile("ukp_tb.vcd");
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$dumpvars;
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#5
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rst = 1'b0;
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#48000
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usb_dm_out = 1'b1;
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#1000
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enable = 1'b0;
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#3267997
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usb_dm_out = 1'b1;
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enable = 1'b1;
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#10
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usb_dm_out = 1'b0;
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usb_dp_out = 1'b1;
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#10
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usb_dm_out = 1'b1;
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usb_dp_out = 1'b0;
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#10
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usb_dm_out = 1'b0;
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usb_dp_out = 1'b1;
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#50000 $display("Stopping...");
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$finish;
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end
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//////////////////////////////////////////////////////////////////////////
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// Clock
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always
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#2 clk12 = !clk12;
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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ukp my_ukp (
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.clk12(clk12),
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.rst(rst),
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.usb_dm(usb_dm),
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.usb_dp(usb_dp),
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.record_n(record_n),
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.kbd_adr(kbd_adr),
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.kbd_data(kbd_data)
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);
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endmodule
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