Niels Moseley f067774293 Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.		2018-01-26 22:38:46 +01:00
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boards/ice40hx8k
cpu
led_and_key
uart	Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files.	2018-01-26 21:29:12 +01:00
vga
apple1_top.v	Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.	2018-01-26 22:38:46 +01:00
ram.v
rom_wozmon.v