238 lines
21 KiB
Swift
238 lines
21 KiB
Swift
//
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// CPUInstructions.swift
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// FruitMachine
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//
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// Created by Christopher Rohl on 7/20/17.
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// Copyright © 2017 Christopher Rohl. All rights reserved.
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//
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import Cocoa
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final class CPUInstruction: NSObject {
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let mnemonic: String //The mnemonic for this instruction.
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let cycles: Int //How many cycles does this instruction take?
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let bytes: Int //How many bytes long is this instruction?
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let addressingMode: CPU.AddressingMode //The addressing mode of this instruction.
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let action: (CPU, CPU.AddressingMode) -> Void //A closure that describes this function's action.
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init(mnemonic: String, cycles: Int, bytes: Int, addressingMode: CPU.AddressingMode, action: @escaping (CPU, CPU.AddressingMode) -> Void) {
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self.mnemonic = mnemonic
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self.cycles = cycles
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self.bytes = bytes
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self.addressingMode = addressingMode
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self.action = action
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}
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}
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//indexed_indirect = LDA ($00,X)
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//indirect_indexed = LDA ($00),Y
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let InstructionTable: [UInt8:CPUInstruction] = [
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//ADC/SBC
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0x69: CPUInstruction(mnemonic: "ADC", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.ADC),
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0x65: CPUInstruction(mnemonic: "ADC", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.ADC),
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0x75: CPUInstruction(mnemonic: "ADC", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.ADC),
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0x6D: CPUInstruction(mnemonic: "ADC", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.ADC),
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0x7D: CPUInstruction(mnemonic: "ADC", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.ADC),
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0x79: CPUInstruction(mnemonic: "ADC", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_y, action: Opcodes.ADC),
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0x61: CPUInstruction(mnemonic: "ADC", cycles: 6, bytes: 2, addressingMode: .indexed_indirect, action: Opcodes.ADC),
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0x71: CPUInstruction(mnemonic: "ADC", cycles: 5, bytes: 2, addressingMode: .indirect_indexed, action: Opcodes.ADC),
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0xE9: CPUInstruction(mnemonic: "SBC", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.SBC),
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0xE5: CPUInstruction(mnemonic: "SBC", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.SBC),
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0xF5: CPUInstruction(mnemonic: "SBC", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.SBC),
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0xED: CPUInstruction(mnemonic: "SBC", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.SBC),
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0xFD: CPUInstruction(mnemonic: "SBC", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.SBC),
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0xF9: CPUInstruction(mnemonic: "SBC", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_y, action: Opcodes.SBC),
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0xE1: CPUInstruction(mnemonic: "SBC", cycles: 6, bytes: 2, addressingMode: .indexed_indirect, action: Opcodes.SBC),
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0xF1: CPUInstruction(mnemonic: "SBC", cycles: 5, bytes: 2, addressingMode: .indirect_indexed, action: Opcodes.SBC),
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//Boolean operators
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0x09: CPUInstruction(mnemonic: "ORA", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.ORA),
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0x05: CPUInstruction(mnemonic: "ORA", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.ORA),
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0x15: CPUInstruction(mnemonic: "ORA", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.ORA),
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0x0D: CPUInstruction(mnemonic: "ORA", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.ORA),
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0x1D: CPUInstruction(mnemonic: "ORA", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.ORA),
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0x19: CPUInstruction(mnemonic: "ORA", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_y, action: Opcodes.ORA),
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0x01: CPUInstruction(mnemonic: "ORA", cycles: 6, bytes: 2, addressingMode: .indexed_indirect, action: Opcodes.ORA),
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0x11: CPUInstruction(mnemonic: "ORA", cycles: 5, bytes: 2, addressingMode: .indirect_indexed, action: Opcodes.ORA),
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0x49: CPUInstruction(mnemonic: "EOR", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.EOR),
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0x45: CPUInstruction(mnemonic: "EOR", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.EOR),
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0x55: CPUInstruction(mnemonic: "EOR", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.EOR),
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0x4D: CPUInstruction(mnemonic: "EOR", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.EOR),
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0x5D: CPUInstruction(mnemonic: "EOR", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.EOR),
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0x59: CPUInstruction(mnemonic: "EOR", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_y, action: Opcodes.EOR),
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0x41: CPUInstruction(mnemonic: "EOR", cycles: 6, bytes: 2, addressingMode: .indexed_indirect, action: Opcodes.EOR),
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0x51: CPUInstruction(mnemonic: "EOR", cycles: 5, bytes: 2, addressingMode: .indirect_indexed, action: Opcodes.EOR),
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0x29: CPUInstruction(mnemonic: "AND", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.AND),
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0x25: CPUInstruction(mnemonic: "AND", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.AND),
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0x35: CPUInstruction(mnemonic: "AND", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.AND),
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0x2D: CPUInstruction(mnemonic: "AND", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.AND),
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0x3D: CPUInstruction(mnemonic: "AND", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.AND),
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0x39: CPUInstruction(mnemonic: "AND", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_y, action: Opcodes.AND),
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0x21: CPUInstruction(mnemonic: "AND", cycles: 6, bytes: 2, addressingMode: .indexed_indirect, action: Opcodes.AND),
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0x31: CPUInstruction(mnemonic: "AND", cycles: 5, bytes: 2, addressingMode: .indirect_indexed, action: Opcodes.AND),
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//Bitwise operations
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0x24: CPUInstruction(mnemonic: "BIT", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.BIT),
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0x2C: CPUInstruction(mnemonic: "BIT", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.BIT),
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0x0A: CPUInstruction(mnemonic: "ASL", cycles: 2, bytes: 1, addressingMode: .accumulator, action: Opcodes.ASL),
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0x06: CPUInstruction(mnemonic: "ASL", cycles: 5, bytes: 2, addressingMode: .zeropage, action: Opcodes.ASL),
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0x16: CPUInstruction(mnemonic: "ASL", cycles: 6, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.ASL),
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0x0E: CPUInstruction(mnemonic: "ASL", cycles: 6, bytes: 3, addressingMode: .absolute, action: Opcodes.ASL),
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0x1E: CPUInstruction(mnemonic: "ASL", cycles: 7, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.ASL),
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0x4A: CPUInstruction(mnemonic: "LSR", cycles: 2, bytes: 1, addressingMode: .accumulator, action: Opcodes.LSR),
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0x46: CPUInstruction(mnemonic: "LSR", cycles: 5, bytes: 2, addressingMode: .zeropage, action: Opcodes.LSR),
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0x56: CPUInstruction(mnemonic: "LSR", cycles: 6, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.LSR),
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0x4E: CPUInstruction(mnemonic: "LSR", cycles: 6, bytes: 3, addressingMode: .absolute, action: Opcodes.LSR),
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0x5E: CPUInstruction(mnemonic: "LSR", cycles: 7, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.LSR),
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0x2A: CPUInstruction(mnemonic: "ROL", cycles: 2, bytes: 1, addressingMode: .accumulator, action: Opcodes.ROL),
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0x26: CPUInstruction(mnemonic: "ROL", cycles: 5, bytes: 2, addressingMode: .zeropage, action: Opcodes.ROL),
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0x36: CPUInstruction(mnemonic: "ROL", cycles: 6, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.ROL),
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0x2E: CPUInstruction(mnemonic: "ROL", cycles: 6, bytes: 3, addressingMode: .absolute, action: Opcodes.ROL),
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0x3E: CPUInstruction(mnemonic: "ROL", cycles: 7, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.ROL),
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0x6A: CPUInstruction(mnemonic: "ROR", cycles: 2, bytes: 1, addressingMode: .accumulator, action: Opcodes.ROR),
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0x66: CPUInstruction(mnemonic: "ROR", cycles: 5, bytes: 2, addressingMode: .zeropage, action: Opcodes.ROR),
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0x76: CPUInstruction(mnemonic: "ROR", cycles: 6, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.ROR),
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0x6E: CPUInstruction(mnemonic: "ROR", cycles: 6, bytes: 3, addressingMode: .absolute, action: Opcodes.ROR),
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0x7E: CPUInstruction(mnemonic: "ROR", cycles: 7, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.ROR),
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//INC/DEC
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0xC6: CPUInstruction(mnemonic: "DEC", cycles: 5, bytes: 2, addressingMode: .zeropage, action: Opcodes.DEC),
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0xD6: CPUInstruction(mnemonic: "DEC", cycles: 6, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.DEC),
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0xCE: CPUInstruction(mnemonic: "DEC", cycles: 6, bytes: 3, addressingMode: .absolute, action: Opcodes.DEC),
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0xDE: CPUInstruction(mnemonic: "DEC", cycles: 7, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.DEC),
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0xE6: CPUInstruction(mnemonic: "INC", cycles: 5, bytes: 2, addressingMode: .zeropage, action: Opcodes.INC),
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0xF6: CPUInstruction(mnemonic: "INC", cycles: 6, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.INC),
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0xEE: CPUInstruction(mnemonic: "INC", cycles: 6, bytes: 3, addressingMode: .absolute, action: Opcodes.INC),
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0xFE: CPUInstruction(mnemonic: "INC", cycles: 7, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.INC),
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//JMP
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0x4C: CPUInstruction(mnemonic: "JMP", cycles: 3, bytes: 3, addressingMode: .absolute, action: Opcodes.JMP),
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0x6C: CPUInstruction(mnemonic: "JMP", cycles: 5, bytes: 3, addressingMode: .indirect, action: Opcodes.JMP),
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//LD instructions
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0xA9: CPUInstruction(mnemonic: "LDA", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.LDA),
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0xA5: CPUInstruction(mnemonic: "LDA", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.LDA),
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0xB5: CPUInstruction(mnemonic: "LDA", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.LDA),
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0xAD: CPUInstruction(mnemonic: "LDA", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.LDA),
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0xBD: CPUInstruction(mnemonic: "LDA", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.LDA),
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0xB9: CPUInstruction(mnemonic: "LDA", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_y, action: Opcodes.LDA),
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0xA1: CPUInstruction(mnemonic: "LDA", cycles: 6, bytes: 2, addressingMode: .indexed_indirect, action: Opcodes.LDA),
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0xB1: CPUInstruction(mnemonic: "LDA", cycles: 5, bytes: 2, addressingMode: .indirect_indexed, action: Opcodes.LDA),
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0xA2: CPUInstruction(mnemonic: "LDX", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.LDX),
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0xA6: CPUInstruction(mnemonic: "LDX", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.LDX),
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0xB6: CPUInstruction(mnemonic: "LDX", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_y, action: Opcodes.LDX),
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0xAE: CPUInstruction(mnemonic: "LDX", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.LDX),
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0xBE: CPUInstruction(mnemonic: "LDX", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_y, action: Opcodes.LDX),
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0xA0: CPUInstruction(mnemonic: "LDY", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.LDY),
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0xA4: CPUInstruction(mnemonic: "LDY", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.LDY),
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0xB4: CPUInstruction(mnemonic: "LDY", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.LDY),
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0xAC: CPUInstruction(mnemonic: "LDY", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.LDY),
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0xBC: CPUInstruction(mnemonic: "LDY", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.LDY),
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//ST functions
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0x85: CPUInstruction(mnemonic: "STA", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.STA),
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0x95: CPUInstruction(mnemonic: "STA", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.STA),
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0x8D: CPUInstruction(mnemonic: "STA", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.STA),
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0x9D: CPUInstruction(mnemonic: "STA", cycles: 5, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.STA),
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0x99: CPUInstruction(mnemonic: "STA", cycles: 5, bytes: 3, addressingMode: .absolute_indexed_y, action: Opcodes.STA),
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0x81: CPUInstruction(mnemonic: "STA", cycles: 6, bytes: 2, addressingMode: .indexed_indirect, action: Opcodes.STA),
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0x91: CPUInstruction(mnemonic: "STA", cycles: 6, bytes: 2, addressingMode: .indirect_indexed, action: Opcodes.STA),
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0x86: CPUInstruction(mnemonic: "STX", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.STX),
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0x96: CPUInstruction(mnemonic: "STX", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_y, action: Opcodes.STX),
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0x8E: CPUInstruction(mnemonic: "STX", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.STX),
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0x84: CPUInstruction(mnemonic: "STY", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.STY),
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0x94: CPUInstruction(mnemonic: "STY", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.STY),
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0x8C: CPUInstruction(mnemonic: "STY", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.STY),
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//Compare functions
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0xC9: CPUInstruction(mnemonic: "CMP", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.CMP),
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0xC5: CPUInstruction(mnemonic: "CMP", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.CMP),
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0xD5: CPUInstruction(mnemonic: "CMP", cycles: 4, bytes: 2, addressingMode: .zeropage_indexed_x, action: Opcodes.CMP),
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0xCD: CPUInstruction(mnemonic: "CMP", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.CMP),
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0xDD: CPUInstruction(mnemonic: "CMP", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_x, action: Opcodes.CMP),
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0xD9: CPUInstruction(mnemonic: "CMP", cycles: 4, bytes: 3, addressingMode: .absolute_indexed_y, action: Opcodes.CMP),
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0xC1: CPUInstruction(mnemonic: "CMP", cycles: 6, bytes: 2, addressingMode: .indexed_indirect, action: Opcodes.CMP),
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0xD1: CPUInstruction(mnemonic: "CMP", cycles: 5, bytes: 2, addressingMode: .indirect_indexed, action: Opcodes.CMP),
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0xE0: CPUInstruction(mnemonic: "CPX", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.CPX),
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0xE4: CPUInstruction(mnemonic: "CPX", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.CPX),
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0xEC: CPUInstruction(mnemonic: "CPX", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.CPX),
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0xC0: CPUInstruction(mnemonic: "CPY", cycles: 2, bytes: 2, addressingMode: .immediate, action: Opcodes.CPY),
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0xC4: CPUInstruction(mnemonic: "CPY", cycles: 3, bytes: 2, addressingMode: .zeropage, action: Opcodes.CPY),
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0xCC: CPUInstruction(mnemonic: "CPY", cycles: 4, bytes: 3, addressingMode: .absolute, action: Opcodes.CPY),
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//Register functions
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0x88: CPUInstruction(mnemonic: "DEY", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.DEY),
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0x8A: CPUInstruction(mnemonic: "TXA", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.TXA),
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0x98: CPUInstruction(mnemonic: "TYA", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.TYA),
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0xA8: CPUInstruction(mnemonic: "TAY", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.TAY),
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0xAA: CPUInstruction(mnemonic: "TAX", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.TAX),
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0xC8: CPUInstruction(mnemonic: "INY", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.INY),
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0xCA: CPUInstruction(mnemonic: "DEX", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.DEX),
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0xE8: CPUInstruction(mnemonic: "INX", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.INX),
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//Processor flag instructions
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0x18: CPUInstruction(mnemonic: "CLC", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.CLC),
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0x38: CPUInstruction(mnemonic: "SEC", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.SEC),
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0x58: CPUInstruction(mnemonic: "CLI", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.CLI),
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0x78: CPUInstruction(mnemonic: "SEI", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.SEI),
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0xB8: CPUInstruction(mnemonic: "CLV", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.CLV),
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0xD8: CPUInstruction(mnemonic: "CLD", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.CLD),
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0xF8: CPUInstruction(mnemonic: "SED", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.SED),
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//Stack instructions
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0x9A: CPUInstruction(mnemonic: "TXS", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.TXS),
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0xBA: CPUInstruction(mnemonic: "TSX", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.TSX),
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0x48: CPUInstruction(mnemonic: "PHA", cycles: 3, bytes: 1, addressingMode: .implied, action: Opcodes.PHA),
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0x68: CPUInstruction(mnemonic: "PLA", cycles: 4, bytes: 1, addressingMode: .implied, action: Opcodes.PLA),
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0x08: CPUInstruction(mnemonic: "PHP", cycles: 3, bytes: 1, addressingMode: .implied, action: Opcodes.PHP),
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0x28: CPUInstruction(mnemonic: "PLP", cycles: 4, bytes: 1, addressingMode: .implied, action: Opcodes.PLP),
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//Branch instructions
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0x10: CPUInstruction(mnemonic: "BPL", cycles: 2, bytes: 2, addressingMode: .relative, action: Opcodes.BPL),
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0x30: CPUInstruction(mnemonic: "BMI", cycles: 2, bytes: 2, addressingMode: .relative, action: Opcodes.BMI),
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0x50: CPUInstruction(mnemonic: "BVC", cycles: 2, bytes: 2, addressingMode: .relative, action: Opcodes.BVC),
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0x70: CPUInstruction(mnemonic: "BVS", cycles: 2, bytes: 2, addressingMode: .relative, action: Opcodes.BVS),
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0x90: CPUInstruction(mnemonic: "BCC", cycles: 2, bytes: 2, addressingMode: .relative, action: Opcodes.BCC),
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0xB0: CPUInstruction(mnemonic: "BCS", cycles: 2, bytes: 2, addressingMode: .relative, action: Opcodes.BCS),
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0xD0: CPUInstruction(mnemonic: "BNE", cycles: 2, bytes: 2, addressingMode: .relative, action: Opcodes.BNE),
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0xF0: CPUInstruction(mnemonic: "BEQ", cycles: 2, bytes: 2, addressingMode: .relative, action: Opcodes.BEQ),
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0x20: CPUInstruction(mnemonic: "JSR", cycles: 6, bytes: 3, addressingMode: .absolute, action: Opcodes.JSR),
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0x40: CPUInstruction(mnemonic: "RTI", cycles: 6, bytes: 1, addressingMode: .implied, action: Opcodes.RTI),
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0x60: CPUInstruction(mnemonic: "RTS", cycles: 6, bytes: 1, addressingMode: .implied, action: Opcodes.RTS),
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0x00: CPUInstruction(mnemonic: "BRK", cycles: 7, bytes: 1, addressingMode: .implied, action: Opcodes.BRK),
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0xEA: CPUInstruction(mnemonic: "NOP", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.NOP),
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//Illegal opcodes
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0x1A: CPUInstruction(mnemonic: "NOP", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.NOP),
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0x3A: CPUInstruction(mnemonic: "NOP", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.NOP),
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0x5A: CPUInstruction(mnemonic: "NOP", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.NOP),
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0x7A: CPUInstruction(mnemonic: "NOP", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.NOP),
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0xDA: CPUInstruction(mnemonic: "NOP", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.NOP),
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0xFA: CPUInstruction(mnemonic: "NOP", cycles: 2, bytes: 1, addressingMode: .implied, action: Opcodes.NOP),
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0x82: CPUInstruction(mnemonic: "NOP", cycles: 2, bytes: 2, addressingMode: .implied, action: Opcodes.NOP),
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0xC2: CPUInstruction(mnemonic: "NOP", cycles: 2, bytes: 2, addressingMode: .implied, action: Opcodes.NOP),
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0xE2: CPUInstruction(mnemonic: "NOP", cycles: 2, bytes: 2, addressingMode: .implied, action: Opcodes.NOP),
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//0x07: CPUInstruction(mnemonic: "SLO", cycles: 5, bytes: 2, addressingMode: .zeropage, action: Opcodes.SLO),
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]
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