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https://github.com/nippur72/apple1-videocard-lib.git
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duty cycle monitor
This commit is contained in:
nino-porcino
parent
95d46a7e00
commit
a8e97b5aa3
126
demos/tapemon/tapeload.c
Normal file
126
demos/tapemon/tapeload.c
Normal file
@ -0,0 +1,126 @@
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#include <utils.h>
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#include <apple1.h>
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#pragma start_address(0x3000)
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byte *const HEX1L = 0x24; // End address of dump block
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byte *const HEX1H = 0x25; //
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byte *const HEX2L = 0x26; // Begin address of dump block
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byte *const HEX2H = 0x27; //
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byte *const LASTSTATE = 0x29; // Last input state
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byte *const NUMPULSES = 0x30; // Number of long pulses to sync at the header
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byte *const TAPEIN = 0xC081; // Tape input
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byte *const DSP = 0xD012; // display data port
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void load_from_tape(word start_address, word end_address)
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{
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*((word *)HEX1L) = end_address;
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*((word *)HEX2L) = start_address;
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asm {
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// synchronizes with the short header
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syncstart: lda #24 // 24 cycles (3 bytes of $ff)
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sta NUMPULSES // count 24 cycles pulses
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jsr fullcycle // skip the first full cycle (when looping)
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nextsync: ldy #58 // full cycle duration
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jsr fullcycle // read a full cycle
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bcc syncstart // if short cycle found (c=0), redo from start
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dec NUMPULSES // else long cycle found, decrease count
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bne nextsync // if not 24 cycles, get next cycle
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// else read bit start and 32 bytes of data normally
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// the following routine was copied directly from the ACI ROM
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notstart: ldy #31 // try to detect the much shorter start bit
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jsr cmplevel //
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bcs notstart // start bit not detected yet!
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jsr cmplevel // wait for 2nd phase of start bit
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ldy #58 // set threshold value in middle
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rdbyte: ldx #8 // receiver 8 bits
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rdbit: pha
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jsr fullcycle // detect a full cycle
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pla
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rol // roll new bit into result
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ldy #57 // set threshold value in middle
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dex // decrement bit counter
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bne rdbit // read next bit!
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sta ($26,x) // save new byte *** same as "STA (HEX2L,X)" see KickC bug #756 https://gitlab.com/camelot/kickc/-/issues/756
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jsr incaddr // increment address
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ldy #53 // compensate threshold with workload
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bcc rdbyte // do next byte if not done yet!
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bcs restidx // always taken! restore parse index
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fullcycle: jsr cmplevel // wait for two level changes
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cmplevel: dey // decrement time counter
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lda TAPEIN // get tape in data
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cmp LASTSTATE // same as before?
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beq cmplevel // yes!
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sta LASTSTATE // save new data
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cpy #128 // compare threshold
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rts
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// [...]
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incaddr: lda HEX2L // compare current address with
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cmp HEX1L // end address
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lda HEX2H
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sbc HEX1H
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inc HEX2L // and increment current address
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bne nocarry // no carry to msb!
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inc HEX2H
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nocarry: rts
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// end of read routine "restidx" is the exit point
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restidx: rts
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}
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}
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// converts the hexadecimal string argument to 16 bit word
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word xtow(byte *str) {
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word res=0;
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byte c;
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for(byte i=0; c=str[i]; ++i) {
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res = res << 4;
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if(c<'A') res += (c-'0');
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else res += (c-'A');
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}
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return res;
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}
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byte keybuf[32];
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void main() {
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woz_puts("\r\rTAPE ALTERNATE LOAD\r");
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word start_address;
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word end_address;
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woz_puts("\rSTART ADDRESS: "); apple1_input_line(keybuf, 32); start_address = xtow(keybuf);
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woz_puts("\rEND ADDRESS: "); apple1_input_line(keybuf, 32); end_address = xtow(keybuf);
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end_address += 1; // include checksum byte
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while(1) {
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woz_puts("\r\rPRESS PLAY ON TAPE\r\r");
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load_from_tape(start_address, end_address);
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// calculate checksum
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byte chk = 0xFF;
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for(byte *t=start_address; t<end_address; t++) {
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chk ^= *t;
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}
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if(chk == 0) {
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woz_puts("OK\r");
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break;
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}
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woz_puts("?LOAD ERROR\r\r");
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woz_puts("RETRY ? (Y/N) ");
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if(apple1_getkey()!='Y') break;
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}
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woz_mon();
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}
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@ -1,34 +1,57 @@
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#include <utils.h>
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#include <apple1.h>
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byte *const HEX1L = 0x24; // End address of dump block
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byte *const HEX1H = 0x25; //
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byte *const HEX2L = 0x26; // Begin address of dump block
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byte *const HEX2H = 0x27; //
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byte *const LASTSTATE = 0x29; // Last input state
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byte *const NUMPULSES = 0x30; // Number of long pulses to sync at the header
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byte *const TAPEIN = 0xC081; // Tape input
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byte *const DSP = 0xD012; // display data port
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__address(0x24) word ENDADDR; // End address of dump block
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__address(0x26) word STARTADDR; // Begin address of dump block
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__address(0x29) byte LASTSTATE; // Last input state
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__address(0x30) byte NUMPULSES; // Number of long pulses to sync at the header
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__address(0xC081) byte TAPEIN; // Tape input
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__address(0xD012) byte DSP; // display data port
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#define PACKETSIZE 64
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/*
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#pragma zp_reserve(0x24)
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#pragma zp_reserve(0x25)
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#pragma zp_reserve(0x26)
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#pragma zp_reserve(0x27)
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#pragma zp_reserve(0x29)
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#pragma zp_reserve(0x30)
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const byte *RX_BUFFER = 0x200;
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const byte *RX_BUFFER_END = (0x200+PACKETSIZE-1);
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__export byte *const ENDADDR = (byte *) 0x24; // End address of dump block
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__export byte *const STARTADDR = (byte *) 0x26; // Begin address of dump block
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__export byte *const LASTSTATE = (byte *) 0x29; // Last input state
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__export byte *const NUMPULSES = (byte *) 0x30; // Number of long pulses to sync at the header
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__export byte *const TAPEIN = (byte *) 0xC081; // Tape input
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__export byte *const DSP = (byte *) 0xD012; // display data port
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*/
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byte PACKETSIZE;
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byte reference_packet[256];
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byte *vmeter = "0123456789ABCDEF";
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//byte *const RX_BUFFER = (byte *) 0x060c; //0x4200;
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const byte RX_BUFFER[256]; // TODO ??????????????????????????????????????????
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void read_packet()
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{
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word RX_BUFFER_END = (word) RX_BUFFER + (word) PACKETSIZE - 1;
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ENDADDR = (word) RX_BUFFER_END;
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STARTADDR = (word) RX_BUFFER;
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/*
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*((word *)ENDADDR) = (word) RX_BUFFER_END;
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*((word *)STARTADDR) = (word) RX_BUFFER;
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*/
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/*
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woz_putc('\r');
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woz_print_hex(*(STARTADDR+1)); woz_print_hex(*(STARTADDR));
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woz_putc('.');
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woz_print_hex(*(ENDADDR+1)); woz_print_hex(*(ENDADDR));
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*/
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asm {
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// set READ buffer pointers to $0200-$021F (32 characters)
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lda #<RX_BUFFER_END
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sta HEX1L
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lda #>RX_BUFFER_END
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lda HEX1H
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lda #<RX_BUFFER
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sta HEX2L
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lda #>RX_BUFFER
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lda HEX2H
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// synchronizes with the short header
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syncstart: lda #24 // 24 cycles (3 bytes of $ff)
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@ -56,7 +79,7 @@ rdbit: pha
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ldy #57 // set threshold value in middle
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dex // decrement bit counter
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bne rdbit // read next bit!
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sta ($26,x) // save new byte *** same as "STA (HEX2L,X)" see KickC bug #756 https://gitlab.com/camelot/kickc/-/issues/756
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sta (STARTADDR,x) // save new byte
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jsr incaddr // increment address
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ldy #53 // compensate threshold with workload
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bcc rdbyte // do next byte if not done yet!
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@ -70,14 +93,14 @@ cmplevel: dey // decrement time counter
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cpy #128 // compare threshold
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rts
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// [...]
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incaddr: lda HEX2L // compare current address with
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cmp HEX1L // end address
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lda HEX2H
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sbc HEX1H
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inc HEX2L // and increment current address
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bne nocarry // no carry to msb!
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inc HEX2H
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nocarry: rts
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incaddr: lda <STARTADDR // compare current address with
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cmp <ENDADDR // end address
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lda >STARTADDR
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sbc >ENDADDR // carry set if STARTADDR = ENDADDR
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inc <STARTADDR // increment current address
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bne no_inc_hi //
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inc >STARTADDR
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no_inc_hi: rts
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// end of read routine "restidx" is the exit point
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@ -86,11 +109,10 @@ restidx: rts
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}
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}
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byte reference_packet[PACKETSIZE];
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byte *vmeter = "0123456789ABCDEF";
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void decode_packets() {
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woz_puts("\rPACKET DECODER MONITOR\r");
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// fill the reference packet with the known values
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for(byte t=0;t<PACKETSIZE;t++) reference_packet[t] = t;
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@ -107,7 +129,21 @@ void decode_packets() {
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// display result
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if(i==0) woz_putc('.');
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else if(i==PACKETSIZE) woz_putc('*');
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else woz_putc(vmeter[i>>2]);
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else {
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if(PACKETSIZE == 32) woz_putc(vmeter[i>>1]);
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if(PACKETSIZE == 64) woz_putc(vmeter[i>>2]);
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if(PACKETSIZE == 128) woz_putc(vmeter[i>>3]);
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if(PACKETSIZE == 255) woz_putc(vmeter[i>>4]);
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}
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/*
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if(apple1_readkey()=='D') {
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woz_puts("\r\r");
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for(i=0;i<PACKETSIZE;i++) {
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woz_print_hex(RX_BUFFER[i]); woz_putc(' ');
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}
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}
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*/
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// exit with "X"
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if(apple1_readkey()=='X') break;
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@ -116,6 +152,8 @@ void decode_packets() {
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void simple_toggle_monitor()
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{
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woz_puts("\rTAPE BIT TOGGLE MONITOR\r");
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asm {
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simple_monitor: lda TAPEIN // read tape input
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cmp LASTSTATE // compare to previous state
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@ -130,15 +168,88 @@ no_toggle: bit DSP // check if display is ready to accep
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}
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}
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void main() {
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woz_puts("\r\rTAPE MONITOR\r\r"
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"[1] DECODE PACKETS\r"
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"[2] SIMPLE TOGGLE MONITOR\r\r"
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);
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// store the lengths for each phase
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byte phase0[256];
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byte phase1[256];
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void count_256_phase_lengths() {
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asm {
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ldx #0 // count pulses
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countpulse: ldy #00 // phase length
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lphase0: iny // decrement phase length
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lda TAPEIN // get tape in data
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cmp LASTSTATE // same as before?
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beq lphase0 // yes, keep counting
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sta LASTSTATE // save new state
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tya
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sta phase0,x // save phase0 length
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ldy #00 // phase length
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lphase1: iny // decrement phase length
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lda TAPEIN // get tape in data
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cmp LASTSTATE // same as before?
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beq lphase1 // yes, keep counting
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sta LASTSTATE // save new state
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tya
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sta phase1,x // save phase0 length
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inx
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bne countpulse // if not 256, repeat
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while(1) {
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byte key = apple1_getkey();
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if(key == '1') decode_packets();
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if(key == '2') simple_toggle_monitor();
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}
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}
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void duty_cycle_monitor() {
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woz_puts("\rDUTY CYCLE MONITOR\r");
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while(1) {
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count_256_phase_lengths();
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// don't consider the first phase, because it's measured during transition
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phase0[0] = phase0[1];
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phase1[0] = phase1[1];
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word sum_0 = 0;
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word sum_1 = 0;
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byte i=0;
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do {
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sum_0 += phase0[i];
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sum_1 += phase1[i];
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i++;
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} while(i!=255);
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// make average
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sum_0 = sum_0 / 256;
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sum_1 = sum_1 / 256;
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// display result in 5 columns
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woz_print_hex((byte)sum_0);
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woz_putc('-');
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woz_print_hex((byte)sum_1);
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woz_puts(" ");
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byte k = apple1_readkey();
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if(k=='X') break;
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}
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}
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void main() {
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while(1) {
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woz_puts("\r\rTAPE MONITOR\r\r"
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"1,2,3,4 => 32,64,128,255 BYTES PACKETS\r"
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"T SIMPLE TOGGLE MONITOR\r"
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"D DUTY CYLE MONITOR\r\r"
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"X EXIT\r\r"
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);
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byte key = apple1_getkey();
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if(key == '1') { PACKETSIZE = 32; decode_packets(); }
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if(key == '2') { PACKETSIZE = 64; decode_packets(); }
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if(key == '3') { PACKETSIZE = 128; decode_packets(); }
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if(key == '4') { PACKETSIZE = 255; decode_packets(); }
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if(key == 'T') simple_toggle_monitor();
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if(key == 'D') duty_cycle_monitor();
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if(key == 'X') woz_mon();
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}
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}
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