diff --git a/AppleIIGateSch/AppleIIGateSch.gise b/AppleIIGateSch/AppleIIGateSch.gise
new file mode 100644
index 0000000..701deb5
--- /dev/null
+++ b/AppleIIGateSch/AppleIIGateSch.gise
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="AppleIIGateSch.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="ClockVideoGenerator_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="chip74LS161_guide.ncd" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/AppleIIGateSch/AppleIIGateSch.xise b/AppleIIGateSch/AppleIIGateSch.xise
new file mode 100644
index 0000000..0257aed
--- /dev/null
+++ b/AppleIIGateSch/AppleIIGateSch.xise
@@ -0,0 +1,408 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="chip74LS161.sch" xil_pn:type="FILE_SCHEMATIC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="JK_FlipFlop.sch" xil_pn:type="FILE_SCHEMATIC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="JK_FlipFlop_tb.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="chip74LS161_tb.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="56"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="56"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="56"/>
+    </file>
+    <file xil_pn:name="chip74LS175.sch" xil_pn:type="FILE_SCHEMATIC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="chip74LS175_tb.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="70"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="70"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="70"/>
+    </file>
+    <file xil_pn:name="chipi74LS153.sch" xil_pn:type="FILE_SCHEMATIC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="chip74LS153_tb.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="75"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="75"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/>
+    </file>
+    <file xil_pn:name="chip74S195.sch" xil_pn:type="FILE_SCHEMATIC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="chip74S195_tb.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="94"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="94"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="94"/>
+    </file>
+    <file xil_pn:name="ClockVideoGenerator.sch" xil_pn:type="FILE_SCHEMATIC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
+    <file xil_pn:name="ClockVideoGenerator_tb.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="90"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="90"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="90"/>
+    </file>
+    <file xil_pn:name="chip74LS257.sch" xil_pn:type="FILE_SCHEMATIC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="chip74LS257_tb.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="72"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="72"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|ClockVideoGenerator" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="ClockVideoGenerator.sch" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ClockVideoGenerator" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="ClockVideoGenerator" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="ClockVideoGenerator_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="ClockVideoGenerator_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="ClockVideoGenerator_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="ClockVideoGenerator_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="Schematic entry of apple II from Apple II schematic. Using 74 series chips. Can't find a library of 74 series chips so will have to make my own verilog representations of them. &#xA;&#xA;Plan on using gate diagrams of the chips.. Not verilog descriptions. TTL diagrams always seem to have internal gate level representation of 74 sereis logic chips.&#xA;&#xA;Goal will be that if an Apple expansion connector is connected to the design that real Apple cards will be usable.. Of course voltage level shifters and what not will be needed.&#xA;&#xA;Hmm composite video signal is generated.. To use VGA port will need to translate composite signal to colors. I think there was a VHDL Apple II on an Altera board that might maybe have a module that does that.. Although looking at it I think it was a functional not gate level model so might not generate composite signal.&#xA;&#xA;May the force be with you." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/chip74LS257_chip74LS257_sch_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.chip74LS257_chip74LS257_sch_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="30000 ns" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.chip74LS257_chip74LS257_sch_tb" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="Schematic" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|chip74LS257_chip74LS257_sch_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIIGateSch" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-05-21T16:09:30" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5D23A760673F46A08FD1BCCFE9330768" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/AppleIIGateSch/ClockVideoGenerator.sch b/AppleIIGateSch/ClockVideoGenerator.sch
new file mode 100644
index 0000000..64c1340
--- /dev/null
+++ b/AppleIIGateSch/ClockVideoGenerator.sch
@@ -0,0 +1,940 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+    <attr value="spartan3e" name="DeviceFamilyName">
+        <trait delete="all:0" />
+        <trait editname="all:0" />
+        <trait edittrait="all:0" />
+    </attr>
+    <netlist>
+        <signal name="XLXN_1" />
+        <signal name="XLXN_3" />
+        <signal name="XLXN_4" />
+        <signal name="XLXN_5" />
+        <signal name="XLXN_6" />
+        <signal name="SOFT5_A2_11" />
+        <signal name="XLXN_10" />
+        <signal name="XLXN_11" />
+        <signal name="XLXN_12" />
+        <signal name="XLXN_13" />
+        <signal name="XLXN_14" />
+        <signal name="VA" />
+        <signal name="XLXN_17" />
+        <signal name="V5" />
+        <signal name="V4" />
+        <signal name="V3" />
+        <signal name="V2" />
+        <signal name="V1" />
+        <signal name="V0" />
+        <signal name="VC" />
+        <signal name="VB" />
+        <signal name="H5" />
+        <signal name="H4" />
+        <signal name="H3" />
+        <signal name="H2" />
+        <signal name="H1" />
+        <signal name="H0" />
+        <signal name="SOFT5_A2_8" />
+        <signal name="XLXN_35" />
+        <signal name="XLXN_36" />
+        <signal name="RASn" />
+        <signal name="CASn" />
+        <signal name="AX" />
+        <signal name="XLXN_44" />
+        <signal name="Q3" />
+        <signal name="XLXN_46" />
+        <signal name="LDPSn" />
+        <signal name="LD194" />
+        <signal name="XLXN_52" />
+        <signal name="XLXN_54" />
+        <signal name="PHI0" />
+        <signal name="PHI1" />
+        <signal name="XLXN_62" />
+        <signal name="COLOR_REF" />
+        <signal name="XLXN_64" />
+        <signal name="c7M" />
+        <signal name="c7Mn" />
+        <signal name="XLXN_70" />
+        <signal name="XLXN_72" />
+        <signal name="XLXN_76" />
+        <signal name="CLK_14o3M" />
+        <signal name="XLXN_78" />
+        <signal name="XLXN_79" />
+        <signal name="XLXN_81" />
+        <signal name="XLXN_82" />
+        <signal name="XLXN_84" />
+        <signal name="XLXN_86" />
+        <signal name="XLXN_87" />
+        <port polarity="Input" name="SOFT5_A2_11" />
+        <port polarity="Output" name="VA" />
+        <port polarity="Output" name="V5" />
+        <port polarity="Output" name="V4" />
+        <port polarity="Output" name="V3" />
+        <port polarity="Output" name="V2" />
+        <port polarity="Output" name="V1" />
+        <port polarity="Output" name="V0" />
+        <port polarity="Output" name="VC" />
+        <port polarity="Output" name="VB" />
+        <port polarity="Output" name="H5" />
+        <port polarity="Output" name="H4" />
+        <port polarity="Output" name="H3" />
+        <port polarity="Output" name="H2" />
+        <port polarity="Output" name="H1" />
+        <port polarity="Output" name="H0" />
+        <port polarity="Input" name="SOFT5_A2_8" />
+        <port polarity="Output" name="RASn" />
+        <port polarity="Output" name="CASn" />
+        <port polarity="Output" name="AX" />
+        <port polarity="Output" name="Q3" />
+        <port polarity="Output" name="LDPSn" />
+        <port polarity="Output" name="LD194" />
+        <port polarity="Output" name="PHI0" />
+        <port polarity="Output" name="PHI1" />
+        <port polarity="Output" name="COLOR_REF" />
+        <port polarity="Output" name="c7M" />
+        <port polarity="Output" name="c7Mn" />
+        <port polarity="Input" name="CLK_14o3M" />
+        <blockdef name="chip74LS161">
+            <timestamp>2018-5-24T4:42:36</timestamp>
+            <rect width="256" x="64" y="-512" height="512" />
+            <line x2="384" y1="-32" y2="-32" x1="320" />
+            <line x2="0" y1="-32" y2="-32" x1="64" />
+            <line x2="384" y1="-96" y2="-96" x1="320" />
+            <line x2="0" y1="-96" y2="-96" x1="64" />
+            <line x2="384" y1="-224" y2="-224" x1="320" />
+            <line x2="384" y1="-288" y2="-288" x1="320" />
+            <line x2="384" y1="-352" y2="-352" x1="320" />
+            <line x2="384" y1="-416" y2="-416" x1="320" />
+            <line x2="384" y1="-160" y2="-160" x1="320" />
+            <line x2="0" y1="-224" y2="-224" x1="64" />
+            <line x2="0" y1="-288" y2="-288" x1="64" />
+            <line x2="0" y1="-352" y2="-352" x1="64" />
+            <line x2="0" y1="-416" y2="-416" x1="64" />
+            <line x2="0" y1="-480" y2="-480" x1="64" />
+        </blockdef>
+        <blockdef name="inv">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="160" y1="-32" y2="-32" x1="224" />
+            <line x2="128" y1="-64" y2="-32" x1="64" />
+            <line x2="64" y1="-32" y2="0" x1="128" />
+            <line x2="64" y1="0" y2="-64" x1="64" />
+            <circle r="16" cx="144" cy="-32" />
+        </blockdef>
+        <blockdef name="gnd">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-96" x1="64" />
+            <line x2="52" y1="-48" y2="-48" x1="76" />
+            <line x2="60" y1="-32" y2="-32" x1="68" />
+            <line x2="40" y1="-64" y2="-64" x1="88" />
+            <line x2="64" y1="-64" y2="-80" x1="64" />
+            <line x2="64" y1="-128" y2="-96" x1="64" />
+        </blockdef>
+        <blockdef name="vcc">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-32" y2="-64" x1="64" />
+            <line x2="64" y1="0" y2="-32" x1="64" />
+            <line x2="32" y1="-64" y2="-64" x1="96" />
+        </blockdef>
+        <blockdef name="xor2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="60" y1="-128" y2="-128" x1="0" />
+            <line x2="208" y1="-96" y2="-96" x1="256" />
+            <arc ex="44" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
+            <arc ex="64" ey="-144" sx="64" sy="-48" r="56" cx="32" cy="-96" />
+            <line x2="64" y1="-144" y2="-144" x1="128" />
+            <line x2="64" y1="-48" y2="-48" x1="128" />
+            <arc ex="128" ey="-144" sx="208" sy="-96" r="88" cx="132" cy="-56" />
+            <arc ex="208" ey="-96" sx="128" sy="-48" r="88" cx="132" cy="-136" />
+        </blockdef>
+        <blockdef name="nand4">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="64" y1="-256" y2="-256" x1="0" />
+            <line x2="216" y1="-160" y2="-160" x1="256" />
+            <circle r="12" cx="204" cy="-160" />
+            <line x2="64" y1="-64" y2="-256" x1="64" />
+            <line x2="144" y1="-208" y2="-208" x1="64" />
+            <arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
+            <line x2="64" y1="-112" y2="-112" x1="144" />
+        </blockdef>
+        <blockdef name="chip74S195">
+            <timestamp>2018-6-3T18:32:16</timestamp>
+            <rect width="256" x="64" y="-512" height="512" />
+            <line x2="384" y1="-96" y2="-96" x1="320" />
+            <line x2="0" y1="-96" y2="-96" x1="64" />
+            <line x2="0" y1="-32" y2="-32" x1="64" />
+            <line x2="384" y1="-32" y2="-32" x1="320" />
+            <line x2="0" y1="-288" y2="-288" x1="64" />
+            <line x2="0" y1="-352" y2="-352" x1="64" />
+            <line x2="0" y1="-416" y2="-416" x1="64" />
+            <line x2="0" y1="-480" y2="-480" x1="64" />
+            <line x2="384" y1="-224" y2="-224" x1="320" />
+            <line x2="384" y1="-288" y2="-288" x1="320" />
+            <line x2="384" y1="-352" y2="-352" x1="320" />
+            <line x2="384" y1="-480" y2="-480" x1="320" />
+            <line x2="384" y1="-416" y2="-416" x1="320" />
+            <line x2="0" y1="-224" y2="-224" x1="64" />
+            <circle r="12" cx="56" cy="-224" />
+            <circle r="12" cx="332" cy="-98" />
+            <circle r="12" cx="332" cy="-34" />
+            <circle r="12" cx="332" cy="-482" />
+        </blockdef>
+        <blockdef name="nand2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="216" y1="-96" y2="-96" x1="256" />
+            <circle r="12" cx="204" cy="-96" />
+            <line x2="64" y1="-48" y2="-144" x1="64" />
+            <line x2="144" y1="-144" y2="-144" x1="64" />
+            <line x2="64" y1="-48" y2="-48" x1="144" />
+            <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+        </blockdef>
+        <blockdef name="and3">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="192" y1="-128" y2="-128" x1="256" />
+            <line x2="144" y1="-176" y2="-176" x1="64" />
+            <line x2="64" y1="-80" y2="-80" x1="144" />
+            <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+            <line x2="64" y1="-64" y2="-192" x1="64" />
+        </blockdef>
+        <blockdef name="nor2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="216" y1="-96" y2="-96" x1="256" />
+            <circle r="12" cx="204" cy="-96" />
+            <arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
+            <arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
+            <arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
+            <line x2="48" y1="-48" y2="-48" x1="112" />
+            <line x2="48" y1="-144" y2="-144" x1="112" />
+        </blockdef>
+        <blockdef name="chipi74LS153">
+            <timestamp>2018-6-4T6:43:36</timestamp>
+            <rect width="256" x="64" y="-576" height="576" />
+            <line x2="384" y1="-224" y2="-224" x1="320" />
+            <line x2="384" y1="-160" y2="-160" x1="320" />
+            <line x2="384" y1="-96" y2="-96" x1="320" />
+            <line x2="384" y1="-32" y2="-32" x1="320" />
+            <line x2="384" y1="-544" y2="-544" x1="320" />
+            <line x2="384" y1="-480" y2="-480" x1="320" />
+            <line x2="384" y1="-416" y2="-416" x1="320" />
+            <line x2="384" y1="-352" y2="-352" x1="320" />
+            <line x2="0" y1="-288" y2="-288" x1="64" />
+            <line x2="0" y1="-352" y2="-352" x1="64" />
+            <line x2="0" y1="-544" y2="-544" x1="64" />
+            <line x2="0" y1="-32" y2="-32" x1="64" />
+            <line x2="0" y1="-224" y2="-224" x1="64" />
+            <line x2="0" y1="-480" y2="-480" x1="64" />
+            <circle r="12" cx="56" cy="-352" />
+            <circle r="12" cx="56" cy="-288" />
+        </blockdef>
+        <blockdef name="chip74LS175">
+            <timestamp>2018-5-27T1:40:50</timestamp>
+            <rect width="256" x="64" y="-512" height="512" />
+            <line x2="0" y1="-416" y2="-416" x1="64" />
+            <line x2="0" y1="-480" y2="-480" x1="64" />
+            <line x2="0" y1="-160" y2="-160" x1="64" />
+            <line x2="0" y1="-224" y2="-224" x1="64" />
+            <line x2="0" y1="-288" y2="-288" x1="64" />
+            <line x2="0" y1="-352" y2="-352" x1="64" />
+            <line x2="384" y1="-32" y2="-32" x1="320" />
+            <line x2="384" y1="-96" y2="-96" x1="320" />
+            <line x2="384" y1="-160" y2="-160" x1="320" />
+            <line x2="384" y1="-224" y2="-224" x1="320" />
+            <line x2="384" y1="-288" y2="-288" x1="320" />
+            <line x2="384" y1="-352" y2="-352" x1="320" />
+            <line x2="384" y1="-416" y2="-416" x1="320" />
+            <line x2="384" y1="-480" y2="-480" x1="320" />
+            <circle r="10" cx="54" cy="-418" />
+            <circle r="8" cx="332" cy="-480" />
+            <circle r="10" cx="330" cy="-352" />
+            <circle r="8" cx="332" cy="-224" />
+            <circle r="8" cx="332" cy="-100" />
+        </blockdef>
+        <block symbolname="chip74LS161" name="D14_74LS161">
+            <blockpin signalname="SOFT5_A2_11" name="CEP" />
+            <blockpin signalname="SOFT5_A2_11" name="CET" />
+            <blockpin signalname="LDPSn" name="CLK" />
+            <blockpin signalname="SOFT5_A2_11" name="CLRn" />
+            <blockpin signalname="XLXN_11" name="P0" />
+            <blockpin signalname="XLXN_11" name="P1" />
+            <blockpin signalname="XLXN_11" name="P2" />
+            <blockpin signalname="XLXN_11" name="P3" />
+            <blockpin signalname="XLXN_10" name="PEn" />
+            <blockpin signalname="H0" name="Q0" />
+            <blockpin signalname="H1" name="Q1" />
+            <blockpin signalname="H2" name="Q2" />
+            <blockpin signalname="H3" name="Q3" />
+            <blockpin signalname="XLXN_1" name="TC" />
+        </block>
+        <block symbolname="chip74LS161" name="D13_74LS161">
+            <blockpin signalname="XLXN_1" name="CEP" />
+            <blockpin signalname="XLXN_1" name="CET" />
+            <blockpin signalname="LDPSn" name="CLK" />
+            <blockpin signalname="SOFT5_A2_11" name="CLRn" />
+            <blockpin signalname="XLXN_12" name="P0" />
+            <blockpin signalname="XLXN_12" name="P1" />
+            <blockpin signalname="SOFT5_A2_11" name="P2" />
+            <blockpin signalname="VA" name="P3" />
+            <blockpin signalname="XLXN_10" name="PEn" />
+            <blockpin signalname="H4" name="Q0" />
+            <blockpin signalname="H5" name="Q1" />
+            <blockpin signalname="XLXN_10" name="Q2" />
+            <blockpin signalname="VA" name="Q3" />
+            <blockpin signalname="XLXN_3" name="TC" />
+        </block>
+        <block symbolname="chip74LS161" name="D12_74LS161">
+            <blockpin signalname="XLXN_3" name="CEP" />
+            <blockpin signalname="XLXN_3" name="CET" />
+            <blockpin signalname="LDPSn" name="CLK" />
+            <blockpin signalname="SOFT5_A2_11" name="CLRn" />
+            <blockpin signalname="XLXN_17" name="P0" />
+            <blockpin signalname="XLXN_13" name="P1" />
+            <blockpin signalname="XLXN_3" name="P2" />
+            <blockpin signalname="XLXN_17" name="P3" />
+            <blockpin signalname="XLXN_6" name="PEn" />
+            <blockpin signalname="VB" name="Q0" />
+            <blockpin signalname="VC" name="Q1" />
+            <blockpin signalname="V0" name="Q2" />
+            <blockpin signalname="V1" name="Q3" />
+            <blockpin signalname="XLXN_4" name="TC" />
+        </block>
+        <block symbolname="chip74LS161" name="D11_74LS161">
+            <blockpin signalname="XLXN_4" name="CEP" />
+            <blockpin signalname="XLXN_4" name="CET" />
+            <blockpin signalname="LDPSn" name="CLK" />
+            <blockpin signalname="SOFT5_A2_11" name="CLRn" />
+            <blockpin signalname="XLXN_17" name="P0" />
+            <blockpin signalname="XLXN_4" name="P1" />
+            <blockpin signalname="XLXN_4" name="P2" />
+            <blockpin signalname="XLXN_14" name="P3" />
+            <blockpin signalname="XLXN_6" name="PEn" />
+            <blockpin signalname="V2" name="Q0" />
+            <blockpin signalname="V3" name="Q1" />
+            <blockpin signalname="V4" name="Q2" />
+            <blockpin signalname="V5" name="Q3" />
+            <blockpin signalname="XLXN_5" name="TC" />
+        </block>
+        <block symbolname="inv" name="C11_4of6_74LS04">
+            <blockpin signalname="XLXN_5" name="I" />
+            <blockpin signalname="XLXN_6" name="O" />
+        </block>
+        <block symbolname="gnd" name="XLXI_6">
+            <blockpin signalname="XLXN_11" name="G" />
+        </block>
+        <block symbolname="gnd" name="XLXI_7">
+            <blockpin signalname="XLXN_12" name="G" />
+        </block>
+        <block symbolname="gnd" name="XLXI_8">
+            <blockpin signalname="XLXN_13" name="G" />
+        </block>
+        <block symbolname="gnd" name="XLXI_10">
+            <blockpin signalname="XLXN_14" name="G" />
+        </block>
+        <block symbolname="vcc" name="XLXI_12">
+            <blockpin signalname="XLXN_17" name="P" />
+        </block>
+        <block symbolname="xor2" name="B2_2of4_74S86">
+            <blockpin signalname="SOFT5_A2_8" name="I0" />
+            <blockpin signalname="XLXN_10" name="I1" />
+            <blockpin signalname="XLXN_35" name="O" />
+        </block>
+        <block symbolname="nand4" name="D2_1of4_74LS20">
+            <blockpin signalname="XLXN_87" name="I0" />
+            <blockpin signalname="PHI0" name="I1" />
+            <blockpin signalname="XLXN_35" name="I2" />
+            <blockpin signalname="XLXN_46" name="I3" />
+            <blockpin signalname="XLXN_36" name="O" />
+        </block>
+        <block symbolname="chip74S195" name="XLXI_15">
+            <blockpin signalname="SOFT5_A2_8" name="CLRn_1" />
+            <blockpin signalname="XLXN_76" name="CP_10" />
+            <blockpin signalname="XLXN_44" name="J_2" />
+            <blockpin signalname="XLXN_44" name="K_3" />
+            <blockpin signalname="AX" name="P0_4" />
+            <blockpin signalname="XLXN_36" name="P1_5" />
+            <blockpin signalname="AX" name="P2_6" />
+            <blockpin signalname="RASn" name="P3_7" />
+            <blockpin signalname="RASn" name="Q0_15" />
+            <blockpin signalname="AX" name="Q1_14" />
+            <blockpin signalname="CASn" name="Q2_13" />
+            <blockpin signalname="XLXN_54" name="Q3n_11" />
+            <blockpin signalname="Q3" name="Q3_12" />
+            <blockpin signalname="Q3" name="SH_LDn" />
+        </block>
+        <block symbolname="nand2" name="A2_1of4_74LS08">
+            <blockpin signalname="XLXN_46" name="I0" />
+            <blockpin signalname="PHI0" name="I1" />
+            <blockpin signalname="LDPSn" name="O" />
+        </block>
+        <block symbolname="and3" name="B12_2of4_74LS11">
+            <blockpin signalname="c7Mn" name="I0" />
+            <blockpin signalname="XLXN_46" name="I1" />
+            <blockpin signalname="PHI0" name="I2" />
+            <blockpin signalname="LD194" name="O" />
+        </block>
+        <block symbolname="nor2" name="B13_3of4_74LS02">
+            <blockpin signalname="CASn" name="I0" />
+            <blockpin signalname="AX" name="I1" />
+            <blockpin signalname="XLXN_46" name="O" />
+        </block>
+        <block symbolname="gnd" name="XLXI_19">
+            <blockpin signalname="XLXN_44" name="G" />
+        </block>
+        <block symbolname="chipi74LS153" name="C1_74LS153">
+            <blockpin signalname="XLXN_82" name="a0_6" />
+            <blockpin signalname="XLXN_82" name="a1_5" />
+            <blockpin signalname="XLXN_82" name="a2_4" />
+            <blockpin signalname="XLXN_82" name="a3_3" />
+            <blockpin signalname="XLXN_62" name="b0_10" />
+            <blockpin signalname="XLXN_54" name="b1_11" />
+            <blockpin signalname="XLXN_62" name="b2_12" />
+            <blockpin signalname="Q3" name="b3_13" />
+            <blockpin signalname="XLXN_79" name="Ean_11" />
+            <blockpin signalname="XLXN_52" name="Ebn_15" />
+            <blockpin signalname="AX" name="S0_14" />
+            <blockpin signalname="PHI0" name="S1_2" />
+            <blockpin name="Za_7" />
+            <blockpin signalname="XLXN_72" name="Zb_9" />
+        </block>
+        <block symbolname="gnd" name="XLXI_21">
+            <blockpin signalname="XLXN_52" name="G" />
+        </block>
+        <block symbolname="chip74LS175" name="XLXI_22">
+            <blockpin signalname="SOFT5_A2_8" name="CLRn" />
+            <blockpin signalname="XLXN_76" name="CP" />
+            <blockpin signalname="c7Mn" name="D0" />
+            <blockpin signalname="XLXN_64" name="D1" />
+            <blockpin signalname="XLXN_72" name="D2" />
+            <blockpin signalname="XLXN_62" name="D3" />
+            <blockpin signalname="c7M" name="Q0" />
+            <blockpin signalname="c7Mn" name="Q0n" />
+            <blockpin signalname="XLXN_87" name="Q1" />
+            <blockpin signalname="COLOR_REF" name="Q1n" />
+            <blockpin signalname="XLXN_62" name="Q2" />
+            <blockpin name="Q2n" />
+            <blockpin signalname="PHI0" name="Q3" />
+            <blockpin signalname="PHI1" name="Q3n" />
+        </block>
+        <block symbolname="xor2" name="B2_1of4_74S86">
+            <blockpin signalname="c7M" name="I0" />
+            <blockpin signalname="XLXN_87" name="I1" />
+            <blockpin signalname="XLXN_64" name="O" />
+        </block>
+        <block symbolname="xor2" name="B2_3of4_74S86">
+            <blockpin signalname="XLXN_78" name="I0" />
+            <blockpin signalname="CLK_14o3M" name="I1" />
+            <blockpin signalname="XLXN_76" name="O" />
+        </block>
+        <block symbolname="gnd" name="XLXI_25">
+            <blockpin signalname="XLXN_78" name="G" />
+        </block>
+        <block symbolname="vcc" name="XLXI_26">
+            <blockpin signalname="XLXN_79" name="P" />
+        </block>
+        <block symbolname="vcc" name="XLXI_27">
+            <blockpin signalname="XLXN_82" name="P" />
+        </block>
+    </netlist>
+    <sheet sheetnum="1" width="3520" height="2720">
+        <instance x="656" y="656" name="D11_74LS161" orien="R0">
+            <attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="176" y="-528" type="instance" />
+        </instance>
+        <instance x="656" y="1280" name="D12_74LS161" orien="R0">
+            <attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="144" y="-528" type="instance" />
+        </instance>
+        <instance x="656" y="1920" name="D13_74LS161" orien="R0">
+            <attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="144" y="-528" type="instance" />
+        </instance>
+        <instance x="656" y="2560" name="D14_74LS161" orien="R0">
+            <attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="128" y="-528" type="instance" />
+        </instance>
+        <branch name="XLXN_1">
+            <wire x2="656" y1="1888" y2="1888" x1="640" />
+            <wire x2="640" y1="1888" y2="1984" x1="640" />
+            <wire x2="640" y1="1984" y2="2080" x1="640" />
+            <wire x2="656" y1="2080" y2="2080" x1="640" />
+            <wire x2="1072" y1="1984" y2="1984" x1="640" />
+            <wire x2="1072" y1="1888" y2="1888" x1="1040" />
+            <wire x2="1072" y1="1888" y2="1984" x1="1072" />
+        </branch>
+        <branch name="XLXN_3">
+            <wire x2="656" y1="1248" y2="1248" x1="640" />
+            <wire x2="640" y1="1248" y2="1312" x1="640" />
+            <wire x2="640" y1="1312" y2="1440" x1="640" />
+            <wire x2="656" y1="1440" y2="1440" x1="640" />
+            <wire x2="1216" y1="1312" y2="1312" x1="640" />
+            <wire x2="1216" y1="928" y2="928" x1="1040" />
+            <wire x2="1216" y1="928" y2="1248" x1="1216" />
+            <wire x2="1216" y1="1248" y2="1312" x1="1216" />
+            <wire x2="1216" y1="1248" y2="1248" x1="1040" />
+        </branch>
+        <branch name="XLXN_4">
+            <wire x2="656" y1="624" y2="624" x1="640" />
+            <wire x2="640" y1="624" y2="688" x1="640" />
+            <wire x2="640" y1="688" y2="800" x1="640" />
+            <wire x2="656" y1="800" y2="800" x1="640" />
+            <wire x2="1120" y1="688" y2="688" x1="640" />
+            <wire x2="1120" y1="304" y2="304" x1="1040" />
+            <wire x2="1120" y1="304" y2="368" x1="1120" />
+            <wire x2="1120" y1="368" y2="624" x1="1120" />
+            <wire x2="1120" y1="624" y2="688" x1="1120" />
+            <wire x2="1120" y1="368" y2="368" x1="1040" />
+            <wire x2="1120" y1="624" y2="624" x1="1040" />
+        </branch>
+        <instance x="656" y="128" name="C11_4of6_74LS04" orien="R0">
+            <attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="-192" y="-48" type="instance" />
+        </instance>
+        <branch name="XLXN_5">
+            <wire x2="656" y1="96" y2="96" x1="640" />
+            <wire x2="640" y1="96" y2="176" x1="640" />
+            <wire x2="656" y1="176" y2="176" x1="640" />
+        </branch>
+        <branch name="XLXN_6">
+            <wire x2="1248" y1="96" y2="96" x1="880" />
+            <wire x2="1248" y1="96" y2="496" x1="1248" />
+            <wire x2="1248" y1="496" y2="1120" x1="1248" />
+            <wire x2="1248" y1="496" y2="496" x1="1040" />
+            <wire x2="1248" y1="1120" y2="1120" x1="1040" />
+        </branch>
+        <iomarker fontsize="28" x="384" y="2464" name="SOFT5_A2_11" orien="R180" />
+        <branch name="XLXN_10">
+            <wire x2="1216" y1="1344" y2="1344" x1="560" />
+            <wire x2="1216" y1="1344" y2="1760" x1="1216" />
+            <wire x2="1216" y1="1760" y2="2400" x1="1216" />
+            <wire x2="560" y1="1344" y2="1360" x1="560" />
+            <wire x2="560" y1="1360" y2="1568" x1="560" />
+            <wire x2="656" y1="1568" y2="1568" x1="560" />
+            <wire x2="1072" y1="1360" y2="1360" x1="560" />
+            <wire x2="1216" y1="1760" y2="1760" x1="1040" />
+            <wire x2="1216" y1="2400" y2="2400" x1="1040" />
+            <wire x2="1376" y1="640" y2="640" x1="1072" />
+            <wire x2="1072" y1="640" y2="992" x1="1072" />
+            <wire x2="1072" y1="992" y2="1360" x1="1072" />
+        </branch>
+        <branch name="XLXN_11">
+            <wire x2="1056" y1="2144" y2="2144" x1="1040" />
+            <wire x2="1056" y1="2144" y2="2208" x1="1056" />
+            <wire x2="1056" y1="2208" y2="2272" x1="1056" />
+            <wire x2="1056" y1="2272" y2="2336" x1="1056" />
+            <wire x2="1056" y1="2208" y2="2208" x1="1040" />
+            <wire x2="1056" y1="2272" y2="2272" x1="1040" />
+            <wire x2="1056" y1="2336" y2="2336" x1="1040" />
+        </branch>
+        <instance x="1184" y="2208" name="XLXI_6" orien="R270" />
+        <branch name="XLXN_12">
+            <wire x2="1056" y1="1632" y2="1632" x1="1040" />
+            <wire x2="1056" y1="1632" y2="1696" x1="1056" />
+            <wire x2="1056" y1="1696" y2="1696" x1="1040" />
+        </branch>
+        <instance x="1184" y="1696" name="XLXI_7" orien="R270" />
+        <branch name="XLXN_13">
+            <wire x2="1072" y1="992" y2="992" x1="1040" />
+        </branch>
+        <instance x="1200" y="1056" name="XLXI_8" orien="R270" />
+        <branch name="XLXN_14">
+            <wire x2="1072" y1="240" y2="240" x1="1040" />
+        </branch>
+        <instance x="1200" y="304" name="XLXI_10" orien="R270" />
+        <branch name="VA">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="1504" type="branch" />
+            <wire x2="448" y1="1504" y2="1504" x1="400" />
+            <wire x2="480" y1="1504" y2="1504" x1="448" />
+            <wire x2="656" y1="1504" y2="1504" x1="480" />
+            <wire x2="1168" y1="1376" y2="1376" x1="480" />
+            <wire x2="1168" y1="1376" y2="1504" x1="1168" />
+            <wire x2="480" y1="1376" y2="1504" x1="480" />
+            <wire x2="1168" y1="1504" y2="1504" x1="1040" />
+        </branch>
+        <branch name="XLXN_17">
+            <wire x2="1312" y1="432" y2="432" x1="1040" />
+            <wire x2="1312" y1="432" y2="864" x1="1312" />
+            <wire x2="1312" y1="864" y2="1056" x1="1312" />
+            <wire x2="1312" y1="864" y2="864" x1="1040" />
+            <wire x2="1312" y1="1056" y2="1056" x1="1040" />
+        </branch>
+        <branch name="V5">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="240" type="branch" />
+            <wire x2="448" y1="240" y2="240" x1="368" />
+            <wire x2="656" y1="240" y2="240" x1="448" />
+        </branch>
+        <branch name="V4">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="304" type="branch" />
+            <wire x2="448" y1="304" y2="304" x1="368" />
+            <wire x2="656" y1="304" y2="304" x1="448" />
+        </branch>
+        <branch name="V3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="368" type="branch" />
+            <wire x2="448" y1="368" y2="368" x1="368" />
+            <wire x2="656" y1="368" y2="368" x1="448" />
+        </branch>
+        <branch name="V2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="432" type="branch" />
+            <wire x2="448" y1="432" y2="432" x1="368" />
+            <wire x2="656" y1="432" y2="432" x1="448" />
+        </branch>
+        <branch name="V1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="864" type="branch" />
+            <wire x2="448" y1="864" y2="864" x1="400" />
+            <wire x2="656" y1="864" y2="864" x1="448" />
+        </branch>
+        <branch name="V0">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="928" type="branch" />
+            <wire x2="448" y1="928" y2="928" x1="400" />
+            <wire x2="656" y1="928" y2="928" x1="448" />
+        </branch>
+        <branch name="VC">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="992" type="branch" />
+            <wire x2="448" y1="992" y2="992" x1="400" />
+            <wire x2="656" y1="992" y2="992" x1="448" />
+        </branch>
+        <branch name="VB">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="1056" type="branch" />
+            <wire x2="448" y1="1056" y2="1056" x1="400" />
+            <wire x2="656" y1="1056" y2="1056" x1="448" />
+        </branch>
+        <branch name="H5">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="1632" type="branch" />
+            <wire x2="448" y1="1632" y2="1632" x1="400" />
+            <wire x2="656" y1="1632" y2="1632" x1="448" />
+        </branch>
+        <branch name="H4">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="1696" type="branch" />
+            <wire x2="448" y1="1696" y2="1696" x1="400" />
+            <wire x2="656" y1="1696" y2="1696" x1="448" />
+        </branch>
+        <branch name="H3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2144" type="branch" />
+            <wire x2="448" y1="2144" y2="2144" x1="400" />
+            <wire x2="656" y1="2144" y2="2144" x1="448" />
+        </branch>
+        <branch name="H2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2208" type="branch" />
+            <wire x2="448" y1="2208" y2="2208" x1="400" />
+            <wire x2="656" y1="2208" y2="2208" x1="448" />
+        </branch>
+        <branch name="H1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2272" type="branch" />
+            <wire x2="448" y1="2272" y2="2272" x1="400" />
+            <wire x2="656" y1="2272" y2="2272" x1="448" />
+        </branch>
+        <branch name="H0">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2336" type="branch" />
+            <wire x2="448" y1="2336" y2="2336" x1="400" />
+            <wire x2="656" y1="2336" y2="2336" x1="448" />
+        </branch>
+        <iomarker fontsize="28" x="368" y="240" name="V5" orien="R180" />
+        <iomarker fontsize="28" x="368" y="304" name="V4" orien="R180" />
+        <iomarker fontsize="28" x="368" y="368" name="V3" orien="R180" />
+        <iomarker fontsize="28" x="368" y="432" name="V2" orien="R180" />
+        <iomarker fontsize="28" x="400" y="864" name="V1" orien="R180" />
+        <iomarker fontsize="28" x="400" y="928" name="V0" orien="R180" />
+        <iomarker fontsize="28" x="400" y="992" name="VC" orien="R180" />
+        <iomarker fontsize="28" x="400" y="1056" name="VB" orien="R180" />
+        <iomarker fontsize="28" x="400" y="1504" name="VA" orien="R180" />
+        <iomarker fontsize="28" x="400" y="1632" name="H5" orien="R180" />
+        <iomarker fontsize="28" x="400" y="1696" name="H4" orien="R180" />
+        <iomarker fontsize="28" x="400" y="2144" name="H3" orien="R180" />
+        <iomarker fontsize="28" x="400" y="2208" name="H2" orien="R180" />
+        <iomarker fontsize="28" x="400" y="2272" name="H1" orien="R180" />
+        <iomarker fontsize="28" x="400" y="2336" name="H0" orien="R180" />
+        <branch name="SOFT5_A2_11">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2464" type="branch" />
+            <wire x2="448" y1="2464" y2="2464" x1="384" />
+            <wire x2="512" y1="2464" y2="2464" x1="448" />
+            <wire x2="656" y1="2464" y2="2464" x1="512" />
+            <wire x2="512" y1="2464" y2="2592" x1="512" />
+            <wire x2="624" y1="2592" y2="2592" x1="512" />
+            <wire x2="1072" y1="2592" y2="2592" x1="624" />
+            <wire x2="1072" y1="2592" y2="2608" x1="1072" />
+            <wire x2="1312" y1="2608" y2="2608" x1="1072" />
+            <wire x2="656" y1="560" y2="560" x1="512" />
+            <wire x2="512" y1="560" y2="1184" x1="512" />
+            <wire x2="512" y1="1184" y2="1824" x1="512" />
+            <wire x2="512" y1="1824" y2="2464" x1="512" />
+            <wire x2="656" y1="1824" y2="1824" x1="512" />
+            <wire x2="656" y1="1184" y2="1184" x1="512" />
+            <wire x2="656" y1="2528" y2="2528" x1="624" />
+            <wire x2="624" y1="2528" y2="2592" x1="624" />
+            <wire x2="1312" y1="1568" y2="1568" x1="1040" />
+            <wire x2="1312" y1="1568" y2="2608" x1="1312" />
+            <wire x2="1072" y1="2528" y2="2528" x1="1040" />
+            <wire x2="1072" y1="2528" y2="2592" x1="1072" />
+        </branch>
+        <instance x="1248" y="432" name="XLXI_12" orien="R0" />
+        <text style="fontsize:28;fontname:Arial" x="1196" y="396">NTSC=1 PAL=0</text>
+        <branch name="SOFT5_A2_8">
+            <attrtext style="alignment:SOFT-TVCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1376" y="2192" type="branch" />
+            <wire x2="1376" y1="704" y2="1248" x1="1376" />
+            <wire x2="1376" y1="1248" y2="2080" x1="1376" />
+            <wire x2="1376" y1="2080" y2="2192" x1="1376" />
+            <wire x2="1376" y1="2192" y2="2288" x1="1376" />
+            <wire x2="2304" y1="2080" y2="2080" x1="1376" />
+            <wire x2="2736" y1="1248" y2="1248" x1="1376" />
+            <wire x2="2736" y1="960" y2="960" x1="2688" />
+            <wire x2="2736" y1="960" y2="1248" x1="2736" />
+        </branch>
+        <instance x="1856" y="864" name="D2_1of4_74LS20" orien="R0">
+            <attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="16" y="-80" type="instance" />
+        </instance>
+        <branch name="XLXN_35">
+            <wire x2="1856" y1="672" y2="672" x1="1632" />
+        </branch>
+        <instance x="2304" y="1056" name="XLXI_15" orien="R0">
+        </instance>
+        <branch name="XLXN_36">
+            <wire x2="2304" y1="704" y2="704" x1="2112" />
+        </branch>
+        <instance x="1792" y="544" name="B12_2of4_74LS11" orien="R270">
+            <attrtext style="alignment:VRIGHT;fontsize:28;fontname:Arial" attrname="InstName" x="224" y="-368" type="instance" />
+        </instance>
+        <instance x="1904" y="400" name="A2_1of4_74LS08" orien="R270">
+            <attrtext style="alignment:VRIGHT;fontsize:28;fontname:Arial" attrname="InstName" x="144" y="-32" type="instance" />
+        </instance>
+        <branch name="RASn">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3056" y="832" type="branch" />
+            <wire x2="2240" y1="496" y2="576" x1="2240" />
+            <wire x2="2304" y1="576" y2="576" x1="2240" />
+            <wire x2="2736" y1="496" y2="496" x1="2240" />
+            <wire x2="2736" y1="496" y2="832" x1="2736" />
+            <wire x2="3056" y1="832" y2="832" x1="2736" />
+            <wire x2="3120" y1="832" y2="832" x1="3056" />
+            <wire x2="2736" y1="832" y2="832" x1="2688" />
+        </branch>
+        <branch name="CASn">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3056" y="704" type="branch" />
+            <wire x2="2832" y1="704" y2="704" x1="2688" />
+            <wire x2="3056" y1="704" y2="704" x1="2832" />
+            <wire x2="3120" y1="704" y2="704" x1="3056" />
+            <wire x2="2832" y1="448" y2="704" x1="2832" />
+        </branch>
+        <branch name="AX">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3056" y="768" type="branch" />
+            <wire x2="2768" y1="464" y2="464" x1="2192" />
+            <wire x2="2768" y1="464" y2="768" x1="2768" />
+            <wire x2="3056" y1="768" y2="768" x1="2768" />
+            <wire x2="3120" y1="768" y2="768" x1="3056" />
+            <wire x2="2192" y1="464" y2="640" x1="2192" />
+            <wire x2="2304" y1="640" y2="640" x1="2192" />
+            <wire x2="2192" y1="640" y2="768" x1="2192" />
+            <wire x2="2304" y1="768" y2="768" x1="2192" />
+            <wire x2="2192" y1="768" y2="1296" x1="2192" />
+            <wire x2="2304" y1="1296" y2="1296" x1="2192" />
+            <wire x2="2768" y1="768" y2="768" x1="2688" />
+            <wire x2="2768" y1="448" y2="464" x1="2768" />
+        </branch>
+        <instance x="2896" y="448" name="B13_3of4_74LS02" orien="R270">
+            <attrtext style="alignment:VRIGHT;fontsize:28;fontname:Arial" attrname="InstName" x="192" y="-368" type="instance" />
+        </instance>
+        <branch name="XLXN_44">
+            <wire x2="2304" y1="1024" y2="1072" x1="2304" />
+            <wire x2="2688" y1="1072" y2="1072" x1="2304" />
+            <wire x2="2688" y1="1072" y2="1104" x1="2688" />
+            <wire x2="2688" y1="1024" y2="1072" x1="2688" />
+        </branch>
+        <branch name="Q3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3056" y="640" type="branch" />
+            <wire x2="2304" y1="832" y2="832" x1="2256" />
+            <wire x2="2256" y1="832" y2="1104" x1="2256" />
+            <wire x2="2864" y1="1104" y2="1104" x1="2256" />
+            <wire x2="2864" y1="1104" y2="1488" x1="2864" />
+            <wire x2="2864" y1="640" y2="640" x1="2688" />
+            <wire x2="2864" y1="640" y2="1104" x1="2864" />
+            <wire x2="3056" y1="640" y2="640" x1="2864" />
+            <wire x2="3120" y1="640" y2="640" x1="3056" />
+            <wire x2="2864" y1="1488" y2="1488" x1="2688" />
+        </branch>
+        <instance x="2624" y="1232" name="XLXI_19" orien="R0" />
+        <branch name="XLXN_46">
+            <wire x2="1664" y1="544" y2="576" x1="1664" />
+            <wire x2="1840" y1="576" y2="576" x1="1664" />
+            <wire x2="1840" y1="576" y2="608" x1="1840" />
+            <wire x2="1856" y1="608" y2="608" x1="1840" />
+            <wire x2="1840" y1="400" y2="416" x1="1840" />
+            <wire x2="2368" y1="416" y2="416" x1="1840" />
+            <wire x2="1840" y1="416" y2="576" x1="1840" />
+            <wire x2="2368" y1="176" y2="416" x1="2368" />
+            <wire x2="2800" y1="176" y2="176" x1="2368" />
+            <wire x2="2800" y1="176" y2="192" x1="2800" />
+        </branch>
+        <iomarker fontsize="28" x="3120" y="640" name="Q3" orien="R0" />
+        <iomarker fontsize="28" x="3120" y="704" name="CASn" orien="R0" />
+        <iomarker fontsize="28" x="3120" y="768" name="AX" orien="R0" />
+        <iomarker fontsize="28" x="3120" y="832" name="RASn" orien="R0" />
+        <branch name="LDPSn">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="48" type="branch" />
+            <wire x2="448" y1="48" y2="48" x1="368" />
+            <wire x2="1424" y1="48" y2="48" x1="448" />
+            <wire x2="1424" y1="48" y2="480" x1="1424" />
+            <wire x2="1808" y1="48" y2="48" x1="1424" />
+            <wire x2="1808" y1="48" y2="144" x1="1808" />
+            <wire x2="1344" y1="560" y2="560" x1="1040" />
+            <wire x2="1344" y1="560" y2="1184" x1="1344" />
+            <wire x2="1344" y1="1184" y2="1824" x1="1344" />
+            <wire x2="1344" y1="1824" y2="2464" x1="1344" />
+            <wire x2="1344" y1="1184" y2="1184" x1="1040" />
+            <wire x2="1344" y1="1824" y2="1824" x1="1040" />
+            <wire x2="1344" y1="2464" y2="2464" x1="1040" />
+            <wire x2="1344" y1="480" y2="560" x1="1344" />
+            <wire x2="1424" y1="480" y2="480" x1="1344" />
+        </branch>
+        <iomarker fontsize="28" x="368" y="48" name="LDPSn" orien="R180" />
+        <instance x="1376" y="768" name="B2_2of4_74S86" orien="R0">
+            <attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="32" y="0" type="instance" />
+        </instance>
+        <branch name="LD194">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1632" y="128" type="branch" />
+            <wire x2="1632" y1="128" y2="128" x1="1600" />
+            <wire x2="1664" y1="128" y2="128" x1="1632" />
+            <wire x2="1664" y1="128" y2="288" x1="1664" />
+        </branch>
+        <iomarker fontsize="28" x="1600" y="128" name="LD194" orien="R180" />
+        <branch name="XLXN_54">
+            <wire x2="2720" y1="576" y2="576" x1="2688" />
+            <wire x2="2720" y1="576" y2="1360" x1="2720" />
+            <wire x2="2720" y1="1360" y2="1360" x1="2688" />
+        </branch>
+        <branch name="XLXN_52">
+            <wire x2="2304" y1="1488" y2="1488" x1="2272" />
+        </branch>
+        <iomarker fontsize="28" x="3136" y="2080" name="PHI0" orien="R0" />
+        <branch name="COLOR_REF">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3040" y="2272" type="branch" />
+            <wire x2="3040" y1="2272" y2="2272" x1="2688" />
+            <wire x2="3136" y1="2272" y2="2272" x1="3040" />
+        </branch>
+        <iomarker fontsize="28" x="3136" y="2272" name="COLOR_REF" orien="R0" />
+        <instance x="2000" y="2368" name="B2_1of4_74S86" orien="R0">
+            <attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="-112" y="-160" type="instance" />
+        </instance>
+        <branch name="XLXN_64">
+            <wire x2="2304" y1="2272" y2="2272" x1="2256" />
+        </branch>
+        <branch name="c7M">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3072" y="2464" type="branch" />
+            <wire x2="2000" y1="2304" y2="2304" x1="1968" />
+            <wire x2="1968" y1="2304" y2="2560" x1="1968" />
+            <wire x2="2736" y1="2560" y2="2560" x1="1968" />
+            <wire x2="2736" y1="2464" y2="2464" x1="2688" />
+            <wire x2="2736" y1="2464" y2="2560" x1="2736" />
+            <wire x2="3072" y1="2464" y2="2464" x1="2736" />
+            <wire x2="3136" y1="2464" y2="2464" x1="3072" />
+        </branch>
+        <branch name="c7Mn">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3072" y="2400" type="branch" />
+            <wire x2="1728" y1="544" y2="2528" x1="1728" />
+            <wire x2="2288" y1="2528" y2="2528" x1="1728" />
+            <wire x2="2704" y1="2528" y2="2528" x1="2288" />
+            <wire x2="2304" y1="2336" y2="2336" x1="2288" />
+            <wire x2="2288" y1="2336" y2="2528" x1="2288" />
+            <wire x2="2704" y1="2400" y2="2400" x1="2688" />
+            <wire x2="2704" y1="2400" y2="2528" x1="2704" />
+            <wire x2="3072" y1="2400" y2="2400" x1="2704" />
+            <wire x2="3136" y1="2400" y2="2400" x1="3072" />
+        </branch>
+        <instance x="2144" y="1424" name="XLXI_21" orien="R90" />
+        <branch name="XLXN_72">
+            <wire x2="2144" y1="1360" y2="2208" x1="2144" />
+            <wire x2="2304" y1="2208" y2="2208" x1="2144" />
+            <wire x2="2304" y1="1360" y2="1360" x1="2144" />
+        </branch>
+        <iomarker fontsize="28" x="3136" y="2400" name="c7Mn" orien="R0" />
+        <iomarker fontsize="28" x="3136" y="2464" name="c7M" orien="R0" />
+        <iomarker fontsize="28" x="1376" y="2288" name="SOFT5_A2_8" orien="R90" />
+        <instance x="272" y="2736" name="B2_3of4_74S86" orien="R0">
+            <attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="208" y="-64" type="instance" />
+        </instance>
+        <branch name="XLXN_76">
+            <wire x2="1936" y1="2640" y2="2640" x1="528" />
+            <wire x2="2304" y1="960" y2="960" x1="1936" />
+            <wire x2="1936" y1="960" y2="2016" x1="1936" />
+            <wire x2="1936" y1="2016" y2="2640" x1="1936" />
+            <wire x2="2304" y1="2016" y2="2016" x1="1936" />
+        </branch>
+        <branch name="CLK_14o3M">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="256" y="2608" type="branch" />
+            <wire x2="256" y1="2608" y2="2608" x1="192" />
+            <wire x2="272" y1="2608" y2="2608" x1="256" />
+        </branch>
+        <iomarker fontsize="28" x="192" y="2608" name="CLK_14o3M" orien="R180" />
+        <text style="fontsize:48;fontname:Arial" x="20" y="2524">14.31818 Mhz Clock</text>
+        <branch name="XLXN_78">
+            <wire x2="272" y1="2672" y2="2672" x1="240" />
+        </branch>
+        <instance x="112" y="2608" name="XLXI_25" orien="R90" />
+        <instance x="2304" y="1840" name="C1_74LS153" orien="R0">
+            <attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="-112" y="-512" type="instance" />
+        </instance>
+        <branch name="XLXN_79">
+            <wire x2="2304" y1="1552" y2="1552" x1="2272" />
+        </branch>
+        <instance x="2272" y="1616" name="XLXI_26" orien="R270" />
+        <branch name="XLXN_82">
+            <wire x2="2704" y1="1616" y2="1616" x1="2688" />
+            <wire x2="2704" y1="1616" y2="1680" x1="2704" />
+            <wire x2="2704" y1="1680" y2="1744" x1="2704" />
+            <wire x2="2704" y1="1744" y2="1808" x1="2704" />
+            <wire x2="2816" y1="1616" y2="1616" x1="2704" />
+            <wire x2="2704" y1="1680" y2="1680" x1="2688" />
+            <wire x2="2704" y1="1744" y2="1744" x1="2688" />
+            <wire x2="2704" y1="1808" y2="1808" x1="2688" />
+        </branch>
+        <instance x="2816" y="1552" name="XLXI_27" orien="R90" />
+        <text x="2776" y="1584">Temp.. NOT USED HERE. Don't want floating</text>
+        <branch name="PHI1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3024" y="2016" type="branch" />
+            <wire x2="3024" y1="2016" y2="2016" x1="2688" />
+            <wire x2="3136" y1="2016" y2="2016" x1="3024" />
+        </branch>
+        <instance x="2304" y="2496" name="XLXI_22" orien="R0">
+        </instance>
+        <branch name="XLXN_62">
+            <wire x2="2224" y1="1920" y2="2144" x1="2224" />
+            <wire x2="2304" y1="2144" y2="2144" x1="2224" />
+            <wire x2="2784" y1="1920" y2="1920" x1="2224" />
+            <wire x2="2784" y1="1920" y2="2208" x1="2784" />
+            <wire x2="2784" y1="1296" y2="1296" x1="2688" />
+            <wire x2="2784" y1="1296" y2="1424" x1="2784" />
+            <wire x2="2784" y1="1424" y2="1920" x1="2784" />
+            <wire x2="2784" y1="1424" y2="1424" x1="2688" />
+            <wire x2="2784" y1="2208" y2="2208" x1="2688" />
+        </branch>
+        <iomarker fontsize="28" x="3136" y="2016" name="PHI1" orien="R0" />
+        <branch name="PHI0">
+            <attrtext style="alignment:SOFT-TVCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1600" y="576" type="branch" />
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3056" y="2080" type="branch" />
+            <wire x2="1600" y1="544" y2="576" x1="1600" />
+            <wire x2="1600" y1="576" y2="608" x1="1600" />
+            <wire x2="1776" y1="608" y2="608" x1="1600" />
+            <wire x2="1776" y1="608" y2="736" x1="1776" />
+            <wire x2="1856" y1="736" y2="736" x1="1776" />
+            <wire x2="1776" y1="736" y2="1808" x1="1776" />
+            <wire x2="2288" y1="1808" y2="1808" x1="1776" />
+            <wire x2="2304" y1="1808" y2="1808" x1="2288" />
+            <wire x2="2288" y1="1808" y2="1872" x1="2288" />
+            <wire x2="2752" y1="1872" y2="1872" x1="2288" />
+            <wire x2="2752" y1="1872" y2="2080" x1="2752" />
+            <wire x2="3056" y1="2080" y2="2080" x1="2752" />
+            <wire x2="3136" y1="2080" y2="2080" x1="3056" />
+            <wire x2="1776" y1="400" y2="608" x1="1776" />
+            <wire x2="2752" y1="2080" y2="2080" x1="2688" />
+        </branch>
+        <branch name="XLXN_87">
+            <wire x2="1856" y1="800" y2="800" x1="1824" />
+            <wire x2="1824" y1="800" y2="2240" x1="1824" />
+            <wire x2="1824" y1="2240" y2="2544" x1="1824" />
+            <wire x2="2768" y1="2544" y2="2544" x1="1824" />
+            <wire x2="2000" y1="2240" y2="2240" x1="1824" />
+            <wire x2="2768" y1="2336" y2="2336" x1="2688" />
+            <wire x2="2768" y1="2336" y2="2544" x1="2768" />
+        </branch>
+    </sheet>
+</drawing>
\ No newline at end of file
diff --git a/AppleIIGateSch/ClockVideoGenerator.sym b/AppleIIGateSch/ClockVideoGenerator.sym
new file mode 100644
index 0000000..924124f
--- /dev/null
+++ b/AppleIIGateSch/ClockVideoGenerator.sym
@@ -0,0 +1,107 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="ClockVideoGenerator">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2018-6-5T4:4:38</timestamp>
+    <pin polarity="Output" x="1120" y="-1472" name="AX" />
+    <pin polarity="Output" x="1184" y="-1472" name="CASn" />
+    <pin polarity="Output" x="1312" y="-1472" name="COLOR_REF" />
+    <pin polarity="Output" x="992" y="-1472" name="H0" />
+    <pin polarity="Output" x="928" y="-1472" name="H1" />
+    <pin polarity="Output" x="864" y="-1472" name="H2" />
+    <pin polarity="Output" x="800" y="-1472" name="H3" />
+    <pin polarity="Output" x="736" y="-1472" name="H4" />
+    <pin polarity="Output" x="672" y="-1472" name="H5" />
+    <pin polarity="Output" x="1376" y="-1472" name="LD194" />
+    <pin polarity="Output" x="1056" y="-1472" name="LDPSn" />
+    <pin polarity="Output" x="1248" y="-1472" name="RASn" />
+    <pin polarity="Input" x="96" y="0" name="SOFT5_A2_11" />
+    <pin polarity="Input" x="160" y="0" name="SOFT5_A2_8" />
+    <pin polarity="Output" x="416" y="-1472" name="V0" />
+    <pin polarity="Output" x="352" y="-1472" name="V1" />
+    <pin polarity="Output" x="288" y="-1472" name="V2" />
+    <pin polarity="Output" x="224" y="-1472" name="V3" />
+    <pin polarity="Output" x="160" y="-1472" name="V4" />
+    <pin polarity="Output" x="96" y="-1472" name="V5" />
+    <pin polarity="Output" x="608" y="-1472" name="VA" />
+    <pin polarity="Output" x="544" y="-1472" name="VB" />
+    <pin polarity="Output" x="480" y="-1472" name="VC" />
+    <pin polarity="Input" x="0" y="-592" name="CLK_14o3M" />
+    <pin polarity="Output" x="1472" y="-912" name="c7M" />
+    <pin polarity="Output" x="1472" y="-848" name="c7Mn" />
+    <pin polarity="Output" x="1472" y="-784" name="PHI0" />
+    <pin polarity="Output" x="1472" y="-720" name="PHI1" />
+    <pin polarity="Output" x="1472" y="-656" name="Q3" />
+    <graph>
+        <rect width="1344" x="64" y="-1408" height="1344" />
+        <attrtext style="alignment:CENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="736" y="-736" type="symbol" />
+        <line x2="1120" y1="-1408" y2="-1472" x1="1120" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1120" y="-1400" type="pin AX" />
+        <line x2="1184" y1="-1408" y2="-1472" x1="1184" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1184" y="-1400" type="pin CASn" />
+        <line x2="1312" y1="-1408" y2="-1472" x1="1312" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1312" y="-1400" type="pin COLOR_REF" />
+        <line x2="992" y1="-1408" y2="-1472" x1="992" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="992" y="-1400" type="pin H0" />
+        <line x2="928" y1="-1408" y2="-1472" x1="928" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="928" y="-1400" type="pin H1" />
+        <line x2="864" y1="-1408" y2="-1472" x1="864" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="864" y="-1400" type="pin H2" />
+        <line x2="800" y1="-1408" y2="-1472" x1="800" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="800" y="-1400" type="pin H3" />
+        <line x2="736" y1="-1408" y2="-1472" x1="736" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="736" y="-1400" type="pin H4" />
+        <line x2="672" y1="-1408" y2="-1472" x1="672" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="672" y="-1400" type="pin H5" />
+        <line x2="1376" y1="-1408" y2="-1472" x1="1376" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1376" y="-1400" type="pin LD194" />
+        <line x2="1056" y1="-1408" y2="-1472" x1="1056" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1056" y="-1400" type="pin LDPSn" />
+        <line x2="1248" y1="-1408" y2="-1472" x1="1248" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1248" y="-1400" type="pin RASn" />
+        <line x2="96" y1="-64" y2="0" x1="96" />
+        <attrtext style="alignment:VLEFT;fontsize:24;fontname:Arial" attrname="PinName" x="96" y="-72" type="pin SOFT5_A2_11" />
+        <line x2="160" y1="-64" y2="0" x1="160" />
+        <attrtext style="alignment:VLEFT;fontsize:24;fontname:Arial" attrname="PinName" x="160" y="-72" type="pin SOFT5_A2_8" />
+        <line x2="416" y1="-1408" y2="-1472" x1="416" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="416" y="-1400" type="pin V0" />
+        <line x2="352" y1="-1408" y2="-1472" x1="352" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="352" y="-1400" type="pin V1" />
+        <line x2="288" y1="-1408" y2="-1472" x1="288" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="288" y="-1400" type="pin V2" />
+        <line x2="224" y1="-1408" y2="-1472" x1="224" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="224" y="-1400" type="pin V3" />
+        <line x2="160" y1="-1408" y2="-1472" x1="160" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="160" y="-1400" type="pin V4" />
+        <line x2="96" y1="-1408" y2="-1472" x1="96" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="96" y="-1400" type="pin V5" />
+        <line x2="608" y1="-1408" y2="-1472" x1="608" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="608" y="-1400" type="pin VA" />
+        <line x2="544" y1="-1408" y2="-1472" x1="544" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="544" y="-1400" type="pin VB" />
+        <line x2="480" y1="-1408" y2="-1472" x1="480" />
+        <attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="480" y="-1400" type="pin VC" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="84" y="-592" type="pin CLK_14o3M" />
+        <line x2="0" y1="-592" y2="-592" x1="60" />
+        <line x2="1472" y1="-912" y2="-912" x1="1408" />
+        <line x2="1472" y1="-848" y2="-848" x1="1408" />
+        <line x2="1472" y1="-784" y2="-784" x1="1408" />
+        <line x2="1472" y1="-720" y2="-720" x1="1408" />
+        <line x2="1472" y1="-656" y2="-656" x1="1408" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1400" y="-656" type="pin Q3" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1400" y="-720" type="pin PHI1" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1400" y="-784" type="pin PHI0" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1400" y="-848" type="pin c7Mn" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1400" y="-912" type="pin c7M" />
+        <text style="fontsize:56;fontname:Arial" x="284" y="-1100">APPLE II Clock and Video Generator</text>
+        <text style="fontsize:44;fontname:Arial" x="492" y="-1028">Entered into Xilinx ISE 14.7</text>
+        <text style="fontsize:44;fontname:Arial" x="740" y="-976">by</text>
+        <text style="fontsize:40;fontname:Arial" x="636" y="-924">Frederick Kilner </text>
+        <text style="fontsize:32;fontname:Arial" x="504" y="-876">June 4th Year or our Lord  2018 A.D.</text>
+        <text style="fontsize:32;fontname:Arial" x="548" y="-112">Apple ][ Will Live Forever</text>
+        <circle r="12" cx="1056" cy="-1416" />
+        <circle r="12" cx="1186" cy="-1416" />
+        <circle r="12" cx="1246" cy="-1416" />
+        <circle r="10" cx="94" cy="-54" />
+        <circle r="11" cx="160" cy="-54" />
+    </graph>
+</symbol>
diff --git a/AppleIIGateSch/ClockVideoGenerator_guide.ncd b/AppleIIGateSch/ClockVideoGenerator_guide.ncd
new file mode 100644
index 0000000..9da11a5
--- /dev/null
+++ b/AppleIIGateSch/ClockVideoGenerator_guide.ncd
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
+###5820:XlxV32DM    3fff    16a4eNqtWmlz2zjS/iuqKX9IxmWbOHiiUhVdllnRFUlW7P0wLFIkM9pNbL923j3Kcn77NkCABCmQdnZ3pkQCT6Mb3cDTOBifYCt/RhY7WWV/3z/t7++CHjqnvRPMzij8dgR+3312tr/78fTjX98yH1Xl3v4p65099P65I0+2ZWVn+VeCrTPaA5Ve/JjFvbP9Y+8+z6GRfO96yLJ6Z/e94bf73d+2+zS7n2R32WP84/4x+h4/nN/tUpPs/O6rGX/Y5T3wcf8Ij/tv8Hh4BLd/OAk7+0ev4en9t96f+69/9s5+9NCvO7Brd8BjF+GyP0IWKUueKiHssgsBWaqAVKEUUVWwVcFRBVcVfFlAyg5SdhBRBWUHKTvIcUTBs+Vb1V359ou3b8k3km8s31S+pb4v9X2p7/spu1hPw+E4unHoLab1ql2vOlrVrjd2blGjaterTr3q1qrYqldxvUrq1XpHuN4RrneEGx159aoevnuLSL1K61W7XnXqVbdWrYXg1kNw6yG49RDceghuPQS3HgJUfcLQuQUPCx7kHPEHxqyP4Icz+EXoPqeRS6drywOMwA+Whv6NC79oMbi+zFQheoh3f4tQzgYIR1hpIQGQiJRmILZBaXbtOaKKy6rNBtPF8JNbvG5uYXkazCarqL/ZrMLB9Wa8Ztg/glZXi2iz6s/X4Xi+ia7C8aq/Gl7dfmBc/TqcjqJNfzUZbziK2eAGfrc7Nsi+PfWscwIrwiIXtSDkkYRzeKYaAGRX8sUgWlxvANxVAIhlazG00+gSoXrdnl3f5HXo8gi4rRuZgJEhKkbRJhc305swwhDPsD+KtuH4S7Qdr9bhYk4BWd/54ilmQrSRZTkrmA0/ETacfvL5I0L0nsyyqhjxKEG0mC5W0WoMk1oWhRUums3CzWY8ctlwNe5DAbhiWBJRwloX16/fUza8//5QjnlcVAPZe1FeDHayWIwDYrwrWM2KkXCQHAnfhBLLiBIjSo2obUQdWBuPUf8CltnEKOA6EcFdUopMRqnVYhQEHUaVtMUoajOKOo2iTqO4zSjuNIpLo0cjPY+wY0Q9EwqzEptQSfouITbZo7ZJhdpdKp5RxetQsS2Tim0pFVsXRpIxMFoGnFqRbcRR5BhxHLnCJWxMG2xMG2xMEGxMENyWILgzQXBnguC2BMGdCYI7EwS3JQjuTBDcmSC4LUFwZ4LgzgTBxlTAxlTAZrYTk4qkLu6iLjZSF5upSwTlcAt1cQt1cQt1cQt1iZGkxEhSYiQpaSMp6SQp6SQpaSMp6SQp6SQpaSMp6SQp6SQpaSMp6SQp6SQpMdKRdNGRGOlIzHQ0qkg6EjMdC9qRFjqSFjqSFjqSFjpSI/GokXi0jXi0k3i0k3i0jXi0k3i0k3i0jXi0k3i0k3i0jXi0k3i0k3jUyCJqZhE1qUgW0S4W0RYW0RYW0RYW0WMWZWyk3bKwRSHmYL06wH0ALiLhRlxzAl6yAo6ti4sPNJkuvgTT/mZ4FcFR/fISpMH6dj4sxH1ePBwQu8TsEs7/l3Ctu4Tr2yVFPhP3kej4YOpqMtwhIx0yeiRjE8wm4MIEXJiACxO4QV5ZLvzkDVIW5MYDQgRCpIRIE4L2FQYhVkLcEBIQEiUkDSEFIVVC2ujTBqGthLYuRCyMGb+jXIiLoVeU4dKHWTi34Xc4HKDBYnBR3AxdUQY5XNTD9XgTzcazwXgViRttNAjno3A+uTBcky7CtXZ5jdZX/eVYq1uYMt6ivPdGS34DXG/4nXe5WiyjNQjmE7j/8Wayo2hzuxzDLfwV2zA/9RZcLRXYfDEaF1aKNnArHK/G8+FYXENtNh0hn8bFS4wbh5bru7h4Cchh00V/NB5hkF1vLBP3+L36XN19q3b4je3IG9vRznbI4+2QMTd2rSJuotLE7Zq4W5O0a5JuTdquaQwYFsJZfxkNZ6NpOB9Hi+UmXMzXsQBni9H1FOaelzfhbLze9GfLRFTlJwdQjh9cNh9vvixWnzBbgDkwGrPlOYarBIKfw5b94afxiDD+KZI/V83eYEVcjtYyLSbzkWIsLCZGnBOPWyply2l/OJ4B+3MNvF73J+Oa6e1waDSt4cJ0U4d3PZusYBPi+GgBWVZ8+4iu59fr8ShahvN10TWMRLSCEQBTuxLgKRMXtckoCkdF0+VopoYR8kkg4Tzqr9fhZB7BGEs3ODi+gdSGpCmSrzAsvvzog7IdD4X3qBLz7vjyr6vowSoVWxMXHkU89+UY1/DVJWXLq9DyxVOktACQAIolGgHyKRqNRSTzySxaL65Xw3HOUaiWVMrY8vH+xz3/yOOfT85HiH3G7DOs3J/Vyv1ZX7lh1VuJD1wr9VELimoJImy1nGG2tjxWpPAFSFUJVUVcFUlVpLuyyHevuKxd6uXb0vakVJ1UtieV7UllewL7uPqyd9FHegXrFaJXKp2JrjPRdSa6zqTQWVxu7Ih/rEWw9ms18V0PNtMmpD6QtElwq4S0SmAHKAVerpVFG5iiFYXB4eeaG8O55uYXzzXK1v/ijJSxTZn3PNNyUZc8FqlHmwisMuMVpG8Bb/n3dL7cwcqT17HVJq0BM5ggrb5ejscjCfGMD2dLmNhwU1jZ1JaKjcpJ4cA0HKxhV9/8mfUgA3q/Gb8Z/dbZgp9WX2kB59ZXWsCO1miBX/UDv+oHftUP/Kof5FU/yKt+kFf9IK/6QV/1g77qB33VD2ryI6laCBTZhRS5EeqQehHukPoR+Q1uTGapE1m/YbaF0/1Wne63Vv1fIrawhGzV6X6L6sfwLZzut+p0v9VP9zYIYY/Yqj1iSxpm4XS/Vaf7LW0I4XS/Vaf7rd0Q9kHYV8J+/dKwHYBwoISDhkNDEA6VcFi/NMAWcjO6KtaVtSfKsIIMC1ScvyXK8zkRJZXsKbsJ4aR0c3YzGvSsc9Rbb66LQn89DEMYQDnoF3I6ywtzU+KVEtyQ+LCpHDUvPzzkdQF2moDbAI5UiA9Hkhri8B6dJmbqcB7xfzesA25lriLxEQbUPcKAsLDENmmaFQjGMvRGHTfqpFGnIhDul3wXBnlBEqtRx1KBSAViq4KTsfo/XKSyLqtSkcr21JFyWjdsS1j+c4Xqx8GZKkh7SqAMulgWPDdThTIhbz6D+TSJwhQomn6PBvu7dH/3lQ8o1GbxX+8ft9kj/+MRBe3vKojdYnb7mTL+ByGE7dyZxx8iT/KyJN2iHIBjHn8K3GW77+m3/V1mM/HHJZTxv+AgbP+UEXaf54Q9xI8+e4Lnj/iOZB5Tf4wCbDqMVuF2zLf5weImQDgIF6oy3Q5nizW2g/V0/AUeiy+HA5yFD8ctDgdYAQ6H0Yd379797KPf+RP/3qfvT/v4/fvTdxwCBAoChf9+75P3B5ixQqmPPkLD39/1iRDXBYQLsBTgugCMvj+QXIJV12DplCuIHgEhslvNFQ7+LNAD8Y4sgPXK3UJN4D9rgvdV4EK16LqpJNqLvrhZUMI1j38ea/2Ubp8qD4GMlQYELZpxYwfIAk1CpIE+/lioHpAWm5DxMauPf9PzAywNukD0syshPuZljU/cAQ75olqOQTW45ZT91I2lFcb1s6oqZlTT4WN3WgQaa6CawlPVC20Ifzb6Oa33cyr6KeK3DgTeh5ePHx8cnLKPH//p0uAycAP0vHYJ5EQCvzxAhGSZmwdenGbPdyhDAWLwwoHDTlAK8sRmL2sXmxTgnI9QHKDcCiwNz+C4zxWasGOCE4R/CSYshTgACnBrHOC5C3G6HjuxuXs8IuwHdoK8eLezQYw9AUMh5tpQoHHg2uzvG0S4bf6/k3V2kAXUY58RhRbPL/BG/H2CCOA+O3E8LoZmiezI5Y5gXvADlO14YSeGmibKMYf9C1E74EsZFKgoTBF2A+f5BGXQjJ3gAJbtE+gSVsUTCi9wxYEXROCJ18sVopj9BYGj+Nl1AjsNACIxGCI4IIWhmJ3A8GQpuwNf2EsCAwrepwGBPtDz/yFYOOBBGSj67N7lM3DF/0jp/xG1Amwxdo+QZwBtdAzmjgHzDdjOgOWGTix8DFJjQ/sI3CMnMYDusd97JzNFbQgGUSNoGh9qsOkYxgL51AS6JjA2gakBjE3TGBMDmJkCio2gyfl4Z7J53DJBNg5w4AUk8IGXQFYXEgcRO4Azy97hMbC90AMQ8s+OYVqyWMA5Ll5EvJAr3tB1XrwzPn4ssTnMf9azsItsBxKOpAHl/TjghctExw5mexqXPTkO9EQTYcsVHb4kKOHDT3VjqTRmFdaQa0trNri/E54V2jDzqe4otxY3XcukNUf55khrjvSt6dKTw9/4+QOESWP2R+YDhlJagi6AMCQc3aEC5VE4O/YHHCJf4KxU6SegH/OWLq5agrtgAR7QtjQQi8Y5B/kEVo1pCo0zynGRj6o1eAELH3fCqlqDb0IK75eXJI+BCDGMR1InAhxDTETwFBFk3WeSEXL6eP4Kasg65nVaMMau1HLWQR27hTpYTQ8xU4cq6si6zSoOpU4LhfJfZ1DK6WgbCIRsaSx3GwSSHnkND3laSetigZKwWzn+hMRqCFOXOjop0G4nYTegGUwzHBWecrfCgBG5IISjNSzZs0sk/2wD/zhYkhr5Zfcle9EuL1tWTM+TytGKkHlcda/omNplS07G1JVc5OQ1khGOCSYy+g0yilUqqZNVX67k8CLFSY2zbWSkuyZvJBltRUbPTEa7MdWOmuqKrNoCl7ctcPg/WeDSpjW1wBHFz9S8wEnf/Iavns7HapXKdUI6iYJTjXzVKpVq7KvWqLQihVoSYcS5fpZoyyzHSpoqRgJoXGZzjajUrQyUlE6yqmmxGKaCgOCupcVWcvglcfgiyU9qtLFI7tjeLmbDSev7oeQPStoWHop+eWr1wa+tBmqcBKxtBtWgOMd7Dwf5ANo7kXt+AjEmkHu7eoywx3bmXj3l3MZ+gFln7omNQNsYOnPRTVpykWQqGeNXkrHOa6LloIdb5om4v56CHmnZIYinMjA27xAx605FPr76VlFPTTmzEIu+VTgy3cCrcqtAag3moEpX36qwMlnV/gGjX+Wgn1QtVQJ7qOydZ5VHZFKpfAW8Skx/V7laEdZLy7601E5J5YFaGby8wmRiA4fj2MxhmMP/gsNWN4cLjr/xcOO37Sf4f8DhGLVwGPu/zuEYt3FYHbpz+22nnCaHY9Zx3EnlCgfdaxzMKrDcW1K3AktaqxSAodBTQBz/APa1zQXFSdVWWzQV4X1tz4grTCNmHFcelEdtRXewqh2YssqmSqK4cpXnS4zVKUhcdfn9DEsWewWLEYHpwWKaThFBxf6CxCho02TJObfLm1YmpwkWcmQV9xiEM3lYEJ0hXV9Os5OpaVbHbVR2y8OUo88LYBXGBItIhT0icSD1B46AGjSABw+vOClo4blFeAn/cODVoyvmQvfOl7un24gO2GmITvRViy4u9F2qoqNSP9ejUxzgBR7FH+CZwBMZHcch6g8cqUUniG2aPMcwecVByDR57psmT3RmmjwXd05eeQCDgj55wh6RuJg8QOrhtXHTM4XXyk37beG1cdO1usNT3KR1blLFTaq4SRvcFN+OTOG5pvD8tvDkhwRk7TrD89rCQ28Mz6+H56nwfBWeVwtP0u04Ov84uuKUaAoOv2XuRFfGZYV2xVZ+F7H0yIQxUqA8Ls5OfdbENztDXBgZZs232wLz30RKn7bNmtM5a748cPGCPmvCHpG4mDVA6uG5LeFhU3heW3jx28Jz28Jzu8PzVHhePTxXheep8NxGeHFLeKYVszh4msJL3hZe3Bae1x2eut5CoRZerMJLVHhxI7z0KLx/Ay9iI6w=###4092:XlxV32DM    3fff     fe4eNq9m8uO5KgShl9mdrMxxtwqNa/SEuYi9eb04ixH9e4HMAGBk3A6s1tHo5kqR9ngP/n4I4CcvxgXXyw+frLVfy1fj78ZZ/nnzkxIP9f07/LvX+WmxT/+w7j/Eu6RAvJrXUL6RckvuaTHlz0/9out+bHHd3o+t8fw8+F4XpnjeRZ5fZ61br//W/v995/8S2r18SO9WYnn9niNr+HxT46kx9IN6T/fqUe7lDdO//xb2lX6UXoOE3WWUer8LXWlr6k6e6nu6DepSL9gdaU9XuNFXYqM6vhcHXMzeRslL9yTxyl5+7W8DeRtozwO8jaQx0d5TBPy7EQeM4S8bb8lr3Q2kyfjpbyj3yQj/YLllfZ4jRd5KTLIU+wkTx3yfHqtRY/q1HpWZ6o6fVInwkxd6WtQZ+vgCVC31ecjVnf0m1SkX7KKH+nNSpxVdTmeVP+TIyObcj54q5ixqYjBS2N1i01Jsemu2VTAphrZlMCmAjblSZ4h5PGZPEvJY/fkGUqev5ZnQZ4d5RmQZ0GeOclzhLxlJs9T8tZ78hwlL1zL8yDPj/IcyPMgzw3yJDF4bMKmpMZO6DviJDV0Ulxpk3Xk5DBwso6brMMmT6MWKF1+MmqBhJLXN1vc1agFSpleLkctwJwLI5QBoAwAZTjLIyyFzbJ5oCxFxFtQBtJS4k15o6UEsJQAlhJOliIYIW+byBMrle7ulWKCUfL4pTwBCUGsgzwBCUGsVZ4YE4IM82znnrOdjFSyM3eSXelpluukvMp1R69pckWc6Upj/IjmPJeusapIIcmexyxSRG636stIASn11YjFymMccIyVxlhhjCOLkTKSfSKL8pHtVl0ZSYO8XBPEapBxMJFYPSRWC4mjg0Qiq7FJVotUUttu+Uekcpq8XAzEmtLikNFiTWix5rM4prMY57JmS7hloWzxVqVVuprKul4EHN0me0i/YGGxukYOF2Vx9MRlJeoQNdPGKW33yqzS2VTcdRV59JtV8METS3u8xosnpsgoTxDyZpa/SEoevydPUPKuq8ij3yxDjvIEyJMgTwzyFLH4ZuuzOkUtvjd7pxpR1Npbqktt3h3a1LD0VnXlrerCW53W3S73Kr/4l67CzCGMp2ET5c1+lmomBRPPwjzSte3XNl/v/Vrna9ev1SMps/EY9TXDJZAyIWuZ1erPpSpLH+vWu0kFZrru3aTsl659v97ydejXPHWr7PF5htz7hnvda6/nFJwe+xlK/v4ZGR6Un0wIWFuf9336loOvrcjWNwIuaU+r9x/B5qjbUdSn6D6s4HI0Ze3gcnSrw5pkRJaX3mUTJv1h3frtKZJvCHqYw7kdm9oxpU/b2klqHj9E6dOFHi2Vgo0FC8/nWGx8ioU9YWFOWKgTFnrAglFYiBdYyBMW4oQFP2GxYSwChYX8BAv3FhZtuZe0dyyMQNGGhdEo+oxFqFg4wGLttxcsQsWiraBzOx2L0NpBWHjeowMWknALee0WIw32yiRYpGhY75rECIG88gZPQcA/gWB/C4K2FZwkdwjaFmqOdm/YUPQZAl8h2AGCpd9eIPAVArOjdhoEbbj9AIHsUQxBcZIZBHEKgT55g3pc02AGbxAUDfsLGraTN/DHNRYCYREXCgv3CRbhHSxim6aiUxE9CjYoWiWao09QJBEHFAGgkP32DEW6oUARFWqmMSF7Mzhf2B4djCHfbRMT+8jE6h4/pX9ZRiiqjEgf63r84H2o1vRXpvjxcR+k/GJhK8SURf0MmObq270Sg1MlRseEOXXmpFZ6sIIoW9K5M5E+hkPP8fAvth2fStXxvYvcDh8pKW21gp83WI4XH9/XPpC1wM5N+jTQLK8jmnrKYKUqEu+KJy3pXdKIqhL3tsczLOmhg6Kgeyup6biWE4LeX7rroKLtQuQm0rLjh8z1qFj6mzVkvUcvkflOo1lQRjJgKsB2Yo7VmZD5y2+lUtV98qRUAwN/BSREECJKxHy9HbeJftuCQauAMaeJQbfvD7pUZ1ph4xFK/XAa9D7aw+groHU0NY2h2GBXSJWPPophjHQfI+ZNj+Lx8HuPZyikOqCAQc0tNyZg8HKw4eZ1D6Z24zYyqBGD33nfYv3a06Rwp0Sz3DKVG2uTwV0qAjOT8aEyUK73MjlmJsM2GDf55xcyZVQG8NzRKxwtKLC27SV4/inDgdsosBs2t5vxfQfXgfPD9KKNJRjw9JFlYtKfCjE+tHAvfSDl5CAkOch8OdaL1r0HwUR8JTkpKxYUCm/St2gnU4b2nsjyIA3mW4FXSMY5BrhG9HSZGz5kWMVCwOqnsGoK1tGo2GMG5+FXAg/pE6Nsd+chrpBuDVJ/r3RqkKLUt1Mw8vg+jeVAYWaDDUYzt0EzL/nVU65OzgPFUvpcOnLtDCBHgTnRbsVDnJqopXl6XYQYpNUUfTa/HGzmBwZcOmsw77pH8xTJvR6p1rH+Ht2cXexNNwv1Ww+Ct3df3c3gq7lwXL9cYtWfWGUjq+/5qXlcJtmD5W3MrijbFqhJx/WU43LKcd8zWlz+e0ew7T8wWkagzeR5AfMixZuTAn1SoKZW7JAVg2v6w4phxwCWEd53KgOKPfuzR4sQ11vtBd3CWvdoAgWIMjR/msUyZLG+xxrNzbXdUKhKdC9Mv2blrM2+77LpvE7XKPrPlhMXNSaF905terB2FuH+fEGxB4JzZt8HfVfE+mVtpzHudi37DHJ6126BAOKO600Accf1JtCRHsfQwBbpjndTFtXv7dA61ZpFpg/7ujvaRnEo1rd6bQ/CnNl9i+WJuB8L9Lye3AlCzZUvm8mGys3FDsWjW4naYV2Bx3hpt+J5t6VhV9LaFDvzAXaaKmQDVci+XEJ1+gA0t2LHq8OXdGBOAFQ9cMJbtEPZ4NEog0vUKiIV+E/hxr9b2ltlfhyDemHvb9ug1D32DKVu8+e7fHNtXhXwW1XB0w7/bOvmXAOsj4sV9xlKai9wZQDlfq8GoE8F3EaxqT9g01C531O5/zrl2we9vHeVNHds7jnYr2kAbchA4ajJoR0/gMKJScp3YpLyHd52tLr1g2vmhprpVt2c2kyniplNFYOminM9+FQe5P5xrWv93FP5POt/cJI1X7DdyPqWBFq/yPq/c/BlKcRX9T7ix9fWZ1m/Ib6/WLpNsr6tY2k8BgSOqixmEWzTbmNV6FoLvUKAAw3jEWHQlx24hQM6iyaD5S2WZ5iFGYbvbas6mHZ2mHa231knTv5fCcR852Db/t+rMRJUTYHavoZm/tjqyyqKT/EBn4EoD9b9zfJgsvxqvO41IZuAeG1YaHyO59ud3c9M5dKq0TpDv7fvtJt27zNX+c5e+rreKpoZcMhsdafVuh5rtMceA5O3ssXKDFBQuBo9Lx028Tulwz1y+2bYHZJ3iuT2VVjxuzVEGY0pwNsHAEeihljtb+4fqItiotuqncJjIsq8jenYmd7rUj993s/FRA72GWH7043dhn5E6BvT3wnvysneKoC6r+15lEBYb6DNHWva0wVpW00dvnWRW63T5HvXoZ4yqVMtId4vIua7vOg88wBWUbu4vCVY+3GN0JBVVBrn7m4a7/DoOnjKocNAHVvw+YxZ4S1Z+DKCQjuypuKk/GxzX82SvPJ47yc547QK3OY7nqMvvT6EPrmMloTL8Ff5cjSXPkBaUNvtHyRFFajRbklxvX/WDLMqvWKbVbpuR+uyU57/VGdVaPFGgfY9BhAALVoiBtYea6sOE1vnyBMMIBSGjfoeRaay9+BT6sytDmsJRlRq63tnPMRawswPJC84MxRnG8XZqyMeYgGBCzStKRb5ByxGokDj9t5BZCcRkpPCpt9IMvgrdaHd2aswC3zpMb3wfu9TFabxqXlDKc5Q0kMihW95aYMmQugxmAhm6zGAXqsWK5NLQxWW1hpTPFOpcAfPV/uIp6XtUZd9WIdpMq21DUZ9j9yrnUa9U6Sy90nVC1GJcfOiEjsvde07lVhDbUf2WmsmfZwYavjaH3xLUKMk2yYAyrGw4NAOF2KidYStFGBbZlaql4mVanSA3h1/wVON9WDfwHG9f2y6ZbuYf7Evfiq67Mkt0dH3fiS4/wFYx43y###5312:XlxV32DM    3fff    14a8eNqVOluu7Siuk7kDgPDeW2cY97ckAkTqn+6PUn8d1dwbYzuAd7Kqe+scJbbB+IVtyPpSv/9PG/elXfv+pzb1y7rvjvBfhzr6S/Bf3n//w+Yv9dUfJzz+FQb015+66P5y/P6lz/Mr5O8/dDMd7a+JtR17HTA2HAv27Ng+9K9Tt9DR9kt/2d9jtZC+hzzm/P6HK2NVX8dDBzNW183C89TFj6nq61ahogoFNWiBFHCdB7JCyf+l7caySzfEAOk6U9DElVWRjvTl+w9fx9A4sZ0RaG03BQEfTMcHVNG+qZj+XsX0omJCFXVw/72OU8C0CPgnysf4qdDUPi3a1zixbKiuozJfx1fo/+Ou43Heyl2wfEdeX9of3x02N+wugC0Oc3OY+v5pk/N8MYku/7NNzhPIbmVGu+AwxOzyYheQaPmbtgPBAWDkbttEx+9lu+iEtusqTIMqeyMX45/5xnYr/+py9geMNoQvy9YqeSJpZ/2ph+aE7GyvEaPlnMjWkW6MrFOCJW4vcKcHt4qwbY8uVW8uXVwufVnNmy/V/+7LaiUz8qU+OKO5Z1/GN19OX/90Ypf9duIVb9ziw3rcWPBhl2/48KLt1uHpQvYWIG8XsrcAebuQvQVrTW/9GdRA/xHU96/+ro0ewqJgf/SX718AEd5pwjvd8R1C/OUR3YP+V38nZCJk6sjEyELI0pGFkRchr468eC110Fq9oPwCCPGWBts+2M7Bjgc7GOwY70/C+7PjO0T4wIoEUCSwIr4h2rfvX/2dreHZGh6swQpqy3gLeDvxbD0L1rO39WxjfAM88/dkKN8N5dlQOlkanGwf3CHGB8YHwIcbnxmfAZ9vfGV8BXxlfCbH95eOz7frs2G8AbxhfGNlGyjbbmUz4zPg88QnxifA33rlwvgC+HLz5/ENxrd7/OgVXC8crmcVUKE7HZ4+j4dTiO3DsIvAcnXiBAjyX1f+GjwhWgDuM8dzuF2Bi2ohTK9S46VzRURne8Gz13lEWHzpXgN7e1yG2beMz77jxirNokePiou0s090YPhIE2FCf441gME5JvbiOGL7nldQtr7nh2i1jXC6pgRAGSvTcyw9Qgx59LluzO2iQjWm4jFslK9BwaTuwHqWKMjkQvFgtx9o8aEHZjTduVz59sxgptOJiEwESCAw9aoIK3Ka8uQ8Hh/oSeOSo2ekZyO6pqclPmY8rzH9zop2SMYhMHRIJ7mxvwzb9ycYBiRFQqZg6U/w4kgZI0Z6sXTnUAE51uGs/hgmVxwwalhnPJHgmeARUViE/jJGZg6t/oKIyghi3s1AUsf5AkNjG1r0B45rPFHzi+XVzXwBvS5atD+XmlGGxYAlGAzsUhqrOWIQtCukDOuQSKnaSIeCzzEflnO4DFShizYNsD/GKiPGLt4jhVavaHwwouXSF3CaxRJzD084nGx/kU4HqogddqGOFJbjYLd3B9v5jq2XKIcPzjYuuy/TDsLEcHEaGMzjRSwSmQIiyqBr0nhAWhq+QedqelrgC1vRUDpIFA/AAJSHQj12U/Uj8iJxSOTtzgmf9gt7gXROUTAeTtrCUA1QG09CNlQjU3oDHhAGkZqEMRW3ciM5SyPuGX00dojBECE5zZATwhYFdSRGJAGrp4QFLE5i4VAsZJHJkxDfBQN7RGfOc3FUmiJnFBZUzdDGpVCF1YnV4EF1B6eiao5U03yQ0X56HcaAUR2VH6jA90KkHtrSUeynSDk0RcqhUJ3vOYX0SrSRMYmnRjaBynz7KJPlyVe0tzQGBjhrhG/m0gjV+57LUZYoEeBcS7JlS7JBZb/nFIrIRDkDZcuBx94brt3bG8eGe2xl35ZF50wOIceQnRzqAfay9yEa5jZ2ZlscMSb35/B7HwrFcdTjedrsc6Fb41ruqeRxY8AzsUhRkbgqGu8qSzKhVIc5BaVVXBmVQmtc1zKBk2KiGoDGGKctCFfoWm/DJUycY045aeMFSl2GyoXhpKV4s0Aze/PIxIN4oYiFMkamLAs2GKIGNc04loG4hm3j1NdyBIRVOvOxeQvvDkWhVCiZ5HBLiHtynOjNb0yNlpon7BiGk/pBplHerZzVqUWr2HuOViJjSzMIjfDDpJlMOijFM8XfRiDKfbFAJR1qEVIy7/hAkRiIMoIVRM/1jlFK0w6bm8yXGICgdIJzT767gr2caS8PSiR1IydE2IWQYBJfoCTaPqnRlMR9GAwttGGRwgrDtqSCMSh//dPR6Qyv3cr3v7UpX92bnZAWQl0JeSG0lXAuhGsllElwaiXUhaBXQlsIx0q4FoJZCIdaCHYl6IXgVsKxiJtWglkIeSXYhXCuBLes4VeCXwhhJYSFEFfC4g+3SbX4w21SLf5wm1SLP9zq2mP1x+raY/XH6tpj9cfq2mPxh19daxZ/+NW1ZvGHX11rFn/41bVm8YdfXWsWf/jVtcaNTMR3yUT4f23OHk2/jTP5UO1U/a9GY67+Z0IzAF/RpSeYx7c4hv+gR9UywEmZ9oluoqmf+FtlNcCwNY0fbfTQwmxK6NP8NocJJrfYHMw7OnXlc5GcF9G1QzrLkUnOK14AKq/1scKmHvUZ3vm9re9Ij7f1LdmB6a2HGIA1tTT4RaM+wZb8dl6XBjgoo5/4dSkCzr/a1X7qK+U3ptkxX9nzCdYnwl55/wSzfAw3ta8v5ZFwc20I2JUa+kiY9dVR+08w20PCUl+GSzrUHj+He7L3HacES3uzf7XwF9uD6QxL+aU8b/ylPpdGOst3KGMHf4P848t4GQ9y/NiHeLLDNLPtw6tvQw3ppMS+MixrTFjVNiTGG2zJTKqiGFahWyQ/CXuHYpaOeYIrhVWK+nziz+uflAbe4G7G69P8RuNn2NhHfd7mR0oDkh+7ub3Iw3SGJT+mS/5s7yUNqSd78bY1PTDvMIDKnDAMwp6O7UjHymTv2kF+Lnv473JI2JGcb/OrsIMTemll1RPMfpH0KuzMcFJIz9oksd7Gzyh7PI2XsFaYHp3D7SzhS2MZ7FAZ6VnAHPfNtBPgN/sUsoeUT45/mx+EPYuIoyLoQdDlfCfijGGpz10eVBvpn+d3CY91PsNv/mH6iNM001Xb4rSNdGVN5u3YojUbm7iHiYQjVXWGL8qSLCbDrKY2aquCpe+wzcxKmFlsC16P3SrX13FPBwy/6SfXy+p5/Nt85u8pTEtEfaS+KeL4lNBNcrxcX46XsLT3cHMe5076Er+6+TggG+Wl5Wx7jt2N2ISR29qCnuNiAxvpPemlvkqaGe8SpvJxX+UHrD7DkcYvmbqtO5jXe1v/EKHB8/sJUpEr09N6d6gRLMdzKKto9Kf1GB5WhPOWJl/ll07e2YYbubfOwyABFculhpH6BDxbgmKf4BywJbCxDvhQecSguyy2ILYe63oSzqk6TJV+tBxSPj7BWHUGcQIaimdKVUVb/wRLeSQs15PwkXB9lu8HTI7MMdhP9J68/Sd6jXE4WtqjUyo6OmwnQmkPF2P5RD9VrE/0W74Yr0903y3+JF8m+Vj/N/mvGD7q51Qwn+wT4rP9Z4vm/Sd6ig7lFfF6bzRV3Yjfl/klevuJP+s3NuK436B8po/9YgCauAjVkc9kQbnRDFY6g3nl2iN8V0s/zkzZYcq4ot+qZyNJ3+A+frhaXdgkZbL83byqcHzi72l9yW9WD4T5TFVd2JoUFcOx0rPzZmsShbys75wv1qf17sOB2uVhfe4UTbDU5z4zEsxnxtT7gVVe5UJb6Z7sx2c+rZH+Zt+icCe/0QPReT3j4rk31bF+gnPEncryGXEGZn0kzPJbjeuxfN3gbT/cxO3Og+OX7xBcxHiVsLSXhGW8yPgrCdezCuPlB0yVyV7ePMUXHwr6Av4J5vnX6dwqf1LO792ZS5/go2v8yT7M741/pUwl5x/cxGuvn2C+Y6gplGd4jycZf9Lfb/7PCiuNjC+On6bRf2/xbWJ4zF9v8sj5jSqNtI/mTK6dfYLf9gPDMl64MjB/uZ6Ef8SriKe7Gyf/yniZlczFT/mR5ZXxPltKrExyP3GlfdtvTOf8LP3Jlf4k+7tUC+VTt9IZlvnkruTUSch8NTuppD7N19SpyHiep7tYP9E9dUoyn7P+hjotmc/n3XzUT/aZlyDBf6Kz/WQ8T/47nevF1C9cT/Vi3lnudM4ns77u8VfEnWkRd8xK1FeG2f/3fuVOkGCmJ4onpjMs68k8Qu355iJ/zU4rlqd8NE+7O53zzX1pE/f4ZP9Ied/oUr+D/C33Q+U7Zhfi03iZn+X4t/6L/fNGV6L/kv0D2290qvDBrdLBez8xlnFijCaHxEffsF/+Ud/3Rs/Rb3YJcbdbEXlEwuynt/kx7nHX7Y4nEFfQLor7iB1+4/eDP/eJGvXrfWmlum1wPNZ9Cc++zIUn+SS/H/DsS/0nfRmW683L1n2fsz9mHRLfkgTdCzr7e+bhPQ+wvW75CJb+zDPPbn18on01T/i7fjHufXwUeUSrvY9neMkDx/6NFOG3+E3qOb5+jH/xH6//xv/v1mf9xj695mWrFl8F1Lhu9fO6tVJDvByg0n4g2h3r6MDzNl+Ol/ApCggfjfkW2VCDKuFpCGx45PopomGSMecT3BMcftzukf4E88asPYXTR88N5gYqnzUBLOV/s4fU9xT2YH1moCEs15vX1dVst/Lkr3k149OTv+bVD8IQKBZ/qY2Bkp6/IvJdZm8UT/Hx1K13nZLeAzqJRjM+jZ+Nr41rI52jLftdpmh8Cb7tLBLSKRKSEgnphjUeHK5oH+Xha+8j0UFKjJf6yfESlvq82Ythae/lY/VH+7P+b3TWf8SBntf2+y9T7PEbbp+We7Owbh7tnP8En27ffAzPT1r7BXsRF94MDyGPGaxxT2pmBGsy8AMSS98k2t7VPsOzy0X4db74EFDF5wkJX/Hw60V9Ubo+wVfl+1P8BiNhDkZ/qvbEn4PLat2eYP7G46FJbj9h5n/Spz/J35O8RzzKEyztJeXlzRz7v5V+ik+NXqE8s2iIT+IEZ9Kv1uPci4xRT/Z5G9/i/o2Q4b8bP+LQzDg0b9V1OZ7gN2aHhkrUhkl4Xk/uxzmG53XlTufjw/yp1t4maRWPPavErc3i4x+3LfI4GKI4LsadbiN9qLh/ghO8OJ6pNTBjCucTLPWR86U8r/Nf1pf2uI9fxE/aw1bMmjricV6Ol/zl+BEodv42w4rfyh0jUOL8zZ9R0a73jL4G8eMGpHM6bzG6J/g+H5Eicv4sJ3H7eJ/0bshIhnyjGxF4zF+Of5vfKJClvss5/RFezu3qSZ/5BSoeT/rMch3Eb+N2x/4HulekRA==###4272:XlxV32DM    3b24    1098eNqVW0uS7agR3UwvgL+gauKwJx70wB22FyAkNHwRNbAnFbV3p4AUcC6Sb79wR92jTCXklwRkJ5bj/GfDvgn6t1UsxL73eA8pnFiLxZ5YiRR7zPQkFtPTGTPdeq977Kp8Z5PK/N7bGf/Pzy9r7If48N+/pN4/jPr8j9Tbh/r8t9TxQyr9raX2euWBo68TtUkXQUuc4UtxXyayijKwl4V+TdR7lQ2zHycUq198T1/F4nrFeXyUdyd/817M3g++GiK4NMNqSSbzi/o+YHEUrHzYZnjzRza80SHMxkd97/Q3lR/lJXEsWV8Rpvbk8RijPbxIa4/RX1eg+jFQ0R+Mcb5MZ5wDzVGg6RJo+hgCTalvrVqUrX4Mf4OjwCwY51GWFs5ajOEscjg7vbIg74MY1PP+6N25V3cz/RB+6zG+T+54xME/v08c8olOebw/zY/52b221gnkX2u4L2FMFyvGOsKYDY101ofHQ/1YH34f9WN7N8f7Y6Yvy2eM/mA6YtYf9c2B4ilQlhooZgiULccJBSTL8VRY+nEjl7Uqdw1+SFvtfXqiJ5gny0f+u/cDxCHPh+XFl7QNYkzbMa54vvw+47v5Jhg/AJ0xl+UovZ/N50V/4M9+Cl1Cy5uEVrLWZ/+SsDlg7uipBuzt+zWh7uirKAHL60esjkJ+pHcJIJ6wrwnHhnI1AVAeYneU9ViJuMwwryeLjnqGeX1hfpwPB5KHgnDZq9IPLLACEl6MCc/+6hJ6n/mrKwjbFShrW19UnK0vV1mAMmKh7FgoS4zzKLGN8jgIWUaW2EhlbS8r8QtmUxuv1TXIRoO4qso6jJJyyBu9cm8nfdBjL+mPJ2xeTA4ug9rg/OhyB72mAZcy5pDa9baPLcue7aJ1SRHyoJ7xM135Ncz4ueWMIrgZfwvBOj/gD7XWbFCbUF9+H/mRjv648w/bN/t5Jz/b6mc/X4Pa2lvWTlH1UL4MjLil4rhmIV5e1vYqv7aiTvg4w23tH+OG33eytrLVzohlLPP1YjMzzHFwxM3PMM1aFn12McNXPoldPM03QGlCezDOfkpdr5DGNUhmRy2UkFVR42EPIjwkWOlWbQ0Q2gz6Ka49+Qo9OuJYN3sonwMw1j0FYp7fDptJxNqP3Tfrc+0huKlcLkcMCZ9oXmBoBYZWs/GuzXDFqC/vURjvItnMH7c0m8+ud1ua0HWd8aP9kf/FvuDvO/+zfjmQjlbY9VjYY44jqVdOOC2WBHur4wlL2OtJ2AsyvuwIez1sGnfwM+NjLwsYNYF26BVgr73V8ZD/Tr9dzN9Hfo5jVTHqg+8j/+kHK1rh1W7ww579oMkP1S6S98x7kbPXwxTErRkf89OBnR3YOcKenPGyl/i1Qpliv2LnIJQu+pXCuEbtcpwBPxfWNf/vlZ/ptvZ4yJ9k0W+pCwvyo32Q/6pXYm4Ptp8GPzL/nf1170fZ/Cj3+QLKdlZQx7xfhsZDwtnKJsI24782LRV3h3hq2ERVzGdHAs6GeDxdN+cBzpqYnxsPJ8vZFPK3XriMh/xI53wiTw0NAdqH59/qyYiZ/04e82c/qbaAqvHsRxp99s2iO5UReIrgh8S3tRORthiCD7EQXwUYOlaWd3XqYtztBmj/w8upxNhJJOwkoINkTFJkKdxlQeRAo11vXmDiXrDY9jjj58ARutCRnzvgWDsh5F98SeAgo5rx8+7b7qVTQ36211rthfxIR3+1wBntifbdYXumoMNGeciP8cP+uXuf+XOg6hao4qbR44CPXrvxFEQPcaGEHhY85r97f687wDtsq/xrsx6PLD/aurMyc8wdcjqPI/O8xvnxKRNtVMIM+yWJwn/EGTYLN05zjPNFHGKZ31bnd6e/9trMcGsURzrbq50GFozjcR4udeFDezFdi3F+AeQzznFkWhzJMZCOHEdWr0YWudGr4jdfGtK0KzHDfIobRTlZQMx23aLK+YfyV1sbKa+2GW47ej0cAvH7KA+x5J1XkGmGj6qP36We4XXZXWkQ1BRzwy5KWLzYp9VjZWf6tBMKPZXXndyIJ7q7sffVaIsShzkObGv4pb05veSEk8GNK7JwQ0Ii3Qpnx47EDjtJJ2ya4RCLYYMoHQzirSqujtJpIY7V8dRR7DN8bdmXOfahJNj60lFZP9MX+a8OzTu4JrXLeExtl5k9WwEs+M6ejFunPspj+dftnbBuxo/6IX8OFNd1snoIFK++zztYd+1P3XgA5517wgK0itVqfBBJVtRP/AKsIP1oRcYoj70kvFv65Rfnz+/j/JA/W6m73VN6fjC61H1CFAtcmpR+9JYO/XyAfj5APxwgehnzPsZcd9VlH8OY6dxf8z6HMdP3Ko/pO+xXdr0M5yyuHvChfsi/tv2+nfHzPovvonG++D7y373P87+j93fFtrucUzfLJ8vBfUeo+447+irAzx78DPsc5m/t7ehn3ucwTuC3dDMfxHfyEBuIG5bP+28+f0LM+3dVz7MQc5yEuKYZ5rYo+OhmuJ33Rft/7KGf9GGc4yB0VXEIg0BFMbRDV+t1GHtnI2eYixbSVz/2cozZCFZbOSabKafjfOsgzDbjx/khP48n623RC39dKqRQx9N8+X3kz0Zcu2RS86KprlsElyDphw86dmhJTP1gBnHbW9VDkBv5R00mlI/8d+8vkIyIdU0OlM+HKA75xVi0GaO8q2hDcrI+TD+g2HhYVDwsKgsUG8Y4X+TPfj6vJk3x83gW5ihZXLuaXGpHe62wdSOKuF0d6fFkRyg3Nrxqyn/d4lZsa3AfQq0zeTg/5M9Kbu3+VT5ewMbabbVjAOjeoDtjnEfZ2yjb06dKTpixKRBjXWF8nSVVnAdJnSrrkyrJv7RgU9yqgWtL6dFdi8vZKO2g9aWBUTMsWkNzFWonulHc0yhLvV5iqdg2BVguGOdRZDeKfbKYhGbOwKJuYNEfdFEtj9TofUOjmDbKDieHpp5U3dEPOKkycNJo4CTsgO+fGOdZ6s4W+1OMKjiftPAFgIUbfMZ5FNN9tKefRvHwbVeE7wgifGcQu3twZ7tRHpNawdmugksvBZdejPMo3QeIRjxaTCzLaKHxaNzCB4i2+wDRLZ0uj7XjwLmLOW6z6nTx3Sj+Kd8MXEctfvw2eYHrKcY0Sr72ltVgV1L//Fp0ey6752Hp+H17voXuuWzPD9eea9WeK02PiZAfiPxANk63dpxmA878SQVzdnNQZLGR03Wzcp0Wyhvg9Lbj3DrOtVOgn/9m2vOje546fmkaQcvuBdMTtO/e6EynXU/oxtB+7QipI6xbR+i00Hv3hureMKLTW4WOoI6OsHQE1+mh944QOlG6FxW7WNK2Ixz9rDqTWNlHX/Pwz3//JeVZucl3H+L7nxSk1D6cWOuUluPDr0l//l1K/fklpf2My+lmItOUv+mx+fxNStpshM8YfKaIkeA/f2IIt5T1lhLvKKT7HcXcUuwtxd1Rtu2Wst9S0i3luKMkdUu51TTdappuNZWbuifpe5K5J92Ndf77y1/+9m3T8XEstJJ6t9KDv36r7VvqXO+oRnxJiukfepBD88N82Hh82E3Sf5r+sxdDPAOUJm8/KLqJmWKPEoOqAkmihKaKRM+pjadUpTpG5ZcSjWYiJI1yBvcZ+2fAkgBBlfc3SYFClfnnO5zlwJDolSSpk0B2sKcikfLBi8/fZTyz5ne7UGvzZd3nL7mScPpDvhGUF1af2n6HUAWZ88PbV0nyfUkrS3JpJkm9LymypOBmkvTbknK1OSVREE8EmfcFmSpIx6mZ7PuSLEvap2Zy70tybCYxNdPytqRtY0mUhBNJ/n1JO2tnzExSeF9SYkluavH1fUkHS/JTi8e3JSVVJVkhZpK29yVxYJppYO7vC+LAVNvUTOl9SVdgyqmk421JZ70uosJMUhB/QhLbSc8MHuSfkHQZ6pAzUepPiGJLLbMYD++XJylyY3UGFDVl8qRQ0zc+j1TiZ8+3s2LPCGfvnmaEdNbTGeGg8jh5nsRZ7WYEeRavGSHXohlBn6VlRjBnpZgR7Jn4M4I783hGWM60nBE8ZdnseTiTZkZYzxyYESJF9Oz5dv5/zybPz6+f5IyQKHbqc2ov/vH9B1Vg8fkHVU95tqsn+MoNwOeX3cPHSn+oI6EI+bLU5Ja/+owM+utyJNCPkD1PP7bsafqRPfvlRF63zh82e45++Owp+hGzZ+hHyp74cjT6aXn6YbKl6UexLP1YT0vS3z1b7sspkS1FP/RpGfrrTkvQ35A1px/bqSnp+D+W1EkA
\ No newline at end of file
diff --git a/AppleIIGateSch/ClockVideoGenerator_isim_beh1.wdb b/AppleIIGateSch/ClockVideoGenerator_isim_beh1.wdb
new file mode 100644
index 0000000..093e2eb
Binary files /dev/null and b/AppleIIGateSch/ClockVideoGenerator_isim_beh1.wdb differ
diff --git a/AppleIIGateSch/ClockVideoGenerator_summary.html b/AppleIIGateSch/ClockVideoGenerator_summary.html
new file mode 100644
index 0000000..d9c98a2
--- /dev/null
+++ b/AppleIIGateSch/ClockVideoGenerator_summary.html
@@ -0,0 +1,79 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>ClockVideoGenerator Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>AppleIIGateSch.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>ClockVideoGenerator</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc3s500e-4fg320</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>&nbsp;</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Jun 7 00:01:13 2018</TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 06/07/2018 - 15:05:13</center>
+</BODY></HTML>
\ No newline at end of file
diff --git a/AppleIIGateSch/ClockVideoGenerator_tb.v b/AppleIIGateSch/ClockVideoGenerator_tb.v
new file mode 100644
index 0000000..7b4a362
--- /dev/null
+++ b/AppleIIGateSch/ClockVideoGenerator_tb.v
@@ -0,0 +1,104 @@
+// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\ClockVideoGenerator.sch - Sun Jun 03 21:54:27 2018
+
+`timescale 1ns / 1ps
+
+module ClockVideoGenerator_ClockVideoGenerator_sch_tb();
+
+// Inputs
+   reg SOFT5_A2_11;
+   reg SOFT5_A2_8;
+   reg CLK_14o3M;
+
+// Output
+   wire VA;
+   wire V5;
+   wire V4;
+   wire V3;
+   wire V2;
+   wire V1;
+   wire V0;
+   wire VC;
+   wire VB;
+   wire H5;
+   wire H4;
+   wire H3;
+   wire H2;
+   wire H1;
+   wire H0;
+   wire RASn;
+   wire CASn;
+   wire AX;
+   wire Q3;
+   wire LDPSn;
+   wire LD194;
+   wire PHI0;
+   wire PHI1;
+   wire COLOR_REF;
+   wire c7M;
+   wire c7Mn;
+
+// Bidirs
+
+// TB vars and stuff
+  integer i;
+
+// Instantiate the UUT
+  ClockVideoGenerator UUT (
+		.SOFT5_A2_11(SOFT5_A2_11), 
+		.V5(V5), 
+		.V4(V4), 
+		.V3(V3), 
+		.V2(V2), 
+		.V1(V1), 
+		.V0(V0), 
+		.VC(VC), 
+		.VB(VB), 
+		.VA(VA), 
+		.H5(H5), 
+		.H4(H4), 
+		.H3(H3), 
+		.H2(H2), 
+		.H1(H1), 
+		.H0(H0), 
+		.SOFT5_A2_8(SOFT5_A2_8), 
+		.RASn(RASn), 
+		.CASn(CASn), 
+		.AX(AX), 
+		.Q3(Q3), 
+		.LDPSn(LDPSn), 
+		.LD194(LD194), 
+		.PHI0(PHI0), 
+		.PHI1(PHI1), 
+		.COLOR_REF(COLOR_REF), 
+		.c7M(c7M), 
+		.c7Mn(c7Mn), 
+		.CLK_14o3M(CLK_14o3M)
+   );
+// Initialize Inputs
+  `ifdef auto_init
+    initial begin
+      $display("auto_init set");
+    end
+  `else
+    initial begin
+      $display("NOT SET auto_init");
+    end
+ `endif
+  initial begin  
+	  SOFT5_A2_11 = 0;
+	  SOFT5_A2_8  = 0;
+    #5
+	  SOFT5_A2_11 = 1;
+	  SOFT5_A2_8  = 1;
+    #5
+    CLK_14o3M = 0;
+    #100
+    for (i=0; i<3000; i = i + 1) begin
+      CLK_14o3M = 0;
+      #5;
+      CLK_14o3M = 1;
+      #5;
+    end
+    $finish;
+  end
+endmodule
diff --git a/AppleIIGateSch/JK_FlipFlop.jhd b/AppleIIGateSch/JK_FlipFlop.jhd
new file mode 100644
index 0000000..acb80b5
--- /dev/null
+++ b/AppleIIGateSch/JK_FlipFlop.jhd
@@ -0,0 +1 @@
+MODULE JK_FlipFlop
diff --git a/AppleIIGateSch/JK_FlipFlop.sch b/AppleIIGateSch/JK_FlipFlop.sch
new file mode 100644
index 0000000..a37ab31
--- /dev/null
+++ b/AppleIIGateSch/JK_FlipFlop.sch
@@ -0,0 +1,134 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+    <attr value="spartan3e" name="DeviceFamilyName">
+        <trait delete="all:0" />
+        <trait editname="all:0" />
+        <trait edittrait="all:0" />
+    </attr>
+    <netlist>
+        <signal name="Q" />
+        <signal name="Qnot" />
+        <signal name="XLXN_6" />
+        <signal name="XLXN_7" />
+        <signal name="CLK" />
+        <signal name="J" />
+        <signal name="K" />
+        <port polarity="Output" name="Q" />
+        <port polarity="Output" name="Qnot" />
+        <port polarity="Input" name="CLK" />
+        <port polarity="Input" name="J" />
+        <port polarity="Input" name="K" />
+        <blockdef name="nand2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="216" y1="-96" y2="-96" x1="256" />
+            <circle r="12" cx="204" cy="-96" />
+            <line x2="64" y1="-48" y2="-144" x1="64" />
+            <line x2="144" y1="-144" y2="-144" x1="64" />
+            <line x2="64" y1="-48" y2="-48" x1="144" />
+            <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+        </blockdef>
+        <blockdef name="nand3">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="216" y1="-128" y2="-128" x1="256" />
+            <circle r="12" cx="204" cy="-128" />
+            <line x2="144" y1="-176" y2="-176" x1="64" />
+            <line x2="64" y1="-80" y2="-80" x1="144" />
+            <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+            <line x2="64" y1="-64" y2="-192" x1="64" />
+        </blockdef>
+        <block symbolname="nand2" name="XLXI_1">
+            <blockpin signalname="Qnot" name="I0" />
+            <blockpin signalname="XLXN_6" name="I1" />
+            <blockpin signalname="Q" name="O" />
+        </block>
+        <block symbolname="nand2" name="XLXI_2">
+            <blockpin signalname="XLXN_7" name="I0" />
+            <blockpin signalname="Q" name="I1" />
+            <blockpin signalname="Qnot" name="O" />
+        </block>
+        <block symbolname="nand3" name="XLXI_3">
+            <blockpin signalname="CLK" name="I0" />
+            <blockpin signalname="J" name="I1" />
+            <blockpin signalname="Qnot" name="I2" />
+            <blockpin signalname="XLXN_6" name="O" />
+        </block>
+        <block symbolname="nand3" name="XLXI_4">
+            <blockpin signalname="Q" name="I0" />
+            <blockpin signalname="K" name="I1" />
+            <blockpin signalname="CLK" name="I2" />
+            <blockpin signalname="XLXN_7" name="O" />
+        </block>
+    </netlist>
+    <sheet sheetnum="1" width="3520" height="2720">
+        <instance x="1312" y="640" name="XLXI_1" orien="R0" />
+        <instance x="1312" y="992" name="XLXI_2" orien="R0" />
+        <branch name="Q">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1744" y="544" type="branch" />
+            <wire x2="976" y1="992" y2="1040" x1="976" />
+            <wire x2="1680" y1="1040" y2="1040" x1="976" />
+            <wire x2="1312" y1="816" y2="816" x1="1296" />
+            <wire x2="1584" y1="816" y2="816" x1="1312" />
+            <wire x2="1296" y1="816" y2="864" x1="1296" />
+            <wire x2="1312" y1="864" y2="864" x1="1296" />
+            <wire x2="1584" y1="544" y2="544" x1="1568" />
+            <wire x2="1584" y1="544" y2="608" x1="1584" />
+            <wire x2="1584" y1="608" y2="816" x1="1584" />
+            <wire x2="1680" y1="544" y2="544" x1="1584" />
+            <wire x2="1680" y1="544" y2="1040" x1="1680" />
+            <wire x2="1744" y1="544" y2="544" x1="1680" />
+            <wire x2="1840" y1="544" y2="544" x1="1744" />
+        </branch>
+        <branch name="Qnot">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1744" y="896" type="branch" />
+            <wire x2="1664" y1="416" y2="416" x1="976" />
+            <wire x2="1664" y1="416" y2="896" x1="1664" />
+            <wire x2="1744" y1="896" y2="896" x1="1664" />
+            <wire x2="1824" y1="896" y2="896" x1="1744" />
+            <wire x2="976" y1="416" y2="448" x1="976" />
+            <wire x2="1312" y1="576" y2="576" x1="1296" />
+            <wire x2="1296" y1="576" y2="688" x1="1296" />
+            <wire x2="1312" y1="688" y2="688" x1="1296" />
+            <wire x2="1616" y1="688" y2="688" x1="1312" />
+            <wire x2="1616" y1="688" y2="896" x1="1616" />
+            <wire x2="1664" y1="896" y2="896" x1="1616" />
+            <wire x2="1616" y1="896" y2="896" x1="1568" />
+        </branch>
+        <instance x="976" y="640" name="XLXI_3" orien="R0" />
+        <instance x="976" y="1056" name="XLXI_4" orien="R0" />
+        <branch name="XLXN_6">
+            <wire x2="1312" y1="512" y2="512" x1="1232" />
+        </branch>
+        <branch name="XLXN_7">
+            <wire x2="1312" y1="928" y2="928" x1="1232" />
+        </branch>
+        <branch name="CLK">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="832" y="720" type="branch" />
+            <wire x2="832" y1="720" y2="720" x1="784" />
+            <wire x2="896" y1="720" y2="720" x1="832" />
+            <wire x2="896" y1="720" y2="864" x1="896" />
+            <wire x2="976" y1="864" y2="864" x1="896" />
+            <wire x2="976" y1="576" y2="576" x1="896" />
+            <wire x2="896" y1="576" y2="720" x1="896" />
+        </branch>
+        <branch name="J">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="848" y="512" type="branch" />
+            <wire x2="848" y1="512" y2="512" x1="784" />
+            <wire x2="976" y1="512" y2="512" x1="848" />
+        </branch>
+        <branch name="K">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="848" y="928" type="branch" />
+            <wire x2="848" y1="928" y2="928" x1="784" />
+            <wire x2="976" y1="928" y2="928" x1="848" />
+        </branch>
+        <iomarker fontsize="28" x="1840" y="544" name="Q" orien="R0" />
+        <iomarker fontsize="28" x="1824" y="896" name="Qnot" orien="R0" />
+        <iomarker fontsize="28" x="784" y="512" name="J" orien="R180" />
+        <iomarker fontsize="28" x="784" y="720" name="CLK" orien="R180" />
+        <iomarker fontsize="28" x="784" y="928" name="K" orien="R180" />
+    </sheet>
+</drawing>
\ No newline at end of file
diff --git a/AppleIIGateSch/JK_FlipFlop.schlog b/AppleIIGateSch/JK_FlipFlop.schlog
new file mode 100644
index 0000000..49a37aa
--- /dev/null
+++ b/AppleIIGateSch/JK_FlipFlop.schlog
@@ -0,0 +1,4 @@
+select figure at 1586 606 8 -branches -sn=1
+select figure at 1851 891 8 -branches -sn=1
+select figure at 1838 986 8 -branches -sn=1
+select figure at 2039 1088 8 -branches -sn=1
diff --git a/AppleIIGateSch/JK_FlipFlop.sym b/AppleIIGateSch/JK_FlipFlop.sym
new file mode 100644
index 0000000..92e65cb
--- /dev/null
+++ b/AppleIIGateSch/JK_FlipFlop.sym
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="JK_FlipFlop">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2018-5-22T0:7:17</timestamp>
+    <pin polarity="Input" x="0" y="-96" name="CLK" />
+    <pin polarity="Input" x="0" y="-160" name="J" />
+    <pin polarity="Input" x="0" y="-32" name="K" />
+    <pin polarity="Output" x="384" y="-160" name="Q" />
+    <pin polarity="Output" x="384" y="-32" name="Qnot" />
+    <graph>
+        <rect width="256" x="64" y="-192" height="192" />
+        <attrtext style="alignment:BCENTER;fontsize:44;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
+        <line x2="0" y1="-96" y2="-96" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin CLK" />
+        <line x2="0" y1="-160" y2="-160" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin J" />
+        <line x2="0" y1="-32" y2="-32" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin K" />
+        <line x2="384" y1="-160" y2="-160" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin Q" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin Qnot" />
+        <line x2="384" y1="-32" y2="-32" x1="320" />
+    </graph>
+</symbol>
diff --git a/AppleIIGateSch/JK_FlipFlop_JK_FlipFlop_sch_tb_beh.prj b/AppleIIGateSch/JK_FlipFlop_JK_FlipFlop_sch_tb_beh.prj
new file mode 100644
index 0000000..1a274f7
--- /dev/null
+++ b/AppleIIGateSch/JK_FlipFlop_JK_FlipFlop_sch_tb_beh.prj
@@ -0,0 +1,3 @@
+verilog work "JK_FlipFlop.vf"
+verilog work "JK_FlipFlop_tb.v"
+verilog work "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
diff --git a/AppleIIGateSch/JK_FlipFlop_tb.v b/AppleIIGateSch/JK_FlipFlop_tb.v
new file mode 100644
index 0000000..5051ff3
--- /dev/null
+++ b/AppleIIGateSch/JK_FlipFlop_tb.v
@@ -0,0 +1,61 @@
+// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\JK_FlipFlop.sch - Mon May 21 17:10:31 2018
+// On positive clock EDGE 
+//   J=0 K=0 outputs Q,Qnot unchanged
+//   J=1 K=1 outputs Q,Qnot toggled.
+//   J=1 K=0 outputs Q=1, Qnot=0
+//   J=0 K=1 outputs Q=0, Qnot=1
+
+`timescale 1ns / 1ps
+
+module JK_FlipFlop_JK_FlipFlop_sch_tb();
+
+// Inputs
+   reg CLK;
+   reg J;
+   reg K;
+
+// Output
+   wire Q;
+   wire Qnot;
+	integer i;
+
+// Bidirs
+
+// Instantiate the UUT
+   JK_FlipFlop UUT (
+		.Q(Q), 
+		.Qnot(Qnot), 
+		.CLK(CLK), 
+		.J(J), 
+		.K(K)
+   );
+// Initialize Inputs
+//   `ifdef auto_init
+//       initial begin
+//		CLK = 0;
+//		J = 0;
+//		K = 0;
+//   `endif
+  initial begin
+    J=0; K=0; CLK=0;
+	 #2 force UUT.Q_DUMMY = 0;  force UUT.Qnot_DUMMY = 1;
+	 #2 CLK=1;
+	 #2 CLK=0;
+	 #2 release UUT.Q_DUMMY;  
+	 #2 release UUT.Qnot_DUMMY;
+    #4;
+	 J = 0;
+	 K = 0;
+	 CLK = 0; #4;
+	 CLK = 1; #4;
+	 
+    for (i=0; i<320; i=i+1) begin
+	   CLK = i & 1;
+		J   = (i >> 1) & 1;
+		K   = (i >> 2) & 1;
+		$display("CLK=%b J=%b K=%b  Q=%b Qnot=%b  clock=%d", CLK, J, K,  Q, Qnot,  $time);
+		#2;
+	 end
+	 // $finish;
+  end
+endmodule
diff --git a/AppleIIGateSch/README.txt b/AppleIIGateSch/README.txt
new file mode 100644
index 0000000..9decea5
--- /dev/null
+++ b/AppleIIGateSch/README.txt
@@ -0,0 +1,24 @@
+I, Frederick Kilner, being of sound mind and body and making a gate level Apple ][ in a FPGA.
+
+Creating a functional gate level Apple II from Apple II schematic. 
+Using Xilinx 14.7 Schematic Entry. Making small test benches of module.
+Design will be loaded in to Nexsys-2 Spartan3E-500 board.
+Also manually entering 74series chips(gate level schemtic).
+
+I didn't find a 74series library so have to enter my own chips.
+
+My goal is to have a functional gate level apple II in an FPGA.
+
+I want to be able to connect it to the composite input of a monitor. I'll need a few analog components for that.
+Also I will want to have a module which reads the generated composite signal and drives the analog VGA port.
+That will probably require a frame buffer unless 59.94Hz refresh rate is okay for some VGA mode.
+
+Voltage level shifters will be needed but I have expansion connections and want to be able to plug in
+real Apple II cards including disk drive card and music card and 80 column card.
+
+I want to be able to prototype Apple II hardware changes in FPGA board.
+
+Verilog generated from Xilinx ISE can be used in Xilinx Vivado project to have apple II on Artix-7 chip. 
+Verilog can be used in other design tool for other chips/boards.. such as Quartus-II or whatever it is now.
+
+FPGA is neat.
\ No newline at end of file
diff --git a/AppleIIGateSch/chip74LS153_tb.v b/AppleIIGateSch/chip74LS153_tb.v
new file mode 100644
index 0000000..8305aac
--- /dev/null
+++ b/AppleIIGateSch/chip74LS153_tb.v
@@ -0,0 +1,108 @@
+// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chipi74LS153.sch - Sun May 27 17:02:08 2018
+
+`timescale 1ns / 1ps
+
+module chipi74LS153_chipi74LS153_sch_tb();
+
+// Inputs
+   reg Ebn_15;
+   reg b0_10;
+   reg b1_11;
+   reg b2_12;
+   reg b3_13;
+   reg Ean_11;
+   reg a0_6;
+   reg a1_5;
+   reg a2_4;
+   reg a3_3;
+   reg S0_14;
+   reg S1_2;
+
+// Output
+   wire Zb_9;
+   wire Za_7;
+   	
+// Simulate test bench vars
+   integer i, j, errct;
+   wire [3:0] abus;
+   wire [3:0] bbus;
+   assign abus = { a3_3, a2_4, a1_5, a0_6 };
+   assign bbus = { b3_13, b2_12, b1_11, b0_10 };
+   reg expectedA, expectedB; // Just for simulation
+
+// Bidirs
+
+// Instantiate the UUT
+   chipi74LS153 UUT (
+		.Zb_9(Zb_9), 
+		.Ebn_15(Ebn_15), 
+		.b0_10(b0_10), 
+		.b1_11(b1_11), 
+		.b2_12(b2_12), 
+		.b3_13(b3_13), 
+		.Za_7(Za_7), 
+		.Ean_11(Ean_11), 
+		.a0_6(a0_6), 
+		.a1_5(a1_5), 
+		.a2_4(a2_4), 
+		.a3_3(a3_3), 
+		.S0_14(S0_14), 
+		.S1_2(S1_2)
+   );
+// Initialize Inputs
+  `ifdef auto_init
+    initial begin
+      $display("auto_init is defined");
+	 end
+  `else
+    initial begin
+      $display("not defined auto_init");
+    end	
+  `endif
+  initial begin	
+    Ebn_15 = 0;
+    b0_10  = 0;
+    b1_11  = 0;
+    b2_12  = 0;
+    b3_13  = 0;
+    Ean_11 = 0;
+    a0_6  = 0;
+    a1_5  = 0;
+    a2_4  = 0;
+    a3_3  = 0;
+    S0_14 = 0;
+    S1_2  = 0;
+    errct = 0;
+    #5;
+    for (i=0; i<256; i=i+1) begin
+		  a0_6 = i[0];
+		  a1_5 = i[1];
+		  a2_4 = i[2];
+		  a3_3 = i[3];
+		  b0_10 = i[4];
+		  b1_11 = i[5];
+		  b2_12 = i[6];
+		  b3_13 = i[7];
+		  #10;
+		  for (j=0; j<16; j=j+1) begin
+		    Ean_11 = j[0];
+			  Ebn_15 = j[1];
+			  S0_14  = j[2];
+			  S1_2   = j[3];
+			  #5;
+        expectedA = (~Ean_11) & abus[{S1_2,S0_14}];
+        expectedB = (~Ebn_15) & bbus[{S1_2,S0_14}];
+        if (expectedA != Za_7) begin
+          $display("ERR: expectedA=%b Za=%b a=%b S1=%b S0=%b Ean=%b", 
+            expectedA, Za_7, abus, bbus, S1_2, S0_14, Ean_11); 
+          errct = errct + 1;
+        end
+		  end
+		end
+    if ( errct == 0 ) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED  errct=%d", errct);
+    end
+  end
+endmodule
diff --git a/AppleIIGateSch/chip74LS161.jhd b/AppleIIGateSch/chip74LS161.jhd
new file mode 100644
index 0000000..1e513de
--- /dev/null
+++ b/AppleIIGateSch/chip74LS161.jhd
@@ -0,0 +1 @@
+MODULE chip74LS161
diff --git a/AppleIIGateSch/chip74LS161.sch b/AppleIIGateSch/chip74LS161.sch
new file mode 100644
index 0000000..ae2d5f6
--- /dev/null
+++ b/AppleIIGateSch/chip74LS161.sch
@@ -0,0 +1,741 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+    <attr value="spartan3e" name="DeviceFamilyName">
+        <trait delete="all:0" />
+        <trait editname="all:0" />
+        <trait edittrait="all:0" />
+    </attr>
+    <netlist>
+        <signal name="XLXN_11" />
+        <signal name="XLXN_12" />
+        <signal name="XLXN_13" />
+        <signal name="CLK" />
+        <signal name="XLXN_15" />
+        <signal name="XLXN_17" />
+        <signal name="XLXN_19" />
+        <signal name="XLXN_21" />
+        <signal name="XLXN_26" />
+        <signal name="XLXN_28" />
+        <signal name="XLXN_29" />
+        <signal name="XLXN_35" />
+        <signal name="XLXN_36" />
+        <signal name="CLRn" />
+        <signal name="Q1" />
+        <signal name="Q2" />
+        <signal name="Q3" />
+        <signal name="PEn" />
+        <signal name="XLXN_44" />
+        <signal name="XLXN_45" />
+        <signal name="XLXN_48" />
+        <signal name="XLXN_50" />
+        <signal name="XLXN_54" />
+        <signal name="CEP" />
+        <signal name="CET" />
+        <signal name="TC" />
+        <signal name="P0" />
+        <signal name="P1" />
+        <signal name="P2" />
+        <signal name="P3" />
+        <signal name="XLXN_64" />
+        <signal name="XLXN_65" />
+        <signal name="Q0" />
+        <signal name="XLXN_71" />
+        <signal name="XLXN_72" />
+        <signal name="XLXN_76" />
+        <signal name="XLXN_77" />
+        <signal name="XLXN_82" />
+        <signal name="XLXN_83" />
+        <signal name="XLXN_84" />
+        <signal name="XLXN_86" />
+        <signal name="XLXN_87" />
+        <port polarity="Input" name="CLK" />
+        <port polarity="Input" name="CLRn" />
+        <port polarity="Output" name="Q1" />
+        <port polarity="Output" name="Q2" />
+        <port polarity="Output" name="Q3" />
+        <port polarity="Input" name="PEn" />
+        <port polarity="Input" name="CEP" />
+        <port polarity="Input" name="CET" />
+        <port polarity="Output" name="TC" />
+        <port polarity="Input" name="P0" />
+        <port polarity="Input" name="P1" />
+        <port polarity="Input" name="P2" />
+        <port polarity="Input" name="P3" />
+        <port polarity="Output" name="Q0" />
+        <blockdef name="and2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="192" y1="-96" y2="-96" x1="256" />
+            <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+            <line x2="64" y1="-48" y2="-48" x1="144" />
+            <line x2="144" y1="-144" y2="-144" x1="64" />
+            <line x2="64" y1="-48" y2="-144" x1="64" />
+        </blockdef>
+        <blockdef name="or2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="192" y1="-96" y2="-96" x1="256" />
+            <arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
+            <arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
+            <line x2="48" y1="-144" y2="-144" x1="112" />
+            <arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
+            <line x2="48" y1="-48" y2="-48" x1="112" />
+        </blockdef>
+        <blockdef name="nand2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="216" y1="-96" y2="-96" x1="256" />
+            <circle r="12" cx="204" cy="-96" />
+            <line x2="64" y1="-48" y2="-144" x1="64" />
+            <line x2="144" y1="-144" y2="-144" x1="64" />
+            <line x2="64" y1="-48" y2="-48" x1="144" />
+            <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+        </blockdef>
+        <blockdef name="nand3">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="216" y1="-128" y2="-128" x1="256" />
+            <circle r="12" cx="204" cy="-128" />
+            <line x2="144" y1="-176" y2="-176" x1="64" />
+            <line x2="64" y1="-80" y2="-80" x1="144" />
+            <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+            <line x2="64" y1="-64" y2="-192" x1="64" />
+        </blockdef>
+        <blockdef name="or2b2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="32" y1="-64" y2="-64" x1="0" />
+            <circle r="12" cx="44" cy="-64" />
+            <line x2="32" y1="-128" y2="-128" x1="0" />
+            <circle r="12" cx="44" cy="-128" />
+            <line x2="192" y1="-96" y2="-96" x1="256" />
+            <arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
+            <line x2="48" y1="-48" y2="-48" x1="112" />
+            <arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
+            <line x2="48" y1="-144" y2="-144" x1="112" />
+            <arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
+        </blockdef>
+        <blockdef name="and3">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="192" y1="-128" y2="-128" x1="256" />
+            <line x2="144" y1="-176" y2="-176" x1="64" />
+            <line x2="64" y1="-80" y2="-80" x1="144" />
+            <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+            <line x2="64" y1="-64" y2="-192" x1="64" />
+        </blockdef>
+        <blockdef name="and4">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-112" y2="-112" x1="144" />
+            <arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
+            <line x2="144" y1="-208" y2="-208" x1="64" />
+            <line x2="64" y1="-64" y2="-256" x1="64" />
+            <line x2="192" y1="-160" y2="-160" x1="256" />
+            <line x2="64" y1="-256" y2="-256" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+        </blockdef>
+        <blockdef name="and5">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <arc ex="144" ey="-240" sx="144" sy="-144" r="48" cx="144" cy="-192" />
+            <line x2="64" y1="-144" y2="-144" x1="144" />
+            <line x2="144" y1="-240" y2="-240" x1="64" />
+            <line x2="64" y1="-64" y2="-320" x1="64" />
+            <line x2="192" y1="-192" y2="-192" x1="256" />
+            <line x2="64" y1="-320" y2="-320" x1="0" />
+            <line x2="64" y1="-256" y2="-256" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+        </blockdef>
+        <blockdef name="fjkc">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="64" y1="-320" y2="-320" x1="0" />
+            <line x2="320" y1="-256" y2="-256" x1="384" />
+            <line x2="64" y1="-256" y2="-256" x1="0" />
+            <line x2="64" y1="-32" y2="-32" x1="192" />
+            <line x2="192" y1="-64" y2="-32" x1="192" />
+            <line x2="64" y1="-128" y2="-144" x1="80" />
+            <line x2="80" y1="-112" y2="-128" x1="64" />
+            <rect width="256" x="64" y="-384" height="320" />
+        </blockdef>
+        <blockdef name="buf">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="128" y1="-32" y2="-32" x1="224" />
+            <line x2="128" y1="0" y2="-32" x1="64" />
+            <line x2="64" y1="-32" y2="-64" x1="128" />
+            <line x2="64" y1="-64" y2="0" x1="64" />
+        </blockdef>
+        <blockdef name="inv">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="160" y1="-32" y2="-32" x1="224" />
+            <line x2="128" y1="-64" y2="-32" x1="64" />
+            <line x2="64" y1="-32" y2="0" x1="128" />
+            <line x2="64" y1="0" y2="-64" x1="64" />
+            <circle r="16" cx="144" cy="-32" />
+        </blockdef>
+        <block symbolname="and2" name="XLXI_5">
+            <blockpin signalname="XLXN_86" name="I0" />
+            <blockpin signalname="XLXN_15" name="I1" />
+            <blockpin signalname="XLXN_64" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_6">
+            <blockpin signalname="XLXN_35" name="I0" />
+            <blockpin signalname="XLXN_86" name="I1" />
+            <blockpin signalname="XLXN_65" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_7">
+            <blockpin signalname="XLXN_11" name="I0" />
+            <blockpin signalname="XLXN_17" name="I1" />
+            <blockpin signalname="XLXN_71" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_8">
+            <blockpin signalname="XLXN_26" name="I0" />
+            <blockpin signalname="XLXN_11" name="I1" />
+            <blockpin signalname="XLXN_72" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_9">
+            <blockpin signalname="XLXN_12" name="I0" />
+            <blockpin signalname="XLXN_19" name="I1" />
+            <blockpin signalname="XLXN_76" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_10">
+            <blockpin signalname="XLXN_28" name="I0" />
+            <blockpin signalname="XLXN_12" name="I1" />
+            <blockpin signalname="XLXN_77" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_11">
+            <blockpin signalname="XLXN_13" name="I0" />
+            <blockpin signalname="XLXN_21" name="I1" />
+            <blockpin signalname="XLXN_82" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_12">
+            <blockpin signalname="XLXN_29" name="I0" />
+            <blockpin signalname="XLXN_13" name="I1" />
+            <blockpin signalname="XLXN_83" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_14">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_45" name="I1" />
+            <blockpin signalname="XLXN_11" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_15">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_48" name="I1" />
+            <blockpin signalname="XLXN_12" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_16">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_50" name="I1" />
+            <blockpin signalname="XLXN_13" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_17">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_54" name="I1" />
+            <blockpin signalname="XLXN_86" name="O" />
+        </block>
+        <block symbolname="nand2" name="XLXI_18">
+            <blockpin signalname="XLXN_35" name="I0" />
+            <blockpin signalname="XLXN_36" name="I1" />
+            <blockpin signalname="XLXN_15" name="O" />
+        </block>
+        <block symbolname="nand2" name="XLXI_20">
+            <blockpin signalname="XLXN_26" name="I0" />
+            <blockpin signalname="XLXN_36" name="I1" />
+            <blockpin signalname="XLXN_17" name="O" />
+        </block>
+        <block symbolname="nand2" name="XLXI_24">
+            <blockpin signalname="XLXN_28" name="I0" />
+            <blockpin signalname="XLXN_36" name="I1" />
+            <blockpin signalname="XLXN_19" name="O" />
+        </block>
+        <block symbolname="nand2" name="XLXI_26">
+            <blockpin signalname="XLXN_29" name="I0" />
+            <blockpin signalname="XLXN_36" name="I1" />
+            <blockpin signalname="XLXN_21" name="O" />
+        </block>
+        <block symbolname="nand3" name="XLXI_28">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_44" name="I1" />
+            <blockpin signalname="P0" name="I2" />
+            <blockpin signalname="XLXN_35" name="O" />
+        </block>
+        <block symbolname="nand3" name="XLXI_29">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_44" name="I1" />
+            <blockpin signalname="P1" name="I2" />
+            <blockpin signalname="XLXN_26" name="O" />
+        </block>
+        <block symbolname="nand3" name="XLXI_30">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_44" name="I1" />
+            <blockpin signalname="P2" name="I2" />
+            <blockpin signalname="XLXN_28" name="O" />
+        </block>
+        <block symbolname="nand3" name="XLXI_31">
+            <blockpin signalname="XLXN_44" name="I0" />
+            <blockpin signalname="XLXN_36" name="I1" />
+            <blockpin signalname="P3" name="I2" />
+            <blockpin signalname="XLXN_29" name="O" />
+        </block>
+        <block symbolname="or2b2" name="XLXI_33">
+            <blockpin signalname="XLXN_44" name="I0" />
+            <blockpin signalname="PEn" name="I1" />
+            <blockpin signalname="XLXN_36" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_34">
+            <blockpin signalname="XLXN_54" name="I0" />
+            <blockpin signalname="Q0" name="I1" />
+            <blockpin signalname="XLXN_45" name="O" />
+        </block>
+        <block symbolname="and3" name="XLXI_35">
+            <blockpin signalname="XLXN_54" name="I0" />
+            <blockpin signalname="Q0" name="I1" />
+            <blockpin signalname="Q1" name="I2" />
+            <blockpin signalname="XLXN_48" name="O" />
+        </block>
+        <block symbolname="and4" name="XLXI_36">
+            <blockpin signalname="XLXN_54" name="I0" />
+            <blockpin signalname="Q0" name="I1" />
+            <blockpin signalname="Q1" name="I2" />
+            <blockpin signalname="Q2" name="I3" />
+            <blockpin signalname="XLXN_50" name="O" />
+        </block>
+        <block symbolname="and5" name="XLXI_37">
+            <blockpin signalname="CET" name="I0" />
+            <blockpin signalname="Q0" name="I1" />
+            <blockpin signalname="Q1" name="I2" />
+            <blockpin signalname="Q2" name="I3" />
+            <blockpin signalname="Q3" name="I4" />
+            <blockpin signalname="TC" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_38">
+            <blockpin signalname="CET" name="I0" />
+            <blockpin signalname="CEP" name="I1" />
+            <blockpin signalname="XLXN_54" name="O" />
+        </block>
+        <block symbolname="fjkc" name="XLXI_39">
+            <blockpin signalname="XLXN_84" name="C" />
+            <blockpin signalname="XLXN_87" name="CLR" />
+            <blockpin signalname="XLXN_64" name="J" />
+            <blockpin signalname="XLXN_65" name="K" />
+            <blockpin signalname="Q0" name="Q" />
+        </block>
+        <block symbolname="fjkc" name="XLXI_40">
+            <blockpin signalname="XLXN_84" name="C" />
+            <blockpin signalname="XLXN_87" name="CLR" />
+            <blockpin signalname="XLXN_71" name="J" />
+            <blockpin signalname="XLXN_72" name="K" />
+            <blockpin signalname="Q1" name="Q" />
+        </block>
+        <block symbolname="fjkc" name="XLXI_41">
+            <blockpin signalname="XLXN_84" name="C" />
+            <blockpin signalname="XLXN_87" name="CLR" />
+            <blockpin signalname="XLXN_76" name="J" />
+            <blockpin signalname="XLXN_77" name="K" />
+            <blockpin signalname="Q2" name="Q" />
+        </block>
+        <block symbolname="fjkc" name="XLXI_42">
+            <blockpin signalname="XLXN_84" name="C" />
+            <blockpin signalname="XLXN_87" name="CLR" />
+            <blockpin signalname="XLXN_82" name="J" />
+            <blockpin signalname="XLXN_83" name="K" />
+            <blockpin signalname="Q3" name="Q" />
+        </block>
+        <block symbolname="buf" name="XLXI_43">
+            <blockpin signalname="CLK" name="I" />
+            <blockpin signalname="XLXN_84" name="O" />
+        </block>
+        <block symbolname="buf" name="XLXI_44">
+            <blockpin signalname="CLRn" name="I" />
+            <blockpin signalname="XLXN_44" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_45">
+            <blockpin signalname="XLXN_44" name="I" />
+            <blockpin signalname="XLXN_87" name="O" />
+        </block>
+    </netlist>
+    <sheet sheetnum="1" width="3520" height="2720">
+        <instance x="2368" y="1824" name="XLXI_11" orien="R0" />
+        <branch name="CLK">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="320" y="1232" type="branch" />
+            <wire x2="320" y1="1232" y2="1232" x1="224" />
+            <wire x2="400" y1="1232" y2="1232" x1="320" />
+        </branch>
+        <instance x="1984" y="1120" name="XLXI_14" orien="R0" />
+        <branch name="XLXN_21">
+            <wire x2="2368" y1="1696" y2="1696" x1="1920" />
+        </branch>
+        <instance x="1664" y="1264" name="XLXI_29" orien="R0" />
+        <instance x="1664" y="1392" name="XLXI_24" orien="R0" />
+        <instance x="1664" y="1648" name="XLXI_30" orien="R0" />
+        <instance x="1664" y="1792" name="XLXI_26" orien="R0" />
+        <instance x="1664" y="992" name="XLXI_20" orien="R0" />
+        <branch name="XLXN_26">
+            <wire x2="1664" y1="928" y2="928" x1="1648" />
+            <wire x2="1648" y1="928" y2="960" x1="1648" />
+            <wire x2="1936" y1="960" y2="960" x1="1648" />
+            <wire x2="1936" y1="960" y2="1136" x1="1936" />
+            <wire x2="2352" y1="1136" y2="1136" x1="1936" />
+            <wire x2="1936" y1="1136" y2="1136" x1="1920" />
+            <wire x2="2368" y1="1056" y2="1056" x1="2352" />
+            <wire x2="2352" y1="1056" y2="1136" x1="2352" />
+        </branch>
+        <branch name="XLXN_28">
+            <wire x2="1664" y1="1328" y2="1328" x1="1648" />
+            <wire x2="1648" y1="1328" y2="1360" x1="1648" />
+            <wire x2="1936" y1="1360" y2="1360" x1="1648" />
+            <wire x2="1936" y1="1360" y2="1520" x1="1936" />
+            <wire x2="2160" y1="1520" y2="1520" x1="1936" />
+            <wire x2="1936" y1="1520" y2="1520" x1="1920" />
+            <wire x2="2160" y1="1472" y2="1520" x1="2160" />
+            <wire x2="2384" y1="1472" y2="1472" x1="2160" />
+        </branch>
+        <branch name="XLXN_29">
+            <wire x2="1664" y1="1728" y2="1728" x1="1648" />
+            <wire x2="1648" y1="1728" y2="1760" x1="1648" />
+            <wire x2="1936" y1="1760" y2="1760" x1="1648" />
+            <wire x2="1936" y1="1760" y2="1936" x1="1936" />
+            <wire x2="1936" y1="1936" y2="1968" x1="1936" />
+            <wire x2="2144" y1="1936" y2="1936" x1="1936" />
+            <wire x2="1936" y1="1968" y2="1968" x1="1920" />
+            <wire x2="2144" y1="1888" y2="1936" x1="2144" />
+            <wire x2="2368" y1="1888" y2="1888" x1="2144" />
+        </branch>
+        <instance x="1664" y="2096" name="XLXI_31" orien="R0" />
+        <instance x="1984" y="1920" name="XLXI_16" orien="R0" />
+        <branch name="XLXN_13">
+            <wire x2="2352" y1="1824" y2="1824" x1="2240" />
+            <wire x2="2368" y1="1824" y2="1824" x1="2352" />
+            <wire x2="2368" y1="1760" y2="1760" x1="2352" />
+            <wire x2="2352" y1="1760" y2="1824" x1="2352" />
+        </branch>
+        <instance x="1664" y="544" name="XLXI_18" orien="R0" />
+        <instance x="1984" y="688" name="XLXI_17" orien="R0" />
+        <instance x="1664" y="848" name="XLXI_28" orien="R0" />
+        <branch name="XLXN_35">
+            <wire x2="1664" y1="480" y2="480" x1="1648" />
+            <wire x2="1648" y1="480" y2="512" x1="1648" />
+            <wire x2="1952" y1="512" y2="512" x1="1648" />
+            <wire x2="1952" y1="512" y2="720" x1="1952" />
+            <wire x2="2352" y1="720" y2="720" x1="1952" />
+            <wire x2="1952" y1="720" y2="720" x1="1920" />
+            <wire x2="2352" y1="576" y2="720" x1="2352" />
+            <wire x2="2368" y1="576" y2="576" x1="2352" />
+        </branch>
+        <branch name="XLXN_36">
+            <wire x2="1552" y1="416" y2="416" x1="1200" />
+            <wire x2="1664" y1="416" y2="416" x1="1552" />
+            <wire x2="1552" y1="416" y2="624" x1="1552" />
+            <wire x2="1984" y1="624" y2="624" x1="1552" />
+            <wire x2="1552" y1="624" y2="784" x1="1552" />
+            <wire x2="1664" y1="784" y2="784" x1="1552" />
+            <wire x2="1552" y1="784" y2="864" x1="1552" />
+            <wire x2="1664" y1="864" y2="864" x1="1552" />
+            <wire x2="1552" y1="864" y2="1056" x1="1552" />
+            <wire x2="1552" y1="1056" y2="1200" x1="1552" />
+            <wire x2="1664" y1="1200" y2="1200" x1="1552" />
+            <wire x2="1552" y1="1200" y2="1264" x1="1552" />
+            <wire x2="1664" y1="1264" y2="1264" x1="1552" />
+            <wire x2="1552" y1="1264" y2="1440" x1="1552" />
+            <wire x2="1552" y1="1440" y2="1584" x1="1552" />
+            <wire x2="1664" y1="1584" y2="1584" x1="1552" />
+            <wire x2="1552" y1="1584" y2="1664" x1="1552" />
+            <wire x2="1664" y1="1664" y2="1664" x1="1552" />
+            <wire x2="1552" y1="1664" y2="1856" x1="1552" />
+            <wire x2="1552" y1="1856" y2="1968" x1="1552" />
+            <wire x2="1664" y1="1968" y2="1968" x1="1552" />
+            <wire x2="1984" y1="1856" y2="1856" x1="1552" />
+            <wire x2="1984" y1="1440" y2="1440" x1="1552" />
+            <wire x2="1984" y1="1056" y2="1056" x1="1552" />
+        </branch>
+        <instance x="1984" y="1504" name="XLXI_15" orien="R0" />
+        <branch name="CLRn">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="432" y="2032" type="branch" />
+            <wire x2="432" y1="2032" y2="2032" x1="368" />
+            <wire x2="496" y1="2032" y2="2032" x1="432" />
+        </branch>
+        <branch name="Q1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3328" y="960" type="branch" />
+            <wire x2="3216" y1="1216" y2="1216" x1="928" />
+            <wire x2="928" y1="1216" y2="1280" x1="928" />
+            <wire x2="928" y1="1280" y2="1760" x1="928" />
+            <wire x2="928" y1="1760" y2="2288" x1="928" />
+            <wire x2="2768" y1="2288" y2="2288" x1="928" />
+            <wire x2="1088" y1="1760" y2="1760" x1="928" />
+            <wire x2="960" y1="1280" y2="1280" x1="928" />
+            <wire x2="3216" y1="960" y2="960" x1="3104" />
+            <wire x2="3216" y1="960" y2="1216" x1="3216" />
+            <wire x2="3328" y1="960" y2="960" x1="3216" />
+            <wire x2="3392" y1="960" y2="960" x1="3328" />
+        </branch>
+        <branch name="Q3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3328" y="1792" type="branch" />
+            <wire x2="2768" y1="2080" y2="2160" x1="2768" />
+            <wire x2="3216" y1="2080" y2="2080" x1="2768" />
+            <wire x2="3216" y1="1792" y2="1792" x1="3104" />
+            <wire x2="3216" y1="1792" y2="2080" x1="3216" />
+            <wire x2="3328" y1="1792" y2="1792" x1="3216" />
+            <wire x2="3392" y1="1792" y2="1792" x1="3328" />
+        </branch>
+        <instance x="944" y="512" name="XLXI_33" orien="R0" />
+        <branch name="PEn">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="496" y="384" type="branch" />
+            <wire x2="496" y1="384" y2="384" x1="416" />
+            <wire x2="944" y1="384" y2="384" x1="496" />
+        </branch>
+        <instance x="960" y="1088" name="XLXI_34" orien="R0" />
+        <branch name="XLXN_45">
+            <wire x2="1984" y1="992" y2="992" x1="1216" />
+        </branch>
+        <branch name="XLXN_50">
+            <wire x2="1984" y1="1792" y2="1792" x1="1344" />
+        </branch>
+        <instance x="1088" y="1952" name="XLXI_36" orien="R0" />
+        <instance x="2768" y="2480" name="XLXI_37" orien="R0" />
+        <instance x="480" y="2400" name="XLXI_38" orien="R0" />
+        <branch name="CEP">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="304" y="2272" type="branch" />
+            <wire x2="304" y1="2272" y2="2272" x1="224" />
+            <wire x2="480" y1="2272" y2="2272" x1="304" />
+        </branch>
+        <branch name="CET">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="304" y="2336" type="branch" />
+            <wire x2="304" y1="2336" y2="2336" x1="224" />
+            <wire x2="464" y1="2336" y2="2336" x1="304" />
+            <wire x2="480" y1="2336" y2="2336" x1="464" />
+            <wire x2="464" y1="2336" y2="2416" x1="464" />
+            <wire x2="2768" y1="2416" y2="2416" x1="464" />
+        </branch>
+        <branch name="TC">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="2288" type="branch" />
+            <wire x2="3104" y1="2288" y2="2288" x1="3024" />
+            <wire x2="3184" y1="2288" y2="2288" x1="3104" />
+        </branch>
+        <branch name="P0">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="496" y="656" type="branch" />
+            <wire x2="496" y1="656" y2="656" x1="432" />
+            <wire x2="1664" y1="656" y2="656" x1="496" />
+        </branch>
+        <branch name="P1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1072" type="branch" />
+            <wire x2="512" y1="1072" y2="1072" x1="448" />
+            <wire x2="1664" y1="1072" y2="1072" x1="512" />
+        </branch>
+        <instance x="960" y="1472" name="XLXI_35" orien="R0" />
+        <branch name="XLXN_54">
+            <wire x2="848" y1="2304" y2="2304" x1="736" />
+            <wire x2="1984" y1="560" y2="560" x1="848" />
+            <wire x2="848" y1="560" y2="1024" x1="848" />
+            <wire x2="960" y1="1024" y2="1024" x1="848" />
+            <wire x2="848" y1="1024" y2="1408" x1="848" />
+            <wire x2="960" y1="1408" y2="1408" x1="848" />
+            <wire x2="848" y1="1408" y2="1888" x1="848" />
+            <wire x2="1088" y1="1888" y2="1888" x1="848" />
+            <wire x2="848" y1="1888" y2="2304" x1="848" />
+        </branch>
+        <branch name="XLXN_48">
+            <wire x2="1584" y1="1344" y2="1344" x1="1216" />
+            <wire x2="1584" y1="1344" y2="1376" x1="1584" />
+            <wire x2="1984" y1="1376" y2="1376" x1="1584" />
+        </branch>
+        <branch name="P2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1456" type="branch" />
+            <wire x2="512" y1="1456" y2="1456" x1="432" />
+            <wire x2="1664" y1="1456" y2="1456" x1="512" />
+        </branch>
+        <branch name="P3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1920" type="branch" />
+            <wire x2="512" y1="1920" y2="1920" x1="416" />
+            <wire x2="1664" y1="1920" y2="1920" x1="512" />
+            <wire x2="1664" y1="1904" y2="1920" x1="1664" />
+        </branch>
+        <text style="fontsize:24;fontname:Arial" x="2464" y="152">Q0,Q1,Q2,Q3 is Qa,Qb,Qc,Qd from TTL book</text>
+        <text style="fontsize:24;fontname:Arial" x="3008" y="2168">TC is RCO from TTL Book</text>
+        <text style="fontsize:24;fontname:Arial" x="188" y="2196">CET CEP same as ENT ENP from TTL Book</text>
+        <text style="fontsize:24;fontname:Arial" x="180" y="584">P0 is DATA_A, P1 is DATA_B ... from TTL Book</text>
+        <text style="fontsize:24;fontname:Arial" x="340" y="308">PEn is LOADn from TTL Book</text>
+        <iomarker fontsize="28" x="432" y="656" name="P0" orien="R180" />
+        <iomarker fontsize="28" x="448" y="1072" name="P1" orien="R180" />
+        <iomarker fontsize="28" x="224" y="1232" name="CLK" orien="R180" />
+        <iomarker fontsize="28" x="432" y="1456" name="P2" orien="R180" />
+        <iomarker fontsize="28" x="416" y="1920" name="P3" orien="R180" />
+        <iomarker fontsize="28" x="224" y="2272" name="CEP" orien="R180" />
+        <iomarker fontsize="28" x="224" y="2336" name="CET" orien="R180" />
+        <iomarker fontsize="28" x="3392" y="960" name="Q1" orien="R0" />
+        <iomarker fontsize="28" x="3184" y="2288" name="TC" orien="R0" />
+        <iomarker fontsize="28" x="416" y="384" name="PEn" orien="R180" />
+        <instance x="2720" y="736" name="XLXI_39" orien="R0" />
+        <instance x="2368" y="512" name="XLXI_5" orien="R0" />
+        <branch name="XLXN_15">
+            <wire x2="1936" y1="448" y2="448" x1="1920" />
+            <wire x2="2368" y1="384" y2="384" x1="1936" />
+            <wire x2="1936" y1="384" y2="448" x1="1936" />
+        </branch>
+        <branch name="XLXN_64">
+            <wire x2="2720" y1="416" y2="416" x1="2624" />
+        </branch>
+        <instance x="2368" y="640" name="XLXI_6" orien="R0" />
+        <branch name="XLXN_65">
+            <wire x2="2672" y1="544" y2="544" x1="2624" />
+            <wire x2="2672" y1="480" y2="544" x1="2672" />
+            <wire x2="2720" y1="480" y2="480" x1="2672" />
+        </branch>
+        <branch name="Q0">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3312" y="480" type="branch" />
+            <wire x2="880" y1="816" y2="960" x1="880" />
+            <wire x2="960" y1="960" y2="960" x1="880" />
+            <wire x2="880" y1="960" y2="1344" x1="880" />
+            <wire x2="960" y1="1344" y2="1344" x1="880" />
+            <wire x2="880" y1="1344" y2="1824" x1="880" />
+            <wire x2="880" y1="1824" y2="2352" x1="880" />
+            <wire x2="2768" y1="2352" y2="2352" x1="880" />
+            <wire x2="1088" y1="1824" y2="1824" x1="880" />
+            <wire x2="3184" y1="816" y2="816" x1="880" />
+            <wire x2="3184" y1="480" y2="480" x1="3104" />
+            <wire x2="3184" y1="480" y2="816" x1="3184" />
+            <wire x2="3312" y1="480" y2="480" x1="3184" />
+            <wire x2="3376" y1="480" y2="480" x1="3312" />
+        </branch>
+        <iomarker fontsize="28" x="3376" y="480" name="Q0" orien="R0" />
+        <instance x="2720" y="1216" name="XLXI_40" orien="R0" />
+        <instance x="2368" y="992" name="XLXI_7" orien="R0" />
+        <branch name="XLXN_17">
+            <wire x2="1936" y1="896" y2="896" x1="1920" />
+            <wire x2="2368" y1="864" y2="864" x1="1936" />
+            <wire x2="1936" y1="864" y2="896" x1="1936" />
+        </branch>
+        <branch name="XLXN_11">
+            <wire x2="2352" y1="1024" y2="1024" x1="2240" />
+            <wire x2="2368" y1="928" y2="928" x1="2352" />
+            <wire x2="2352" y1="928" y2="992" x1="2352" />
+            <wire x2="2368" y1="992" y2="992" x1="2352" />
+            <wire x2="2352" y1="992" y2="1024" x1="2352" />
+        </branch>
+        <instance x="2368" y="1120" name="XLXI_8" orien="R0" />
+        <branch name="XLXN_71">
+            <wire x2="2720" y1="896" y2="896" x1="2624" />
+        </branch>
+        <branch name="XLXN_72">
+            <wire x2="2672" y1="1024" y2="1024" x1="2624" />
+            <wire x2="2672" y1="960" y2="1024" x1="2672" />
+            <wire x2="2720" y1="960" y2="960" x1="2672" />
+        </branch>
+        <instance x="2720" y="1632" name="XLXI_41" orien="R0" />
+        <instance x="2384" y="1408" name="XLXI_9" orien="R0" />
+        <branch name="XLXN_19">
+            <wire x2="1936" y1="1296" y2="1296" x1="1920" />
+            <wire x2="2384" y1="1280" y2="1280" x1="1936" />
+            <wire x2="1936" y1="1280" y2="1296" x1="1936" />
+        </branch>
+        <branch name="XLXN_12">
+            <wire x2="2368" y1="1408" y2="1408" x1="2240" />
+            <wire x2="2384" y1="1408" y2="1408" x1="2368" />
+            <wire x2="2384" y1="1344" y2="1344" x1="2368" />
+            <wire x2="2368" y1="1344" y2="1408" x1="2368" />
+        </branch>
+        <instance x="2384" y="1536" name="XLXI_10" orien="R0" />
+        <branch name="XLXN_76">
+            <wire x2="2720" y1="1312" y2="1312" x1="2640" />
+        </branch>
+        <branch name="XLXN_77">
+            <wire x2="2672" y1="1440" y2="1440" x1="2640" />
+            <wire x2="2672" y1="1376" y2="1440" x1="2672" />
+            <wire x2="2720" y1="1376" y2="1376" x1="2672" />
+        </branch>
+        <iomarker fontsize="28" x="3392" y="1376" name="Q2" orien="R0" />
+        <branch name="Q2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3344" y="1376" type="branch" />
+            <wire x2="1024" y1="1632" y2="1696" x1="1024" />
+            <wire x2="1088" y1="1696" y2="1696" x1="1024" />
+            <wire x2="1024" y1="1696" y2="2224" x1="1024" />
+            <wire x2="2768" y1="2224" y2="2224" x1="1024" />
+            <wire x2="3232" y1="1632" y2="1632" x1="1024" />
+            <wire x2="3232" y1="1376" y2="1376" x1="3104" />
+            <wire x2="3232" y1="1376" y2="1632" x1="3232" />
+            <wire x2="3344" y1="1376" y2="1376" x1="3232" />
+            <wire x2="3392" y1="1376" y2="1376" x1="3344" />
+        </branch>
+        <instance x="2720" y="2048" name="XLXI_42" orien="R0" />
+        <instance x="2368" y="1952" name="XLXI_12" orien="R0" />
+        <branch name="XLXN_82">
+            <wire x2="2720" y1="1728" y2="1728" x1="2624" />
+        </branch>
+        <branch name="XLXN_83">
+            <wire x2="2672" y1="1856" y2="1856" x1="2624" />
+            <wire x2="2672" y1="1792" y2="1856" x1="2672" />
+            <wire x2="2720" y1="1792" y2="1792" x1="2672" />
+        </branch>
+        <iomarker fontsize="28" x="3392" y="1792" name="Q3" orien="R0" />
+        <branch name="XLXN_86">
+            <wire x2="2304" y1="592" y2="592" x1="2240" />
+            <wire x2="2368" y1="448" y2="448" x1="2304" />
+            <wire x2="2304" y1="448" y2="512" x1="2304" />
+            <wire x2="2304" y1="512" y2="592" x1="2304" />
+            <wire x2="2368" y1="512" y2="512" x1="2304" />
+        </branch>
+        <iomarker fontsize="28" x="368" y="2032" name="CLRn" orien="R180" />
+        <instance x="400" y="1264" name="XLXI_43" orien="R0" />
+        <branch name="XLXN_84">
+            <wire x2="2304" y1="1232" y2="1232" x1="624" />
+            <wire x2="2304" y1="1232" y2="1520" x1="2304" />
+            <wire x2="2720" y1="1520" y2="1520" x1="2304" />
+            <wire x2="2304" y1="1520" y2="1936" x1="2304" />
+            <wire x2="2544" y1="1936" y2="1936" x1="2304" />
+            <wire x2="2416" y1="752" y2="752" x1="2304" />
+            <wire x2="2304" y1="752" y2="1104" x1="2304" />
+            <wire x2="2512" y1="1104" y2="1104" x1="2304" />
+            <wire x2="2304" y1="1104" y2="1232" x1="2304" />
+            <wire x2="2416" y1="640" y2="752" x1="2416" />
+            <wire x2="2720" y1="640" y2="640" x1="2416" />
+            <wire x2="2720" y1="1088" y2="1088" x1="2512" />
+            <wire x2="2512" y1="1088" y2="1104" x1="2512" />
+            <wire x2="2720" y1="1920" y2="1920" x1="2544" />
+            <wire x2="2544" y1="1920" y2="1936" x1="2544" />
+            <wire x2="2720" y1="608" y2="640" x1="2720" />
+            <wire x2="2720" y1="1504" y2="1520" x1="2720" />
+        </branch>
+        <instance x="496" y="2064" name="XLXI_44" orien="R0" />
+        <branch name="XLXN_87">
+            <wire x2="2304" y1="2144" y2="2144" x1="2224" />
+            <wire x2="2304" y1="2016" y2="2144" x1="2304" />
+            <wire x2="2704" y1="2016" y2="2016" x1="2304" />
+            <wire x2="2720" y1="2016" y2="2016" x1="2704" />
+            <wire x2="2720" y1="704" y2="704" x1="2704" />
+            <wire x2="2704" y1="704" y2="1184" x1="2704" />
+            <wire x2="2720" y1="1184" y2="1184" x1="2704" />
+            <wire x2="2704" y1="1184" y2="1600" x1="2704" />
+            <wire x2="2720" y1="1600" y2="1600" x1="2704" />
+            <wire x2="2704" y1="1600" y2="2016" x1="2704" />
+        </branch>
+        <branch name="XLXN_44">
+            <wire x2="784" y1="2032" y2="2032" x1="720" />
+            <wire x2="1456" y1="2032" y2="2032" x1="784" />
+            <wire x2="1616" y1="2032" y2="2032" x1="1456" />
+            <wire x2="1664" y1="2032" y2="2032" x1="1616" />
+            <wire x2="1616" y1="2032" y2="2144" x1="1616" />
+            <wire x2="1936" y1="2144" y2="2144" x1="1616" />
+            <wire x2="2000" y1="2144" y2="2144" x1="1936" />
+            <wire x2="944" y1="448" y2="448" x1="784" />
+            <wire x2="784" y1="448" y2="2032" x1="784" />
+            <wire x2="1664" y1="720" y2="720" x1="1456" />
+            <wire x2="1456" y1="720" y2="1136" x1="1456" />
+            <wire x2="1664" y1="1136" y2="1136" x1="1456" />
+            <wire x2="1456" y1="1136" y2="1520" x1="1456" />
+            <wire x2="1664" y1="1520" y2="1520" x1="1456" />
+            <wire x2="1456" y1="1520" y2="2032" x1="1456" />
+        </branch>
+        <instance x="2000" y="2176" name="XLXI_45" orien="R0" />
+    </sheet>
+</drawing>
\ No newline at end of file
diff --git a/AppleIIGateSch/chip74LS161.schbak b/AppleIIGateSch/chip74LS161.schbak
new file mode 100644
index 0000000..5dc99eb
--- /dev/null
+++ b/AppleIIGateSch/chip74LS161.schbak
@@ -0,0 +1,736 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+    <attr value="spartan3e" name="DeviceFamilyName">
+        <trait delete="all:0" />
+        <trait editname="all:0" />
+        <trait edittrait="all:0" />
+    </attr>
+    <netlist>
+        <signal name="XLXN_1" />
+        <signal name="XLXN_2" />
+        <signal name="XLXN_3" />
+        <signal name="XLXN_4" />
+        <signal name="XLXN_5" />
+        <signal name="XLXN_6" />
+        <signal name="XLXN_7" />
+        <signal name="XLXN_8" />
+        <signal name="XLXN_9" />
+        <signal name="XLXN_10" />
+        <signal name="XLXN_11" />
+        <signal name="XLXN_12" />
+        <signal name="XLXN_13" />
+        <signal name="CLK" />
+        <signal name="XLXN_15" />
+        <signal name="XLXN_16" />
+        <signal name="XLXN_17" />
+        <signal name="XLXN_18" />
+        <signal name="XLXN_19" />
+        <signal name="XLXN_20" />
+        <signal name="XLXN_21" />
+        <signal name="XLXN_22" />
+        <signal name="XLXN_24" />
+        <signal name="XLXN_26" />
+        <signal name="XLXN_28" />
+        <signal name="XLXN_29" />
+        <signal name="XLXN_33" />
+        <signal name="XLXN_34" />
+        <signal name="XLXN_35" />
+        <signal name="XLXN_36" />
+        <signal name="XLXN_37" />
+        <signal name="CLRn" />
+        <signal name="Q0" />
+        <signal name="Q1" />
+        <signal name="Q2" />
+        <signal name="Q3" />
+        <signal name="LOADn" />
+        <signal name="XLXN_44" />
+        <signal name="XLXN_45" />
+        <signal name="XLXN_47" />
+        <signal name="XLXN_48" />
+        <signal name="XLXN_49" />
+        <signal name="XLXN_50" />
+        <signal name="XLXN_51" />
+        <signal name="XLXN_52" />
+        <signal name="XLXN_53" />
+        <signal name="XLXN_54" />
+        <signal name="XLXN_55" />
+        <signal name="XLXN_56" />
+        <signal name="CEP" />
+        <signal name="CET" />
+        <signal name="XLXN_59" />
+        <signal name="TC" />
+        <signal name="P0" />
+        <signal name="P1" />
+        <signal name="P2" />
+        <signal name="P3" />
+        <port polarity="Input" name="CLK" />
+        <port polarity="Input" name="CLRn" />
+        <port polarity="Output" name="Q0" />
+        <port polarity="Output" name="Q1" />
+        <port polarity="Output" name="Q2" />
+        <port polarity="Output" name="Q3" />
+        <port polarity="Input" name="LOADn" />
+        <port polarity="Input" name="CEP" />
+        <port polarity="Input" name="CET" />
+        <port polarity="Output" name="TC" />
+        <port polarity="Input" name="P0" />
+        <port polarity="Input" name="P1" />
+        <port polarity="Input" name="P2" />
+        <port polarity="Input" name="P3" />
+        <blockdef name="JK_FlipFlop">
+            <timestamp>2018-5-22T0:7:17</timestamp>
+            <rect width="256" x="64" y="-192" height="192" />
+            <line x2="0" y1="-96" y2="-96" x1="64" />
+            <line x2="0" y1="-160" y2="-160" x1="64" />
+            <line x2="0" y1="-32" y2="-32" x1="64" />
+            <line x2="384" y1="-160" y2="-160" x1="320" />
+            <line x2="384" y1="-32" y2="-32" x1="320" />
+        </blockdef>
+        <blockdef name="and2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="192" y1="-96" y2="-96" x1="256" />
+            <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+            <line x2="64" y1="-48" y2="-48" x1="144" />
+            <line x2="144" y1="-144" y2="-144" x1="64" />
+            <line x2="64" y1="-48" y2="-144" x1="64" />
+        </blockdef>
+        <blockdef name="inv">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="160" y1="-32" y2="-32" x1="224" />
+            <line x2="128" y1="-64" y2="-32" x1="64" />
+            <line x2="64" y1="-32" y2="0" x1="128" />
+            <line x2="64" y1="0" y2="-64" x1="64" />
+            <circle r="16" cx="144" cy="-32" />
+        </blockdef>
+        <blockdef name="or2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="192" y1="-96" y2="-96" x1="256" />
+            <arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
+            <arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
+            <line x2="48" y1="-144" y2="-144" x1="112" />
+            <arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
+            <line x2="48" y1="-48" y2="-48" x1="112" />
+        </blockdef>
+        <blockdef name="nand2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="216" y1="-96" y2="-96" x1="256" />
+            <circle r="12" cx="204" cy="-96" />
+            <line x2="64" y1="-48" y2="-144" x1="64" />
+            <line x2="144" y1="-144" y2="-144" x1="64" />
+            <line x2="64" y1="-48" y2="-48" x1="144" />
+            <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+        </blockdef>
+        <blockdef name="nand3">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="216" y1="-128" y2="-128" x1="256" />
+            <circle r="12" cx="204" cy="-128" />
+            <line x2="144" y1="-176" y2="-176" x1="64" />
+            <line x2="64" y1="-80" y2="-80" x1="144" />
+            <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+            <line x2="64" y1="-64" y2="-192" x1="64" />
+        </blockdef>
+        <blockdef name="or2b2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="32" y1="-64" y2="-64" x1="0" />
+            <circle r="12" cx="44" cy="-64" />
+            <line x2="32" y1="-128" y2="-128" x1="0" />
+            <circle r="12" cx="44" cy="-128" />
+            <line x2="192" y1="-96" y2="-96" x1="256" />
+            <arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
+            <line x2="48" y1="-48" y2="-48" x1="112" />
+            <arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
+            <line x2="48" y1="-144" y2="-144" x1="112" />
+            <arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
+        </blockdef>
+        <blockdef name="and3">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="192" y1="-128" y2="-128" x1="256" />
+            <line x2="144" y1="-176" y2="-176" x1="64" />
+            <line x2="64" y1="-80" y2="-80" x1="144" />
+            <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+            <line x2="64" y1="-64" y2="-192" x1="64" />
+        </blockdef>
+        <blockdef name="and4">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-112" y2="-112" x1="144" />
+            <arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
+            <line x2="144" y1="-208" y2="-208" x1="64" />
+            <line x2="64" y1="-64" y2="-256" x1="64" />
+            <line x2="192" y1="-160" y2="-160" x1="256" />
+            <line x2="64" y1="-256" y2="-256" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+        </blockdef>
+        <blockdef name="and5">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <arc ex="144" ey="-240" sx="144" sy="-144" r="48" cx="144" cy="-192" />
+            <line x2="64" y1="-144" y2="-144" x1="144" />
+            <line x2="144" y1="-240" y2="-240" x1="64" />
+            <line x2="64" y1="-64" y2="-320" x1="64" />
+            <line x2="192" y1="-192" y2="-192" x1="256" />
+            <line x2="64" y1="-320" y2="-320" x1="0" />
+            <line x2="64" y1="-256" y2="-256" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+        </blockdef>
+        <block symbolname="JK_FlipFlop" name="XLXI_1">
+            <blockpin signalname="XLXN_9" name="CLK" />
+            <blockpin signalname="XLXN_1" name="J" />
+            <blockpin signalname="XLXN_2" name="K" />
+            <blockpin signalname="Q0" name="Q" />
+            <blockpin name="Qnot" />
+        </block>
+        <block symbolname="JK_FlipFlop" name="XLXI_2">
+            <blockpin signalname="XLXN_9" name="CLK" />
+            <blockpin signalname="XLXN_3" name="J" />
+            <blockpin signalname="XLXN_4" name="K" />
+            <blockpin signalname="Q1" name="Q" />
+            <blockpin name="Qnot" />
+        </block>
+        <block symbolname="JK_FlipFlop" name="XLXI_3">
+            <blockpin signalname="XLXN_9" name="CLK" />
+            <blockpin signalname="XLXN_5" name="J" />
+            <blockpin signalname="XLXN_6" name="K" />
+            <blockpin signalname="Q2" name="Q" />
+            <blockpin name="Qnot" />
+        </block>
+        <block symbolname="JK_FlipFlop" name="XLXI_4">
+            <blockpin signalname="XLXN_9" name="CLK" />
+            <blockpin signalname="XLXN_7" name="J" />
+            <blockpin signalname="XLXN_8" name="K" />
+            <blockpin signalname="Q3" name="Q" />
+            <blockpin signalname="XLXN_55" name="Qnot" />
+        </block>
+        <block symbolname="and2" name="XLXI_5">
+            <blockpin signalname="XLXN_10" name="I0" />
+            <blockpin signalname="XLXN_15" name="I1" />
+            <blockpin signalname="XLXN_1" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_6">
+            <blockpin signalname="XLXN_35" name="I0" />
+            <blockpin signalname="XLXN_10" name="I1" />
+            <blockpin signalname="XLXN_2" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_7">
+            <blockpin signalname="XLXN_11" name="I0" />
+            <blockpin signalname="XLXN_17" name="I1" />
+            <blockpin signalname="XLXN_3" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_8">
+            <blockpin signalname="XLXN_26" name="I0" />
+            <blockpin signalname="XLXN_11" name="I1" />
+            <blockpin signalname="XLXN_4" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_9">
+            <blockpin signalname="XLXN_12" name="I0" />
+            <blockpin signalname="XLXN_19" name="I1" />
+            <blockpin signalname="XLXN_5" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_10">
+            <blockpin signalname="XLXN_28" name="I0" />
+            <blockpin signalname="XLXN_12" name="I1" />
+            <blockpin signalname="XLXN_6" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_11">
+            <blockpin signalname="XLXN_13" name="I0" />
+            <blockpin signalname="XLXN_21" name="I1" />
+            <blockpin signalname="XLXN_7" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_12">
+            <blockpin signalname="XLXN_29" name="I0" />
+            <blockpin signalname="XLXN_13" name="I1" />
+            <blockpin signalname="XLXN_8" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_13">
+            <blockpin signalname="CLK" name="I" />
+            <blockpin signalname="XLXN_9" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_14">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_45" name="I1" />
+            <blockpin signalname="XLXN_11" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_15">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_48" name="I1" />
+            <blockpin signalname="XLXN_12" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_16">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_50" name="I1" />
+            <blockpin signalname="XLXN_13" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_17">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_54" name="I1" />
+            <blockpin signalname="XLXN_10" name="O" />
+        </block>
+        <block symbolname="nand2" name="XLXI_18">
+            <blockpin signalname="XLXN_35" name="I0" />
+            <blockpin signalname="XLXN_36" name="I1" />
+            <blockpin signalname="XLXN_15" name="O" />
+        </block>
+        <block symbolname="nand2" name="XLXI_20">
+            <blockpin signalname="XLXN_26" name="I0" />
+            <blockpin signalname="XLXN_36" name="I1" />
+            <blockpin signalname="XLXN_17" name="O" />
+        </block>
+        <block symbolname="nand2" name="XLXI_24">
+            <blockpin signalname="XLXN_28" name="I0" />
+            <blockpin signalname="XLXN_36" name="I1" />
+            <blockpin signalname="XLXN_19" name="O" />
+        </block>
+        <block symbolname="nand2" name="XLXI_26">
+            <blockpin signalname="XLXN_29" name="I0" />
+            <blockpin signalname="XLXN_36" name="I1" />
+            <blockpin signalname="XLXN_21" name="O" />
+        </block>
+        <block symbolname="nand3" name="XLXI_28">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_44" name="I1" />
+            <blockpin signalname="P0" name="I2" />
+            <blockpin signalname="XLXN_35" name="O" />
+        </block>
+        <block symbolname="nand3" name="XLXI_29">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_44" name="I1" />
+            <blockpin signalname="P1" name="I2" />
+            <blockpin signalname="XLXN_26" name="O" />
+        </block>
+        <block symbolname="nand3" name="XLXI_30">
+            <blockpin signalname="XLXN_36" name="I0" />
+            <blockpin signalname="XLXN_44" name="I1" />
+            <blockpin signalname="P2" name="I2" />
+            <blockpin signalname="XLXN_28" name="O" />
+        </block>
+        <block symbolname="nand3" name="XLXI_31">
+            <blockpin signalname="XLXN_44" name="I0" />
+            <blockpin signalname="XLXN_36" name="I1" />
+            <blockpin signalname="P3" name="I2" />
+            <blockpin signalname="XLXN_29" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_32">
+            <blockpin signalname="CLRn" name="I" />
+            <blockpin signalname="XLXN_44" name="O" />
+        </block>
+        <block symbolname="or2b2" name="XLXI_33">
+            <blockpin signalname="XLXN_44" name="I0" />
+            <blockpin signalname="LOADn" name="I1" />
+            <blockpin signalname="XLXN_36" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_34">
+            <blockpin signalname="XLXN_54" name="I0" />
+            <blockpin signalname="Q0" name="I1" />
+            <blockpin signalname="XLXN_45" name="O" />
+        </block>
+        <block symbolname="and3" name="XLXI_35">
+            <blockpin signalname="XLXN_54" name="I0" />
+            <blockpin signalname="Q0" name="I1" />
+            <blockpin signalname="Q1" name="I2" />
+            <blockpin signalname="XLXN_48" name="O" />
+        </block>
+        <block symbolname="and4" name="XLXI_36">
+            <blockpin signalname="XLXN_54" name="I0" />
+            <blockpin signalname="Q0" name="I1" />
+            <blockpin signalname="Q1" name="I2" />
+            <blockpin signalname="Q2" name="I3" />
+            <blockpin signalname="XLXN_50" name="O" />
+        </block>
+        <block symbolname="and5" name="XLXI_37">
+            <blockpin signalname="CET" name="I0" />
+            <blockpin signalname="Q0" name="I1" />
+            <blockpin signalname="Q1" name="I2" />
+            <blockpin signalname="Q2" name="I3" />
+            <blockpin signalname="XLXN_55" name="I4" />
+            <blockpin signalname="TC" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_38">
+            <blockpin signalname="CET" name="I0" />
+            <blockpin signalname="CEP" name="I1" />
+            <blockpin signalname="XLXN_54" name="O" />
+        </block>
+    </netlist>
+    <sheet sheetnum="1" width="3520" height="2720">
+        <instance x="2688" y="704" name="XLXI_1" orien="R0">
+        </instance>
+        <instance x="2688" y="1120" name="XLXI_2" orien="R0">
+        </instance>
+        <instance x="2688" y="1504" name="XLXI_3" orien="R0">
+        </instance>
+        <instance x="2688" y="1904" name="XLXI_4" orien="R0">
+        </instance>
+        <branch name="XLXN_1">
+            <wire x2="2672" y1="528" y2="528" x1="2624" />
+            <wire x2="2672" y1="528" y2="544" x1="2672" />
+            <wire x2="2688" y1="544" y2="544" x1="2672" />
+        </branch>
+        <branch name="XLXN_2">
+            <wire x2="2672" y1="688" y2="688" x1="2624" />
+            <wire x2="2688" y1="672" y2="672" x1="2672" />
+            <wire x2="2672" y1="672" y2="688" x1="2672" />
+        </branch>
+        <branch name="XLXN_3">
+            <wire x2="2672" y1="944" y2="944" x1="2624" />
+            <wire x2="2672" y1="944" y2="960" x1="2672" />
+            <wire x2="2688" y1="960" y2="960" x1="2672" />
+        </branch>
+        <branch name="XLXN_4">
+            <wire x2="2672" y1="1104" y2="1104" x1="2624" />
+            <wire x2="2688" y1="1088" y2="1088" x1="2672" />
+            <wire x2="2672" y1="1088" y2="1104" x1="2672" />
+        </branch>
+        <branch name="XLXN_5">
+            <wire x2="2672" y1="1328" y2="1328" x1="2624" />
+            <wire x2="2672" y1="1328" y2="1344" x1="2672" />
+            <wire x2="2688" y1="1344" y2="1344" x1="2672" />
+        </branch>
+        <branch name="XLXN_6">
+            <wire x2="2672" y1="1488" y2="1488" x1="2624" />
+            <wire x2="2688" y1="1472" y2="1472" x1="2672" />
+            <wire x2="2672" y1="1472" y2="1488" x1="2672" />
+        </branch>
+        <branch name="XLXN_7">
+            <wire x2="2672" y1="1728" y2="1728" x1="2624" />
+            <wire x2="2672" y1="1728" y2="1744" x1="2672" />
+            <wire x2="2688" y1="1744" y2="1744" x1="2672" />
+        </branch>
+        <branch name="XLXN_8">
+            <wire x2="2672" y1="1888" y2="1888" x1="2624" />
+            <wire x2="2688" y1="1872" y2="1872" x1="2672" />
+            <wire x2="2672" y1="1872" y2="1888" x1="2672" />
+        </branch>
+        <branch name="XLXN_9">
+            <wire x2="2304" y1="1232" y2="1232" x1="656" />
+            <wire x2="2304" y1="1232" y2="1408" x1="2304" />
+            <wire x2="2304" y1="1408" y2="1808" x1="2304" />
+            <wire x2="2688" y1="1808" y2="1808" x1="2304" />
+            <wire x2="2688" y1="1408" y2="1408" x1="2304" />
+            <wire x2="2688" y1="608" y2="608" x1="2304" />
+            <wire x2="2304" y1="608" y2="1024" x1="2304" />
+            <wire x2="2688" y1="1024" y2="1024" x1="2304" />
+            <wire x2="2304" y1="1024" y2="1232" x1="2304" />
+        </branch>
+        <instance x="2368" y="624" name="XLXI_5" orien="R0" />
+        <instance x="2368" y="784" name="XLXI_6" orien="R0" />
+        <instance x="2368" y="1040" name="XLXI_7" orien="R0" />
+        <instance x="2368" y="1200" name="XLXI_8" orien="R0" />
+        <instance x="2368" y="1424" name="XLXI_9" orien="R0" />
+        <instance x="2368" y="1584" name="XLXI_10" orien="R0" />
+        <instance x="2368" y="1824" name="XLXI_11" orien="R0" />
+        <instance x="2368" y="1984" name="XLXI_12" orien="R0" />
+        <branch name="XLXN_11">
+            <wire x2="2272" y1="1024" y2="1024" x1="2240" />
+            <wire x2="2272" y1="1024" y2="1072" x1="2272" />
+            <wire x2="2368" y1="1072" y2="1072" x1="2272" />
+            <wire x2="2368" y1="976" y2="976" x1="2272" />
+            <wire x2="2272" y1="976" y2="1024" x1="2272" />
+        </branch>
+        <branch name="CLK">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="320" y="1232" type="branch" />
+            <wire x2="320" y1="1232" y2="1232" x1="224" />
+            <wire x2="432" y1="1232" y2="1232" x1="320" />
+        </branch>
+        <instance x="1984" y="1120" name="XLXI_14" orien="R0" />
+        <branch name="XLXN_15">
+            <wire x2="2352" y1="448" y2="448" x1="1920" />
+            <wire x2="2352" y1="448" y2="496" x1="2352" />
+            <wire x2="2368" y1="496" y2="496" x1="2352" />
+        </branch>
+        <branch name="XLXN_17">
+            <wire x2="2352" y1="896" y2="896" x1="1920" />
+            <wire x2="2352" y1="896" y2="912" x1="2352" />
+            <wire x2="2368" y1="912" y2="912" x1="2352" />
+        </branch>
+        <branch name="XLXN_19">
+            <wire x2="2368" y1="1296" y2="1296" x1="1920" />
+        </branch>
+        <branch name="XLXN_21">
+            <wire x2="2368" y1="1696" y2="1696" x1="1920" />
+        </branch>
+        <instance x="1664" y="1264" name="XLXI_29" orien="R0" />
+        <instance x="1664" y="1392" name="XLXI_24" orien="R0" />
+        <instance x="1664" y="1648" name="XLXI_30" orien="R0" />
+        <instance x="1664" y="1792" name="XLXI_26" orien="R0" />
+        <instance x="1664" y="992" name="XLXI_20" orien="R0" />
+        <branch name="XLXN_26">
+            <wire x2="1664" y1="928" y2="928" x1="1648" />
+            <wire x2="1648" y1="928" y2="960" x1="1648" />
+            <wire x2="1936" y1="960" y2="960" x1="1648" />
+            <wire x2="1936" y1="960" y2="1136" x1="1936" />
+            <wire x2="2368" y1="1136" y2="1136" x1="1936" />
+            <wire x2="1936" y1="1136" y2="1136" x1="1920" />
+        </branch>
+        <branch name="XLXN_12">
+            <wire x2="2272" y1="1408" y2="1408" x1="2240" />
+            <wire x2="2272" y1="1408" y2="1456" x1="2272" />
+            <wire x2="2368" y1="1456" y2="1456" x1="2272" />
+            <wire x2="2368" y1="1360" y2="1360" x1="2272" />
+            <wire x2="2272" y1="1360" y2="1408" x1="2272" />
+        </branch>
+        <branch name="XLXN_28">
+            <wire x2="1664" y1="1328" y2="1328" x1="1648" />
+            <wire x2="1648" y1="1328" y2="1360" x1="1648" />
+            <wire x2="1936" y1="1360" y2="1360" x1="1648" />
+            <wire x2="1936" y1="1360" y2="1520" x1="1936" />
+            <wire x2="2368" y1="1520" y2="1520" x1="1936" />
+            <wire x2="1936" y1="1520" y2="1520" x1="1920" />
+        </branch>
+        <branch name="XLXN_29">
+            <wire x2="1664" y1="1728" y2="1728" x1="1648" />
+            <wire x2="1648" y1="1728" y2="1760" x1="1648" />
+            <wire x2="1936" y1="1760" y2="1760" x1="1648" />
+            <wire x2="1936" y1="1760" y2="1936" x1="1936" />
+            <wire x2="2352" y1="1936" y2="1936" x1="1936" />
+            <wire x2="1936" y1="1936" y2="1968" x1="1936" />
+            <wire x2="1936" y1="1968" y2="1968" x1="1920" />
+            <wire x2="2368" y1="1920" y2="1920" x1="2352" />
+            <wire x2="2352" y1="1920" y2="1936" x1="2352" />
+        </branch>
+        <instance x="1664" y="2096" name="XLXI_31" orien="R0" />
+        <instance x="1984" y="1920" name="XLXI_16" orien="R0" />
+        <branch name="XLXN_13">
+            <wire x2="2256" y1="1824" y2="1824" x1="2240" />
+            <wire x2="2256" y1="1808" y2="1824" x1="2256" />
+            <wire x2="2272" y1="1808" y2="1808" x1="2256" />
+            <wire x2="2272" y1="1808" y2="1856" x1="2272" />
+            <wire x2="2368" y1="1856" y2="1856" x1="2272" />
+            <wire x2="2368" y1="1760" y2="1760" x1="2272" />
+            <wire x2="2272" y1="1760" y2="1808" x1="2272" />
+        </branch>
+        <instance x="1664" y="544" name="XLXI_18" orien="R0" />
+        <instance x="1984" y="688" name="XLXI_17" orien="R0" />
+        <branch name="XLXN_10">
+            <wire x2="2256" y1="592" y2="592" x1="2240" />
+            <wire x2="2256" y1="592" y2="608" x1="2256" />
+            <wire x2="2272" y1="608" y2="608" x1="2256" />
+            <wire x2="2272" y1="608" y2="656" x1="2272" />
+            <wire x2="2368" y1="656" y2="656" x1="2272" />
+            <wire x2="2368" y1="560" y2="560" x1="2272" />
+            <wire x2="2272" y1="560" y2="608" x1="2272" />
+        </branch>
+        <instance x="1664" y="848" name="XLXI_28" orien="R0" />
+        <branch name="XLXN_35">
+            <wire x2="1664" y1="480" y2="480" x1="1648" />
+            <wire x2="1648" y1="480" y2="512" x1="1648" />
+            <wire x2="1952" y1="512" y2="512" x1="1648" />
+            <wire x2="1952" y1="512" y2="720" x1="1952" />
+            <wire x2="2368" y1="720" y2="720" x1="1952" />
+            <wire x2="1952" y1="720" y2="720" x1="1920" />
+        </branch>
+        <branch name="XLXN_36">
+            <wire x2="1552" y1="416" y2="416" x1="1200" />
+            <wire x2="1664" y1="416" y2="416" x1="1552" />
+            <wire x2="1552" y1="416" y2="624" x1="1552" />
+            <wire x2="1984" y1="624" y2="624" x1="1552" />
+            <wire x2="1552" y1="624" y2="784" x1="1552" />
+            <wire x2="1664" y1="784" y2="784" x1="1552" />
+            <wire x2="1552" y1="784" y2="864" x1="1552" />
+            <wire x2="1664" y1="864" y2="864" x1="1552" />
+            <wire x2="1552" y1="864" y2="1056" x1="1552" />
+            <wire x2="1552" y1="1056" y2="1200" x1="1552" />
+            <wire x2="1664" y1="1200" y2="1200" x1="1552" />
+            <wire x2="1552" y1="1200" y2="1264" x1="1552" />
+            <wire x2="1664" y1="1264" y2="1264" x1="1552" />
+            <wire x2="1552" y1="1264" y2="1440" x1="1552" />
+            <wire x2="1552" y1="1440" y2="1584" x1="1552" />
+            <wire x2="1664" y1="1584" y2="1584" x1="1552" />
+            <wire x2="1552" y1="1584" y2="1664" x1="1552" />
+            <wire x2="1664" y1="1664" y2="1664" x1="1552" />
+            <wire x2="1552" y1="1664" y2="1856" x1="1552" />
+            <wire x2="1552" y1="1856" y2="1968" x1="1552" />
+            <wire x2="1552" y1="1968" y2="1984" x1="1552" />
+            <wire x2="1664" y1="1968" y2="1968" x1="1552" />
+            <wire x2="1984" y1="1856" y2="1856" x1="1552" />
+            <wire x2="1984" y1="1440" y2="1440" x1="1552" />
+            <wire x2="1984" y1="1056" y2="1056" x1="1552" />
+        </branch>
+        <instance x="1984" y="1504" name="XLXI_15" orien="R0" />
+        <instance x="512" y="2096" name="XLXI_32" orien="R0" />
+        <branch name="CLRn">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="432" y="2064" type="branch" />
+            <wire x2="432" y1="2064" y2="2064" x1="352" />
+            <wire x2="512" y1="2064" y2="2064" x1="432" />
+        </branch>
+        <branch name="Q0">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3296" y="544" type="branch" />
+            <wire x2="896" y1="832" y2="960" x1="896" />
+            <wire x2="960" y1="960" y2="960" x1="896" />
+            <wire x2="896" y1="960" y2="1344" x1="896" />
+            <wire x2="896" y1="1344" y2="1824" x1="896" />
+            <wire x2="896" y1="1824" y2="2352" x1="896" />
+            <wire x2="2768" y1="2352" y2="2352" x1="896" />
+            <wire x2="1088" y1="1824" y2="1824" x1="896" />
+            <wire x2="960" y1="1344" y2="1344" x1="896" />
+            <wire x2="3216" y1="832" y2="832" x1="896" />
+            <wire x2="3216" y1="544" y2="544" x1="3072" />
+            <wire x2="3216" y1="544" y2="832" x1="3216" />
+            <wire x2="3296" y1="544" y2="544" x1="3216" />
+            <wire x2="3312" y1="544" y2="544" x1="3296" />
+            <wire x2="3376" y1="544" y2="544" x1="3312" />
+        </branch>
+        <branch name="Q1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3328" y="960" type="branch" />
+            <wire x2="3216" y1="1216" y2="1216" x1="928" />
+            <wire x2="928" y1="1216" y2="1280" x1="928" />
+            <wire x2="928" y1="1280" y2="1760" x1="928" />
+            <wire x2="928" y1="1760" y2="2288" x1="928" />
+            <wire x2="2768" y1="2288" y2="2288" x1="928" />
+            <wire x2="1088" y1="1760" y2="1760" x1="928" />
+            <wire x2="960" y1="1280" y2="1280" x1="928" />
+            <wire x2="3216" y1="960" y2="960" x1="3072" />
+            <wire x2="3312" y1="960" y2="960" x1="3216" />
+            <wire x2="3328" y1="960" y2="960" x1="3312" />
+            <wire x2="3392" y1="960" y2="960" x1="3328" />
+            <wire x2="3216" y1="960" y2="1216" x1="3216" />
+        </branch>
+        <branch name="Q2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3344" y="1344" type="branch" />
+            <wire x2="1024" y1="1600" y2="1696" x1="1024" />
+            <wire x2="1088" y1="1696" y2="1696" x1="1024" />
+            <wire x2="1024" y1="1696" y2="2224" x1="1024" />
+            <wire x2="2768" y1="2224" y2="2224" x1="1024" />
+            <wire x2="3232" y1="1600" y2="1600" x1="1024" />
+            <wire x2="3232" y1="1344" y2="1344" x1="3072" />
+            <wire x2="3312" y1="1344" y2="1344" x1="3232" />
+            <wire x2="3344" y1="1344" y2="1344" x1="3312" />
+            <wire x2="3392" y1="1344" y2="1344" x1="3344" />
+            <wire x2="3232" y1="1344" y2="1600" x1="3232" />
+        </branch>
+        <branch name="Q3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3328" y="1744" type="branch" />
+            <wire x2="3312" y1="1744" y2="1744" x1="3072" />
+            <wire x2="3328" y1="1744" y2="1744" x1="3312" />
+            <wire x2="3392" y1="1744" y2="1744" x1="3328" />
+        </branch>
+        <instance x="944" y="512" name="XLXI_33" orien="R0" />
+        <branch name="LOADn">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="496" y="384" type="branch" />
+            <wire x2="496" y1="384" y2="384" x1="416" />
+            <wire x2="944" y1="384" y2="384" x1="496" />
+        </branch>
+        <branch name="XLXN_44">
+            <wire x2="784" y1="2064" y2="2064" x1="736" />
+            <wire x2="1456" y1="2064" y2="2064" x1="784" />
+            <wire x2="784" y1="448" y2="2064" x1="784" />
+            <wire x2="944" y1="448" y2="448" x1="784" />
+            <wire x2="1664" y1="720" y2="720" x1="1456" />
+            <wire x2="1456" y1="720" y2="1136" x1="1456" />
+            <wire x2="1456" y1="1136" y2="1520" x1="1456" />
+            <wire x2="1456" y1="1520" y2="2032" x1="1456" />
+            <wire x2="1456" y1="2032" y2="2064" x1="1456" />
+            <wire x2="1664" y1="2032" y2="2032" x1="1456" />
+            <wire x2="1664" y1="1520" y2="1520" x1="1456" />
+            <wire x2="1664" y1="1136" y2="1136" x1="1456" />
+        </branch>
+        <instance x="960" y="1088" name="XLXI_34" orien="R0" />
+        <branch name="XLXN_45">
+            <wire x2="1984" y1="992" y2="992" x1="1216" />
+        </branch>
+        <branch name="XLXN_50">
+            <wire x2="1984" y1="1792" y2="1792" x1="1344" />
+        </branch>
+        <instance x="1088" y="1952" name="XLXI_36" orien="R0" />
+        <instance x="432" y="1264" name="XLXI_13" orien="R0" />
+        <instance x="2768" y="2480" name="XLXI_37" orien="R0" />
+        <branch name="XLXN_55">
+            <wire x2="2768" y1="2080" y2="2160" x1="2768" />
+            <wire x2="3152" y1="2080" y2="2080" x1="2768" />
+            <wire x2="3152" y1="1872" y2="1872" x1="3072" />
+            <wire x2="3152" y1="1872" y2="2080" x1="3152" />
+        </branch>
+        <instance x="480" y="2400" name="XLXI_38" orien="R0" />
+        <branch name="CEP">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="304" y="2272" type="branch" />
+            <wire x2="304" y1="2272" y2="2272" x1="224" />
+            <wire x2="480" y1="2272" y2="2272" x1="304" />
+        </branch>
+        <branch name="CET">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="304" y="2336" type="branch" />
+            <wire x2="304" y1="2336" y2="2336" x1="224" />
+            <wire x2="464" y1="2336" y2="2336" x1="304" />
+            <wire x2="480" y1="2336" y2="2336" x1="464" />
+            <wire x2="464" y1="2336" y2="2416" x1="464" />
+            <wire x2="2768" y1="2416" y2="2416" x1="464" />
+        </branch>
+        <branch name="TC">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="2288" type="branch" />
+            <wire x2="3104" y1="2288" y2="2288" x1="3024" />
+            <wire x2="3184" y1="2288" y2="2288" x1="3104" />
+        </branch>
+        <branch name="P0">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="496" y="656" type="branch" />
+            <wire x2="496" y1="656" y2="656" x1="432" />
+            <wire x2="512" y1="656" y2="656" x1="496" />
+            <wire x2="1664" y1="656" y2="656" x1="512" />
+        </branch>
+        <branch name="P1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1072" type="branch" />
+            <wire x2="512" y1="1072" y2="1072" x1="448" />
+            <wire x2="528" y1="1072" y2="1072" x1="512" />
+            <wire x2="1664" y1="1072" y2="1072" x1="528" />
+        </branch>
+        <instance x="960" y="1472" name="XLXI_35" orien="R0" />
+        <branch name="XLXN_54">
+            <wire x2="848" y1="2304" y2="2304" x1="736" />
+            <wire x2="1984" y1="560" y2="560" x1="848" />
+            <wire x2="848" y1="560" y2="1024" x1="848" />
+            <wire x2="960" y1="1024" y2="1024" x1="848" />
+            <wire x2="848" y1="1024" y2="1408" x1="848" />
+            <wire x2="960" y1="1408" y2="1408" x1="848" />
+            <wire x2="848" y1="1408" y2="1888" x1="848" />
+            <wire x2="1088" y1="1888" y2="1888" x1="848" />
+            <wire x2="848" y1="1888" y2="2304" x1="848" />
+        </branch>
+        <branch name="XLXN_48">
+            <wire x2="1584" y1="1344" y2="1344" x1="1216" />
+            <wire x2="1584" y1="1344" y2="1376" x1="1584" />
+            <wire x2="1984" y1="1376" y2="1376" x1="1584" />
+        </branch>
+        <branch name="P2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1456" type="branch" />
+            <wire x2="512" y1="1456" y2="1456" x1="432" />
+            <wire x2="1664" y1="1456" y2="1456" x1="512" />
+        </branch>
+        <branch name="P3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1920" type="branch" />
+            <wire x2="496" y1="1920" y2="1920" x1="416" />
+            <wire x2="512" y1="1920" y2="1920" x1="496" />
+            <wire x2="1664" y1="1920" y2="1920" x1="512" />
+            <wire x2="1664" y1="1904" y2="1920" x1="1664" />
+        </branch>
+        <text style="fontsize:24;fontname:Arial" x="2464" y="152">Q0,Q1,Q2,Q3 is Qa,Qb,Qc,Qd from TTL book</text>
+        <text style="fontsize:24;fontname:Arial" x="3008" y="2168">TC is RCO from TTL Book</text>
+        <text style="fontsize:24;fontname:Arial" x="188" y="2196">CET CEP same as ENT ENP from TTL Book</text>
+        <text style="fontsize:24;fontname:Arial" x="180" y="584">P0 is DATA_A, P1 is DATA_B ... from TTL Book</text>
+        <text style="fontsize:24;fontname:Arial" x="340" y="308">PEn is LOADn from TTL Book</text>
+        <iomarker fontsize="28" x="416" y="384" name="LOADn" orien="R180" />
+        <iomarker fontsize="28" x="432" y="656" name="P0" orien="R180" />
+        <iomarker fontsize="28" x="448" y="1072" name="P1" orien="R180" />
+        <iomarker fontsize="28" x="224" y="1232" name="CLK" orien="R180" />
+        <iomarker fontsize="28" x="432" y="1456" name="P2" orien="R180" />
+        <iomarker fontsize="28" x="416" y="1920" name="P3" orien="R180" />
+        <iomarker fontsize="28" x="352" y="2064" name="CLRn" orien="R180" />
+        <iomarker fontsize="28" x="224" y="2272" name="CEP" orien="R180" />
+        <iomarker fontsize="28" x="224" y="2336" name="CET" orien="R180" />
+        <iomarker fontsize="28" x="3376" y="544" name="Q0" orien="R0" />
+        <iomarker fontsize="28" x="3392" y="960" name="Q1" orien="R0" />
+        <iomarker fontsize="28" x="3392" y="1344" name="Q2" orien="R0" />
+        <iomarker fontsize="28" x="3392" y="1744" name="Q3" orien="R0" />
+        <iomarker fontsize="28" x="3184" y="2288" name="TC" orien="R0" />
+    </sheet>
+</drawing>
\ No newline at end of file
diff --git a/AppleIIGateSch/chip74LS161.schcmd b/AppleIIGateSch/chip74LS161.schcmd
new file mode 100644
index 0000000..0092512
--- /dev/null
+++ b/AppleIIGateSch/chip74LS161.schcmd
@@ -0,0 +1,10 @@
+select figure at 134 1564 8 -branches -sn=1
+select figure at 501 353 8 -branches -sn=1
+delete selection -sn=1
+name branch at 496 384 8 PEn -sn=1
+name branch at 512 384 8 PEn -sn=1
+select figure at 375 383 8 -branches -sn=1
+delete selection -sn=1
+select figure at 379 386 8 -branches -sn=1
+move bawin at 416 384 to 496 384 -sn=1
+add iomarker 416 384 0 Input Unknown -sn=1
diff --git a/AppleIIGateSch/chip74LS161.sym b/AppleIIGateSch/chip74LS161.sym
new file mode 100644
index 0000000..ed64f9d
--- /dev/null
+++ b/AppleIIGateSch/chip74LS161.sym
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="chip74LS161">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2018-5-24T4:39:40</timestamp>
+    <pin polarity="Input" x="384" y="-32" name="CEP" />
+    <pin polarity="Input" x="0" y="-32" name="CET" />
+    <pin polarity="Input" x="384" y="-96" name="CLK" />
+    <pin polarity="Input" x="0" y="-96" name="CLRn" />
+    <pin polarity="Input" x="384" y="-224" name="P0" />
+    <pin polarity="Input" x="384" y="-288" name="P1" />
+    <pin polarity="Input" x="384" y="-352" name="P2" />
+    <pin polarity="Input" x="384" y="-416" name="P3" />
+    <pin polarity="Input" x="384" y="-160" name="PEn" />
+    <pin polarity="Output" x="0" y="-224" name="Q0" />
+    <pin polarity="Output" x="0" y="-288" name="Q1" />
+    <pin polarity="Output" x="0" y="-352" name="Q2" />
+    <pin polarity="Output" x="0" y="-416" name="Q3" />
+    <pin polarity="Output" x="0" y="-480" name="TC" />
+    <graph>
+        <rect width="256" x="64" y="-512" height="512" />
+        <line x2="384" y1="-32" y2="-32" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin CEP" />
+        <line x2="0" y1="-32" y2="-32" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin CET" />
+        <line x2="384" y1="-96" y2="-96" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin CLK" />
+        <line x2="0" y1="-96" y2="-96" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin CLRn" />
+        <line x2="384" y1="-224" y2="-224" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin P0" />
+        <line x2="384" y1="-288" y2="-288" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin P1" />
+        <line x2="384" y1="-352" y2="-352" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-352" type="pin P2" />
+        <line x2="384" y1="-416" y2="-416" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin P3" />
+        <line x2="384" y1="-160" y2="-160" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin PEn" />
+        <line x2="0" y1="-224" y2="-224" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin Q0" />
+        <line x2="0" y1="-288" y2="-288" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin Q1" />
+        <line x2="0" y1="-352" y2="-352" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin Q2" />
+        <line x2="0" y1="-416" y2="-416" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin Q3" />
+        <attrtext style="alignment:BCENTER;fontsize:40;fontname:Arial" attrname="SymbolName" x="196" y="-428" type="symbol" />
+        <line x2="0" y1="-480" y2="-480" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-480" type="pin TC" />
+    </graph>
+</symbol>
diff --git a/AppleIIGateSch/chip74LS161_guide.ncd b/AppleIIGateSch/chip74LS161_guide.ncd
new file mode 100644
index 0000000..57eda3e
--- /dev/null
+++ b/AppleIIGateSch/chip74LS161_guide.ncd
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
+###6620:XlxV32DM    3fff    19c4eNqtWVtvG8eS/itCoIdcYKmvMz3TMBCKpGnClEiTlCPvgwdzTbQbSz62z9kTSMpv3+p7z3BoJQdrQ2RXdXV1Xb6q7hmeYkIeMJKn2/Zft19u7+/yE3zGTk6JfMHgr6bw9zGTL27vvn75+sfvbRqNT26/tCcvPp38u6ZfOELti+5XStALdgJLTsrPbXny4vbzyX3XgZD9rk8wQicv7k/q324/pWy1wwkuPpafzu7qJuad3f3apz/V3QnYcvsZPu5/h49Pn8G8rxxG/3sysOj+95Pfbn/97eTF1xP8/Eb14UatPL+4frW4vL4pbsh7jIQ8X24mM4yoHwk3wiQ1IyJgoOewGxA3YG7A3SBxg9QNMjsAlh04PZg18ny3Wk7nxU3C3mPRJ7MeSVCfxBHJ+7PJ+57mpK8qBWEq8Zn6QPBBz7D6IEROMPypbwp/jMuL1Xr6JjVfNxAueXG52BaT/X67vLjez3eSZAes7et1sd9OrnbL+dW+eL2cbyfb6ev3L2UnbejPF9PVG/iGXWNOAcSr+Vbtcr1czYr9ZLuY79ViIi9uannR/v7lBJ1RSP0aM03mLplOozhkW7WdmQEjXxXLK/hsIgbkws2vL4r19R6YdWDAtJXWIVwVrzDu0xx26/qsVzf9NQtwbDqZFe+W81+Kd/Ptbrm+onI63wj1USg7FLlX5F6TRE7fAGv1JpPWj8WmDUONZJwMGGc2FF3EX2pJFDjFp7L+nwKCOF1t7zL9qXfUMnZsZQ5ZkPPp+vJyud/PZ6mcbucTGDRyev/xk8+PJV0iSksqJZkbry9qOzQRwnKGJTj9CkD4CkD4CkD4CmCsg1vcrG6WBU2xXBC5AIkFSCxAYgESi9X6YrIqVuvFcgqZWRK5RKVUm53rVAszVqUsl1cws744N0lO9RgmAOzLHcT9cn55Md8WGvHFxfJqtrxanEdd5Hy5i0Bd7F5PNvOIRoRJJeHrodioTO/2qhY22/Wm2MHElUqGErMbFPv3mznu5DO6weu+hFrWaN7VejY3WozMdg6Qn19BuSu4JXK1nszmM5zJ1fUeuVgqoJ85dNZqCvswox6pJKFaLyebYno5Wy2v5sV6swcA70rNvFzPrldgihrvl5fz3X5yuak06ZF+WX5K5dV8/8t6+wbLNZFr0Ah6S7k5IwhT6K6Qzg30yA2y8N9An9xgR0DP3RBHUCCoJhK5mUzfzGdUqo6qPrdDIzGXm9nOJnVxNXNxh3iM8lX4lCY/t1lNpvNLyGEXMa93k8W8p/rddDqqOuJr1cM1amvoorjS/NkasGLKqri+ut7NZ8VmebUzW0MAiy1EDVTVnqESXxpqMSuWMyO6mV266AMqNGd5VUx2u+XiqoDUWDMUc34DAAWAGAgZxbpPxUF5N59q63GYVtvt3l9N4yWxs24Jj6aNRYVCsI1xj7+FLriZ3wn1YXoSk5s3xWyuzb5aXBa79fV2Ou8UF0gPt1ZuPt9/vVcdhZ4tzqCXvCXyLcDpLSrWoKd1A9vYYBLg9Ra7STyYBLi9JW6SDCYBfm+pm6TxZCZ97VG53VxiuSNyBxcNU2jn0P/cCIchCUMahqz2Q667qKNe3Xh9Cy++CPoWQd8i6FuwSrrT6XyCY4LEBI2JsGYRr1nEaxbxGiDgfrnbMth3+wimwnG7NB0xVyOUK97O3Bny3Xa1/iVfTfbT18V6C6cmzOYKUmZ6ooaPj4CB3eNsuZtcrOZmAlY9PhK5n6bwZxOx90WlYNxp2uJG45oNOVDCcN8glv1O3Y5UL4Gy7vq87b7pMS6hP0b0bjOH5mpYqpyWlxuIxXJvtOx7dbh3gNcGrJYXO6iC/W/tCWDl5DvTb7MCfXfAZajAI1xckBEuKeh3WAJibmavTUx2Qo/B+6nh6uPFcpUtlR45Qxt5s4QWevPiZnYBhzo+2e2vzWCymy6XqdT7qJuxGWR2QJEbYDegbsDcgLtB4gaitIPsXF3F3FiJFJQMGAyA7gNlFzIUFsK4v9Ax/EIVS7cQRwvxcCEeLoRwu4UkWkiGC8lwIWREO3tVkMQNhBtkdmAjA4OkdQPbVwY0sYKMt24wmBBuQvQnOGrdYDDB3ASzE0TevE3kTVMVywbg0XwsLm7vmtu7XwHriros//v+87v2s3q6dKzbu8CS75lUT4uVjG5QANaDJ7dfP6ay/tj8fnvXcqmfNZlUD3pUwmMflfCASeWn8nMmv8Dn1/KOtkK6Z1MI+eNsu3w3V33hYn2TYwJ3S0es3k0v1zvC4Y45/wU+VNuA4+jxUOLxkYKmx9nL77//c4J/VJ/kx+8n9KcJ++GHn75XxJ8T+qOiNI0VTX7SzD8N9xFu41qDmjSrjfwjHJrxxIQCr/asCflBtThNwt4/acV/aqE2cP9UYmYD9Ejh+/Hp558/EUjfzz//G6M2f5WnOX7YsTZP0zytc0xp21KaQzgxeoAMlTmW8FXliTyFB928aeXTjjUj4nBqJV2OMc9Rjw89HeQP+AQf4adH+OIIP5ON8gSYOTnmiTytq7yu5SkFMYj4XcpzXsETeCcqeZoyzTxNE1goTzPYBXXyX3vBQaf6T9rjihuSwwX+bSYgjk9vs0R9nWY0Jxx2a9Tcad0Z/XWbq8f401q5gWEpUsHNWmtKhuQfWZkroP6RZfp7ldI8eTiFJ6oc1MFOFJSCdY08VTYDBfsBDE6F/np6DV3hvxrY/IF1YGD+9Fp0ciXSnBolJTgJkgR2ha2fKhU4nMNfmpP04R+ikf8QmXwNfeCWUQjp6wbLf2Y8J0jK27Q54HRDjsAHnKGe+xIfcNgBJz3glENOLYZ7ZdWQw7Ihh7YHMmjAqfQqov4/nNZlziFXosxbeZ8o0+VPIlFfFSu1GCx/UPMJhbCSHAuQrqClwCpYTLm8TRRm5X2qzIOoa/U4rGN6nUKKWgcFo9clbp+nL3oBfXgJGyZcvgRSJPID/MGUtkFPpZX8kEBWnyqdqQP7Ie0DB9J21AH6nANa/6ED/KgDegE4ABsqB4D0Dhgb9FTkQDfqABs6INCoA+xZB7pRB5LjDnTGAdhQO9AFB4wNeio4oDEeOUCMAxhqpowdKEnfgcQ4UPUdSA8c0PojB1LjQGkdEGadCA7oBeAAbAhWvgTSO2Bs0FPg24e0VA4IPJaB+iABZDQB/LkECDyagPRoAoS1X2gjX4rIfmHtFyROABtNAD9IAB9NQP1sAthoAqrjCWA2AdwkgEUJ4DYBPE4AHS0BdJABNpqB5NkM0NEMiOMZoDYDzGSARhlgNgMszkA6moHkIANiNAPNsxlIRzNQH89AajMgTAbSKAPCZkBEGSjLUQeyAweqUQfaZx0oRx1ojjtQWgcq40AZOVBZB6rIgVqMOiCGDtTZqAPdcw5o/YcOtEcd0AvAAdhQOQCkd8DYoKeCA1k1WgN0WANZPVoD6XM1oPUf1kB2tAb0AnAANlQ1AKR3wNigp0IN0HbMgWZoP+1G7c+es5+2o/bjo/brBWA/bKjsB9Lbb2zQU8F+hkYTkB7chPCoA+WzNyE06gA5fhNC9iaEzU0IRTchbG9COHZgtIt2B/anY/bDXfA5+8ebKD1uv22isKG2P2qixgY9Fdmv9oP7fM6M/UjbX4EhxBiiykbelp1xI9HSzhyoRGUONW7UqbGGhsVVtNjuFYIAD8lutVrGhs5/Ybbrw66qmpk+vSI/kjwh4AcBXoI8r+zkB/gDOdtzmT4QP6SZblnKnwR8EMZfagDXwb1dJ+yWKxdPM5ZXHK7uPDVM4ZhEMTNHMXhKaIS56qrl3DtXYeOcQ1plnITeTtwGtXo2IGYD4jdoFNNv0MEGnJnwcdVTWdjBdFE6uEyXYB83RldxEipkb6b9iqjcw4TNQu3382cWeAan9gcuohoAWyokP1Ac3S6UXApyqbrOEs/jTCpxzqOboBIFWPL4ZFG8DHiZ6nWd34ZD5sFm0BJ6ODfPIo1QGe1UWATgqp/RNk4lc6kMORS9NNcmYo1jVorZOqr2ab7HSItWLeknw6TbPWG1h9lWqTTZDmkWERJ8mlvc1yxMmvuaa6s5UlnTnkoWVPrrU0tCJjsby1Zn6AP4pZh1EHSpdLff1sKgVTCoA0/JNWptE3gqt3X08NiSkO8u8NTGNokKBCkkMY2TCKD8D5N4kK+mG8sX/v/IF+31RJsv96jajeYrpKaz6Af7XDS+MMsDzT6S7vRXPB/x2q/10XURVzxfjG3g+fS3Xp9P/5N6WCF5Bd7UvVqq7dsam41+W7T90MY/VE8TVU9USyVQNbe5Sfs11Y61UHfbK/s56rdO2zOjrDT9fJuro7n61olRBaccI8Z0veq+1D3Smgc62Fglustb3c9sKME0KsEIMyQqSNcywWOfubb2PNUywQHd8zoRRF1CuyAaEtoFnmujZWJ5TV4ileQ0auHgnUeS68uKd1C7TV7DhblW/Rsj5AVD13A3O7XadwjmVzM4pBnV8FJtugZ4NT14NX14/Y3D9yjmsmH/vuXdX0BgR8YQiNE4BP+TQ7zDY7js/h4ued9Kg8uyf9P4Bi7x8KAItvZQ6hAANnsE+FxzA7MuRhQP+fcI5yMo4wFlGAVmQFSZ+Z0DcDGy+3QkQNyVQjdytHXRKeYuM118EiHPUxXXYVNxDrpAR9CtRqFbfaszBiAfwWw5jlkL1uMoTUZRSv5KowyYHYcnH4Mnxn8Pn8kYPpNv4JOM43PY1QMieUCkyyzs6hHp0ZdEiCSB5xCJUSQYIMk8M4Jk7beOIUktNxmBZBJBsgw8D8kq8DwkmedpSPIBJHkESX0yMLjLs96dCX8Ti+5xpUVj9yEyfh8ah1C4w7jjCEWOCM8L95oyyPnbJQo8G6wn9dIa+hkUW9UrtnLknPjWpZDKv3Q3OXYbKceqrD5+FHzrxli18vCKko3VWvX3Si0du3y6d6zNX7mihOJysM88yL60Lo2luZRkBo++lsoo41XgHVxUylAKoebK6KZC/d5xdbn7SxoVoj9t0lCy/lRKQ217tGW+V9jXI+RBOWffjdjfjoCXNu6HI/tzjOJ17rcY+wsB8AR2Pw/Yd9aKR90La/tLCPBK7H4GsS/nFY+5N/P2dbHipe5dsX0Dq3ile/1qX2oCrxbujaZ9Twi8rHIvCe2PeMq3zP2CZ9/HAY+27mWcfcWl5JB7v2WDVT6odQmYDe0Kcqq/ICiQWcim/qql+hEBYqneZOuvSn9BuSsRwIXuyf43t8aog5UiKnaIqGYLw9ZoSh9UsFLwG57y1eawj95OmK9KmwKiek5dyuKHU8iHs9vfPpIHFWqnMTUajWK1WGtujOY2/o2BelXCHS/8QWXIqRJmbaK/jCrQ0bmWzh5U6pxwZmYT/WWM9q+ihZPS7dG/4K180BqHbdAJ6VNs5URrDOhMPBpXFGAl5FMJgUpqZRsj2xrZOn5/ZhxVr9X8KzSsX5eZ12fMquR5mmldqmhAl/6qzBfJdZvQdZ496KClJna18SDRX6pytTU2dMIERRgMmIT2z8lSxUQLpfGNrrSqhOW7I7Qy4sSyhf+9S5sjTIDdI5JiZxYHdXyxVGozm9U6Pt6VHZnNYO17mPmlRKOTmHli5p/ucGWSaX/y+meG4WxV7Maz4QgJ7Dawq4jdBXYd2DUK7CZi47AlidgksGnEpoHNIjYLbB6xeWCnETsJlrQROw3sLmKLoARF7CywccRWUKiMEsu9zgChgj5QQhktEWoTBP+Sjicd/GuyNlN0JXj6LVoIXiq6xI1ez0Wi1/OsqRXdom/PZ3Z+SJeoacbm28G8o509nWCVogVqy5h2/tGOZYY261PBynje+e/mS+vvsXnwKPuW/gaZ/Z19TLA6ts/Rw3gS1FYx3Yq21f5S0nRaQad3T7OEKJLhLlU0EV0L/w/kW9SfH8o3ouXafs7xWDyH+g7kj6x3/g3zP4xnZ9c3PEVj8kN/h/IZMvJNw8RYPob6hvKqzdTm90Jzdw9FwsiDqhAXQfCpiSN+jK6btjM7GguGtIsQPCHVY7RDiKO1hbW3kEUWcrCQBwtLRHuYOEY33FjUIJqM0Rlk2/jD+RjtLM5EvwazAYYdrT1QPVs8mNt/1IgoNCJMM1oSZAq9w5zGhQ+F0Css7gq9aYkOkzDAG9JuvS882mGtDxkguKDVIuk5xQVFcRocPdTn7HH0MXsd7eYpaIznHe3mK+Qak5kf0kP/U2RhJjpNCwrZHPMXG3lo5HRMfqh/KA+Fp0FQcVqNxmtgz1A+xIeVY/4O1w/lj+FjGE9n/1Beg7D1ZZQcL/QU8Soum2O0a30JNxEc0v7oEoOjTAyOsrhMOn2LN6/Zg4WtrhKw0UWJif4e6SHqRBxVJ39sfYPMcddykzW4IHRxlimi7Fs0syhoLGpSi5qhviHtUNhRmozZP9Q3pJ39fFCFw3ikgyp0/obj2tBDfRGq6jF7/eEgKB6LRzjuDa1y3CCPQnG8mScoSWPUHaMrfyAmdIxO7QGY2AgMaX8BG6A0G6A0buYN1k+G5oel4EGjUUrVpdJf0vQe2NYiwpyN0W7PxB55rne03BzSLuqE0nSM9lFH/V5UIn/J6Okb0g6VNWgco91+WYWrGBXOv+F+Q9qfHVZ+qM/lnEJdjMXD7afp/wOQlWye###1708:XlxV32DM    132a     694eNqNWEuO5DYMvcwcgPpasjeDZNOLWWSQ5ACSLS0b6MVkY9TdQ8mirWLJhSk0UPVoi99HSuqc8+aTB/xoUJDx4yCFHhu/rQc2vmCAbevx4/EpNjnDbPZPL2fhl19ezHL518O8qV0JpVSgRRH0WhYFU3WCBe1HmIwmp+M7nBveRJLVKadtddInXe05JUaYgjYtSO4f18ex9EkVLJyYRpjsBUgip1e8ulz1RbWlEXY5i4JXl4Y4QZ4KlnBgng+K58wPi5eKTLgWUWERVS2itF0RtdyVVoGWQEthFkfIEaQaYQoZhX6EKWStwI4whejw73RRny6GVw9pxQpH0Fq8x8mk3JOO4ytpjRQMX0k8cPXQXJ0gOhdD7QRQIUybPSpnnpjuGs4umZoG0zqDvX+3XjrjegyMCcA6h96n53y9Y+1++VdzBMmrMPKXkhydNKP3qUj0/PX9Z308nppki0m2R5KhS3KuSTYq0KIVzNQrUS3I0pFHOytZK9uM5k2mIW6VV61d6LnbTOWq80dRhGvMYPgMgpjXkiAchD4Jd5j7e+c/+fPib8PSjTExmTD56xkJPCOdYiRSnITASAjPJOT1If08Hv5+JcF0jat+z1E4DHDHiVi8atqpFUThV2UXphan0ABbD3X8TA4H0AAbOLBo+qoLbkare7Etqm0hCwED+llH4QbHu7QW+rX+4rDp3PeoAltFu2NJdiqWJSfOPh2Vf8brBnWDkPqQc2zcVPEU/ZFRhiHH6qF3Mo6wge1Ih9dihKnCNFvvnmdoDLl57l1jxM1z63Q4GRAwhaGmsJ8CYsIxIAsHjDl2bQVGPNNWb++whvdYwHNbR/dM49WZ+A7jrD3a6MY/Dzq9w6ElQZpjy0X9qm9rnNWhb+tE/jJ7fP1dPByn1oZcP9mHNvbu9G83/vH379ZTfDxePA3FHnN7oZFoY88pHiIZYR7PdQR6rr9j+rl94gvp5/whPnR7sR/Vm56HvgniOQYHU5A80o2BwrVzoj8yynE3uNcR7gb5deRZTw+mzgMpSxeeHljWA4pvJWyrUf31YjstqPuD6dp8so3lmEUxwmdXOdZlDAfQYYTPKkBXhXR6aF6rQLykKpBHuN3ZET55y/qOMHlAuHqQTw+EfC3DecFhO3Tirc1MpM5EgsuEujchGPuVezk0eHZoOCudxGki31tInJ1ujLuz78nWVK6qulqInQWDFsxlwdG9CY6DiFXtSsAwWTSsPxw7bUf3zKXIOpo/5/q6K0Z0GIB4Pjg8Puvl7ZDKeEktHlBEPaAAQiG7tfZ8S5j1Ek+X2E2X2F3iKC+xJvHjv39smURobob9b53w+lOuQnj7T0kp7AQQfvmw6/Jl0xIFpPLijPe5/cNuyzfrZ7ktMcUqhl68Lo+Y8lie1Y18GsrL5/v3P3cp/Ow3EcQkEgr+2Nfdrc17nBHLl0vLY3euiSSsTVSnLfb4jEcPzDi6j0Ha5RtOKIlZ2FOsQZV/g2DyJD5Y55DwK8ybXn7goU/sP2REAn7JsHziARKWTwFoe/kIW3FwT5lUQOQqzO+pyIpUYOaZCvubKiZSYRJXMf2eCnukDwkpdLmnfdiwPElNydKr2JbIX8VTieZV7IqHhxgr+df+E12A5SfuGGL5EqKALyErkkLNoXz54g5+h/a9VUe+pIRqGn+oagx/2KoeNf8P2T5ONQ==
\ No newline at end of file
diff --git a/AppleIIGateSch/chip74LS161_tb.v b/AppleIIGateSch/chip74LS161_tb.v
new file mode 100644
index 0000000..c60ccca
--- /dev/null
+++ b/AppleIIGateSch/chip74LS161_tb.v
@@ -0,0 +1,104 @@
+// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS161.sch - Wed May 23 13:17:20 2018
+
+`timescale 1ns / 1ps
+
+module chip74LS161_chip74LS161_sch_tb();
+
+// Inputs
+   reg CLK;
+   reg CLRn;
+   reg PEn;
+   reg CEP;
+   reg CET;
+   reg P0;
+   reg P1;
+   reg P2;
+   reg P3;
+
+// Output
+   wire Q1;
+   wire Q2;
+   wire Q3;
+   wire TC;
+   wire Q0;
+	
+// testbench Vars
+   integer i;
+
+// Bidirs
+
+// Instantiate the UUT
+   chip74LS161 UUT (
+		.CLK(CLK), 
+		.CLRn(CLRn), 
+		.Q0(Q0),
+		.Q1(Q1), 
+		.Q2(Q2), 
+		.Q3(Q3), 
+		.TC(TC), 
+		.PEn(PEn), 
+		.CEP(CEP), 
+		.CET(CET), 
+		.P0(P0), 
+		.P1(P1), 
+		.P2(P2), 
+		.P3(P3) 
+   );
+// Initialize Inputs
+   //`ifdef auto_init
+   initial begin
+		CLK = 0;
+		CLRn = 0;
+		PEn = 0;
+		CEP = 0;
+		CET = 0;
+		P0 = 0;
+		P1 = 0;
+		P2 = 0;
+		P3 = 0;
+   //`endif
+	  #100;
+	  #2 CLRn = 1; #2 CLRn=0; #2 CLRn=1;
+	  
+	  #2; CLK=1; #1;
+	  CEP=1;
+	  CET=1;
+	  PEn = 1;
+	  for (i=0; i<40; i=i+1) begin
+	    CLK=0; #2;
+		 CLK=1; #2;
+	  end
+     #4;
+     CLK=0; #2;
+     CLK=1; #2;
+	  P0 = 1;
+     P1 = 1;
+     P2 = 1;
+     P3 = 1;
+     PEn = 1;
+     CLK=0; #2;
+     CLK=1; #2;
+     PEn = 0;
+     CLK=0; #2;
+     CLK=1; #2;
+     PEn = 1;
+	  for (i=0; i<8; i=i+1) begin
+	    CLK=0; #2;
+		 CLK=1; #2;
+	  end
+	  #4;
+	  P0 = 0;
+     P1 = 1;
+     P2 = 1;
+     P3 = 0;
+     PEn = 0;
+     CLK=0; #2;
+     CLK=1; #2;
+     PEn = 1;
+	  for (i=0; i<8; i=i+1) begin
+	    CLK=0; #2;
+		 CLK=1; #2;
+	  end
+	end
+	
+endmodule
diff --git a/AppleIIGateSch/chip74LS175.cmd_log b/AppleIIGateSch/chip74LS175.cmd_log
new file mode 100644
index 0000000..1f12aa7
--- /dev/null
+++ b/AppleIIGateSch/chip74LS175.cmd_log
@@ -0,0 +1,2 @@
+sch2hdl -intstyle ise -family spartan3e -verilog chip74LS175_drc.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS175.sch 
+sch2verilog -intstyle ise -family spartan3e -tionly {} -tiext tfi -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS175.sch chip74LS175.tfi 
diff --git a/AppleIIGateSch/chip74LS175.jhd b/AppleIIGateSch/chip74LS175.jhd
new file mode 100644
index 0000000..4c8a44e
--- /dev/null
+++ b/AppleIIGateSch/chip74LS175.jhd
@@ -0,0 +1 @@
+MODULE chip74LS175
diff --git a/AppleIIGateSch/chip74LS175.sch b/AppleIIGateSch/chip74LS175.sch
new file mode 100644
index 0000000..4ec124f
--- /dev/null
+++ b/AppleIIGateSch/chip74LS175.sch
@@ -0,0 +1,235 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+    <attr value="spartan3e" name="DeviceFamilyName">
+        <trait delete="all:0" />
+        <trait editname="all:0" />
+        <trait edittrait="all:0" />
+    </attr>
+    <netlist>
+        <signal name="Q0" />
+        <signal name="Q0n" />
+        <signal name="Q3" />
+        <signal name="Q2" />
+        <signal name="Q1" />
+        <signal name="Q1n" />
+        <signal name="Q2n" />
+        <signal name="Q3n" />
+        <signal name="D0" />
+        <signal name="D1" />
+        <signal name="D2" />
+        <signal name="D3" />
+        <signal name="CP" />
+        <signal name="XLXN_19" />
+        <signal name="CLRn" />
+        <port polarity="Output" name="Q0" />
+        <port polarity="Output" name="Q0n" />
+        <port polarity="Output" name="Q3" />
+        <port polarity="Output" name="Q2" />
+        <port polarity="Output" name="Q1" />
+        <port polarity="Output" name="Q1n" />
+        <port polarity="Output" name="Q2n" />
+        <port polarity="Output" name="Q3n" />
+        <port polarity="Input" name="D0" />
+        <port polarity="Input" name="D1" />
+        <port polarity="Input" name="D2" />
+        <port polarity="Input" name="D3" />
+        <port polarity="Input" name="CP" />
+        <port polarity="Input" name="CLRn" />
+        <blockdef name="fdc">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="64" y1="-256" y2="-256" x1="0" />
+            <line x2="320" y1="-256" y2="-256" x1="384" />
+            <rect width="256" x="64" y="-320" height="256" />
+            <line x2="80" y1="-112" y2="-128" x1="64" />
+            <line x2="64" y1="-128" y2="-144" x1="80" />
+            <line x2="192" y1="-64" y2="-32" x1="192" />
+            <line x2="64" y1="-32" y2="-32" x1="192" />
+        </blockdef>
+        <blockdef name="inv">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="160" y1="-32" y2="-32" x1="224" />
+            <line x2="128" y1="-64" y2="-32" x1="64" />
+            <line x2="64" y1="-32" y2="0" x1="128" />
+            <line x2="64" y1="0" y2="-64" x1="64" />
+            <circle r="16" cx="144" cy="-32" />
+        </blockdef>
+        <block symbolname="fdc" name="XLXI_1">
+            <blockpin signalname="CP" name="C" />
+            <blockpin signalname="XLXN_19" name="CLR" />
+            <blockpin signalname="D0" name="D" />
+            <blockpin signalname="Q0" name="Q" />
+        </block>
+        <block symbolname="fdc" name="XLXI_2">
+            <blockpin signalname="CP" name="C" />
+            <blockpin signalname="XLXN_19" name="CLR" />
+            <blockpin signalname="D1" name="D" />
+            <blockpin signalname="Q1" name="Q" />
+        </block>
+        <block symbolname="fdc" name="XLXI_3">
+            <blockpin signalname="CP" name="C" />
+            <blockpin signalname="XLXN_19" name="CLR" />
+            <blockpin signalname="D2" name="D" />
+            <blockpin signalname="Q2" name="Q" />
+        </block>
+        <block symbolname="fdc" name="XLXI_4">
+            <blockpin signalname="CP" name="C" />
+            <blockpin signalname="XLXN_19" name="CLR" />
+            <blockpin signalname="D3" name="D" />
+            <blockpin signalname="Q3" name="Q" />
+        </block>
+        <block symbolname="inv" name="XLXI_5">
+            <blockpin signalname="Q0" name="I" />
+            <blockpin signalname="Q0n" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_6">
+            <blockpin signalname="Q1" name="I" />
+            <blockpin signalname="Q1n" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_7">
+            <blockpin signalname="Q2" name="I" />
+            <blockpin signalname="Q2n" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_8">
+            <blockpin signalname="Q3" name="I" />
+            <blockpin signalname="Q3n" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_9">
+            <blockpin signalname="CLRn" name="I" />
+            <blockpin signalname="XLXN_19" name="O" />
+        </block>
+    </netlist>
+    <sheet sheetnum="1" width="3520" height="2720">
+        <instance x="2320" y="928" name="XLXI_1" orien="R0" />
+        <instance x="2320" y="1344" name="XLXI_2" orien="R0" />
+        <instance x="2320" y="1728" name="XLXI_3" orien="R0" />
+        <instance x="2320" y="2096" name="XLXI_4" orien="R0" />
+        <instance x="2832" y="832" name="XLXI_5" orien="R0" />
+        <branch name="Q0">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3088" y="672" type="branch" />
+            <wire x2="2768" y1="672" y2="672" x1="2704" />
+            <wire x2="2768" y1="672" y2="800" x1="2768" />
+            <wire x2="2832" y1="800" y2="800" x1="2768" />
+            <wire x2="3088" y1="672" y2="672" x1="2768" />
+            <wire x2="3152" y1="672" y2="672" x1="3088" />
+        </branch>
+        <branch name="Q0n">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3088" y="800" type="branch" />
+            <wire x2="3088" y1="800" y2="800" x1="3056" />
+            <wire x2="3152" y1="800" y2="800" x1="3088" />
+        </branch>
+        <instance x="2832" y="1248" name="XLXI_6" orien="R0" />
+        <instance x="2832" y="1632" name="XLXI_7" orien="R0" />
+        <branch name="Q3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="1840" type="branch" />
+            <wire x2="2752" y1="1840" y2="1840" x1="2704" />
+            <wire x2="3104" y1="1840" y2="1840" x1="2752" />
+            <wire x2="3168" y1="1840" y2="1840" x1="3104" />
+            <wire x2="2752" y1="1840" y2="1984" x1="2752" />
+            <wire x2="2832" y1="1984" y2="1984" x1="2752" />
+        </branch>
+        <branch name="Q2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="1472" type="branch" />
+            <wire x2="2768" y1="1472" y2="1472" x1="2704" />
+            <wire x2="2768" y1="1472" y2="1600" x1="2768" />
+            <wire x2="2832" y1="1600" y2="1600" x1="2768" />
+            <wire x2="3104" y1="1472" y2="1472" x1="2768" />
+            <wire x2="3168" y1="1472" y2="1472" x1="3104" />
+        </branch>
+        <branch name="Q1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="1088" type="branch" />
+            <wire x2="2768" y1="1088" y2="1088" x1="2704" />
+            <wire x2="2768" y1="1088" y2="1216" x1="2768" />
+            <wire x2="2832" y1="1216" y2="1216" x1="2768" />
+            <wire x2="3104" y1="1088" y2="1088" x1="2768" />
+            <wire x2="3152" y1="1088" y2="1088" x1="3104" />
+        </branch>
+        <branch name="Q1n">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="1216" type="branch" />
+            <wire x2="3104" y1="1216" y2="1216" x1="3056" />
+            <wire x2="3168" y1="1216" y2="1216" x1="3104" />
+        </branch>
+        <branch name="Q2n">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3120" y="1600" type="branch" />
+            <wire x2="3120" y1="1600" y2="1600" x1="3056" />
+            <wire x2="3184" y1="1600" y2="1600" x1="3120" />
+        </branch>
+        <branch name="Q3n">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="1984" type="branch" />
+            <wire x2="3104" y1="1984" y2="1984" x1="3056" />
+            <wire x2="3168" y1="1984" y2="1984" x1="3104" />
+        </branch>
+        <branch name="D0">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1664" y="672" type="branch" />
+            <wire x2="1664" y1="672" y2="672" x1="1568" />
+            <wire x2="2320" y1="672" y2="672" x1="1664" />
+        </branch>
+        <branch name="D1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1680" y="944" type="branch" />
+            <wire x2="1680" y1="944" y2="944" x1="1568" />
+            <wire x2="1984" y1="944" y2="944" x1="1680" />
+            <wire x2="1984" y1="944" y2="1088" x1="1984" />
+            <wire x2="2320" y1="1088" y2="1088" x1="1984" />
+        </branch>
+        <branch name="D2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1696" y="1216" type="branch" />
+            <wire x2="1696" y1="1216" y2="1216" x1="1568" />
+            <wire x2="1984" y1="1216" y2="1216" x1="1696" />
+            <wire x2="1984" y1="1216" y2="1472" x1="1984" />
+            <wire x2="2320" y1="1472" y2="1472" x1="1984" />
+        </branch>
+        <branch name="D3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1696" y="1472" type="branch" />
+            <wire x2="1696" y1="1472" y2="1472" x1="1568" />
+            <wire x2="1840" y1="1472" y2="1472" x1="1696" />
+            <wire x2="1840" y1="1472" y2="1840" x1="1840" />
+            <wire x2="2320" y1="1840" y2="1840" x1="1840" />
+        </branch>
+        <branch name="CP">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1664" y="1968" type="branch" />
+            <wire x2="1664" y1="1968" y2="1968" x1="1584" />
+            <wire x2="2240" y1="1968" y2="1968" x1="1664" />
+            <wire x2="2320" y1="1968" y2="1968" x1="2240" />
+            <wire x2="2320" y1="800" y2="800" x1="2240" />
+            <wire x2="2240" y1="800" y2="1216" x1="2240" />
+            <wire x2="2240" y1="1216" y2="1600" x1="2240" />
+            <wire x2="2240" y1="1600" y2="1968" x1="2240" />
+            <wire x2="2320" y1="1600" y2="1600" x1="2240" />
+            <wire x2="2320" y1="1216" y2="1216" x1="2240" />
+        </branch>
+        <branch name="XLXN_19">
+            <wire x2="2000" y1="2064" y2="2064" x1="1920" />
+            <wire x2="2128" y1="2064" y2="2064" x1="2000" />
+            <wire x2="2320" y1="2064" y2="2064" x1="2128" />
+            <wire x2="2320" y1="896" y2="896" x1="2128" />
+            <wire x2="2128" y1="896" y2="1312" x1="2128" />
+            <wire x2="2320" y1="1312" y2="1312" x1="2128" />
+            <wire x2="2128" y1="1312" y2="1696" x1="2128" />
+            <wire x2="2128" y1="1696" y2="2064" x1="2128" />
+            <wire x2="2320" y1="1696" y2="1696" x1="2128" />
+        </branch>
+        <instance x="1696" y="2096" name="XLXI_9" orien="R0" />
+        <branch name="CLRn">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1664" y="2064" type="branch" />
+            <wire x2="1664" y1="2064" y2="2064" x1="1584" />
+            <wire x2="1696" y1="2064" y2="2064" x1="1664" />
+        </branch>
+        <iomarker fontsize="28" x="1568" y="672" name="D0" orien="R180" />
+        <iomarker fontsize="28" x="1568" y="944" name="D1" orien="R180" />
+        <iomarker fontsize="28" x="1568" y="1216" name="D2" orien="R180" />
+        <iomarker fontsize="28" x="1568" y="1472" name="D3" orien="R180" />
+        <iomarker fontsize="28" x="1584" y="1968" name="CP" orien="R180" />
+        <iomarker fontsize="28" x="1584" y="2064" name="CLRn" orien="R180" />
+        <iomarker fontsize="28" x="3152" y="672" name="Q0" orien="R0" />
+        <iomarker fontsize="28" x="3152" y="800" name="Q0n" orien="R0" />
+        <iomarker fontsize="28" x="3152" y="1088" name="Q1" orien="R0" />
+        <iomarker fontsize="28" x="3168" y="1216" name="Q1n" orien="R0" />
+        <iomarker fontsize="28" x="3168" y="1472" name="Q2" orien="R0" />
+        <iomarker fontsize="28" x="3184" y="1600" name="Q2n" orien="R0" />
+        <instance x="2832" y="2016" name="XLXI_8" orien="R0" />
+        <iomarker fontsize="28" x="3168" y="1840" name="Q3" orien="R0" />
+        <iomarker fontsize="28" x="3168" y="1984" name="Q3n" orien="R0" />
+    </sheet>
+</drawing>
\ No newline at end of file
diff --git a/AppleIIGateSch/chip74LS175.sym b/AppleIIGateSch/chip74LS175.sym
new file mode 100644
index 0000000..99f62aa
--- /dev/null
+++ b/AppleIIGateSch/chip74LS175.sym
@@ -0,0 +1,56 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="chip74LS175">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2018-5-27T1:40:50</timestamp>
+    <pin polarity="Input" x="0" y="-416" name="CLRn" />
+    <pin polarity="Input" x="0" y="-480" name="CP" />
+    <pin polarity="Input" x="0" y="-160" name="D0" />
+    <pin polarity="Input" x="0" y="-224" name="D1" />
+    <pin polarity="Input" x="0" y="-288" name="D2" />
+    <pin polarity="Input" x="0" y="-352" name="D3" />
+    <pin polarity="Output" x="384" y="-32" name="Q0" />
+    <pin polarity="Output" x="384" y="-96" name="Q0n" />
+    <pin polarity="Output" x="384" y="-160" name="Q1" />
+    <pin polarity="Output" x="384" y="-224" name="Q1n" />
+    <pin polarity="Output" x="384" y="-288" name="Q2" />
+    <pin polarity="Output" x="384" y="-352" name="Q2n" />
+    <pin polarity="Output" x="384" y="-416" name="Q3" />
+    <pin polarity="Output" x="384" y="-480" name="Q3n" />
+    <graph>
+        <rect width="256" x="64" y="-512" height="512" />
+        <attrtext style="alignment:BCENTER;fontsize:40;fontname:Arial" attrname="SymbolName" x="192" y="-520" type="symbol" />
+        <line x2="0" y1="-416" y2="-416" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin CLRn" />
+        <line x2="0" y1="-480" y2="-480" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-480" type="pin CP" />
+        <line x2="0" y1="-160" y2="-160" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin D0" />
+        <line x2="0" y1="-224" y2="-224" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin D1" />
+        <line x2="0" y1="-288" y2="-288" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin D2" />
+        <line x2="0" y1="-352" y2="-352" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin D3" />
+        <line x2="384" y1="-32" y2="-32" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin Q0" />
+        <line x2="384" y1="-96" y2="-96" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin Q0n" />
+        <line x2="384" y1="-160" y2="-160" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin Q1" />
+        <line x2="384" y1="-224" y2="-224" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin Q1n" />
+        <line x2="384" y1="-288" y2="-288" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin Q2" />
+        <line x2="384" y1="-352" y2="-352" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-352" type="pin Q2n" />
+        <line x2="384" y1="-416" y2="-416" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin Q3" />
+        <line x2="384" y1="-480" y2="-480" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-480" type="pin Q3n" />
+        <circle r="10" cx="54" cy="-418" />
+        <circle r="8" cx="332" cy="-480" />
+        <circle r="10" cx="330" cy="-352" />
+        <circle r="8" cx="332" cy="-224" />
+        <circle r="8" cx="332" cy="-100" />
+    </graph>
+</symbol>
diff --git a/AppleIIGateSch/chip74LS175_beh.prj b/AppleIIGateSch/chip74LS175_beh.prj
new file mode 100644
index 0000000..358eb50
--- /dev/null
+++ b/AppleIIGateSch/chip74LS175_beh.prj
@@ -0,0 +1,2 @@
+verilog work "chip74LS175.vf"
+verilog work "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
diff --git a/AppleIIGateSch/chip74LS175_tb.v b/AppleIIGateSch/chip74LS175_tb.v
new file mode 100644
index 0000000..313dce7
--- /dev/null
+++ b/AppleIIGateSch/chip74LS175_tb.v
@@ -0,0 +1,104 @@
+// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS175.sch - Thu May 24 17:45:09 2018
+
+`timescale 1ns / 1ps
+
+module chip74LS175_chip74LS175_sch_tb();
+
+// Inputs
+  reg D0;
+  reg D1;
+  reg D2;
+  reg D3;
+  reg CP;
+  reg CLRn;
+
+// Output
+  wire Q0;
+  wire Q0n;
+  wire Q3;
+  wire Q2;
+  wire Q1;
+  wire Q1n;
+  wire Q2n;
+  wire Q3n;
+  wire [3:0] Qbus  = {Q3,Q2,Q1,Q0};
+  wire [3:0] Qbusn = {Q3n,Q2n,Q1n,Q0n};
+	
+// TB
+  integer i;
+  integer errcnt;
+
+// Bidirs
+
+// Instantiate the UUT
+   chip74LS175 UUT (
+		.Q0(Q0), 
+		.Q0n(Q0n), 
+		.Q3(Q3), 
+		.Q2(Q2), 
+		.Q1(Q1), 
+		.Q1n(Q1n), 
+		.Q2n(Q2n), 
+		.Q3n(Q3n), 
+		.D0(D0), 
+		.D1(D1), 
+		.D2(D2), 
+		.D3(D3), 
+		.CP(CP), 
+		.CLRn(CLRn)
+   );
+// Initialize Inputs
+//  `ifndef auto_init
+    initial begin
+	   $display("auto_init not set");
+		#100;
+      D0 = 0;
+		D1 = 0;
+		D2 = 0;
+		D3 = 0;
+		CP = 0;
+		CLRn = 0;
+		errcnt = 0;
+		#5;
+		CLRn = 1;
+		#5;
+		for (i=0; i<16; i=i+1) begin
+		  CLRn = 1;
+		  {D3,D2,D1,D0} = i[3:0];
+		  CP = 0;  #5;  CP = 1;  #5;
+		  if ( Qbus != i[3:0] ) begin
+		    $display("Wrong answer i=%d Qbus=%d", i[3:0], Qbus);
+			 errcnt = errcnt + 1;
+		  end
+		  if ( Qbusn != ~i[3:0] ) begin
+		    $display("Wrong answer i=%d ~Qbus=%d", i[3:0], ~Qbus);
+			 errcnt = errcnt + 1;
+        end
+		  //CP = 0;  #5;  CP = 1;  #5;
+		  //if ( Qbus != (i[3:0]+1) ) begin
+		  //  $display("Wrong answer i=%d Qbus=%d", i[3:0]+1, Qbus);
+		  //end
+		  CLRn = 0; CP = 0; #5;  CP = 1;  #5;
+		  if ( Qbus != 0 ) begin
+		    $display("Wrong answer i=%d CLRn=0 Qbus=%d should be zero", i[3:0]+1, Qbus);
+			 errcnt = errcnt + 1;
+		  end
+		  if ( Qbusn != 4'hf ) begin
+		    $display("Wrong answer i=%d CLRn=0 Qbusn=%d should be 15. ~0", i[3:0]+1, Qbusn);
+			 errcnt = errcnt + 1;
+		  end
+		end
+		if ( errcnt == 0 ) begin
+		  $display("**** PASSED ****   errcnt=0");
+		end else begin
+		  $display("!!!! FAILED !!!! errcnt=%d", errcnt);
+		end
+	 end	  
+		
+//  `else begin
+//     initial begin
+//       $display("SET auto_init");
+//	  end
+//	end
+//  `endif
+endmodule
diff --git a/AppleIIGateSch/chip74LS257.jhd b/AppleIIGateSch/chip74LS257.jhd
new file mode 100644
index 0000000..2c42631
--- /dev/null
+++ b/AppleIIGateSch/chip74LS257.jhd
@@ -0,0 +1 @@
+MODULE chip74LS257
diff --git a/AppleIIGateSch/chip74LS257.sch b/AppleIIGateSch/chip74LS257.sch
new file mode 100644
index 0000000..1cd9079
--- /dev/null
+++ b/AppleIIGateSch/chip74LS257.sch
@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+    <attr value="spartan3e" name="DeviceFamilyName">
+        <trait delete="all:0" />
+        <trait editname="all:0" />
+        <trait edittrait="all:0" />
+    </attr>
+    <netlist>
+        <signal name="XLXN_1" />
+        <signal name="XLXN_2" />
+        <signal name="XLXN_3" />
+        <signal name="XLXN_4" />
+        <signal name="XLXN_5" />
+        <signal name="XLXN_6" />
+        <signal name="XLXN_7" />
+        <signal name="XLXN_8" />
+        <signal name="XLXN_9" />
+        <signal name="XLXN_10" />
+        <signal name="XLXN_11" />
+        <signal name="XLXN_12" />
+        <signal name="XLXN_13" />
+        <signal name="XLXN_14" />
+        <signal name="XLXN_15" />
+        <signal name="En_15" />
+        <signal name="XLXN_17" />
+        <signal name="XLXN_18" />
+        <signal name="XLXN_19" />
+        <signal name="XLXN_20" />
+        <signal name="XLXN_21" />
+        <signal name="XLXN_22" />
+        <signal name="XLXN_23" />
+        <signal name="S_1" />
+        <signal name="i0a_2" />
+        <signal name="i1a_3" />
+        <signal name="i0b_5" />
+        <signal name="i1b_6" />
+        <signal name="i0c_11" />
+        <signal name="i1c_10" />
+        <signal name="i0d_14" />
+        <signal name="i1d_13" />
+        <signal name="Za_4" />
+        <signal name="Zb_7" />
+        <signal name="Zc_9" />
+        <signal name="Zd_12" />
+        <port polarity="Input" name="En_15" />
+        <port polarity="Input" name="S_1" />
+        <port polarity="Input" name="i0a_2" />
+        <port polarity="Input" name="i1a_3" />
+        <port polarity="Input" name="i0b_5" />
+        <port polarity="Input" name="i1b_6" />
+        <port polarity="Input" name="i0c_11" />
+        <port polarity="Input" name="i1c_10" />
+        <port polarity="Input" name="i0d_14" />
+        <port polarity="Input" name="i1d_13" />
+        <port polarity="Output" name="Za_4" />
+        <port polarity="Output" name="Zb_7" />
+        <port polarity="Output" name="Zc_9" />
+        <port polarity="Output" name="Zd_12" />
+        <blockdef name="or2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="192" y1="-96" y2="-96" x1="256" />
+            <arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
+            <arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
+            <line x2="48" y1="-144" y2="-144" x1="112" />
+            <arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
+            <line x2="48" y1="-48" y2="-48" x1="112" />
+        </blockdef>
+        <blockdef name="and2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="192" y1="-96" y2="-96" x1="256" />
+            <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+            <line x2="64" y1="-48" y2="-48" x1="144" />
+            <line x2="144" y1="-144" y2="-144" x1="64" />
+            <line x2="64" y1="-48" y2="-144" x1="64" />
+        </blockdef>
+        <blockdef name="bufgce">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="128" y1="-32" y2="-32" x1="224" />
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="64" y1="-96" y2="-96" x1="0" />
+            <line x2="96" y1="-48" y2="-96" x1="96" />
+            <line x2="64" y1="-96" y2="-96" x1="96" />
+            <line x2="128" y1="0" y2="-32" x1="64" />
+            <line x2="64" y1="-32" y2="-64" x1="128" />
+            <line x2="64" y1="-64" y2="0" x1="64" />
+        </blockdef>
+        <blockdef name="inv">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="160" y1="-32" y2="-32" x1="224" />
+            <line x2="128" y1="-64" y2="-32" x1="64" />
+            <line x2="64" y1="-32" y2="0" x1="128" />
+            <line x2="64" y1="0" y2="-64" x1="64" />
+            <circle r="16" cx="144" cy="-32" />
+        </blockdef>
+        <block symbolname="or2" name="XLXI_1">
+            <blockpin signalname="XLXN_2" name="I0" />
+            <blockpin signalname="XLXN_1" name="I1" />
+            <blockpin signalname="XLXN_9" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_2">
+            <blockpin signalname="XLXN_4" name="I0" />
+            <blockpin signalname="XLXN_3" name="I1" />
+            <blockpin signalname="XLXN_10" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_3">
+            <blockpin signalname="XLXN_6" name="I0" />
+            <blockpin signalname="XLXN_5" name="I1" />
+            <blockpin signalname="XLXN_11" name="O" />
+        </block>
+        <block symbolname="or2" name="XLXI_4">
+            <blockpin signalname="XLXN_8" name="I0" />
+            <blockpin signalname="XLXN_7" name="I1" />
+            <blockpin signalname="XLXN_12" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_5">
+            <blockpin signalname="XLXN_20" name="I0" />
+            <blockpin signalname="i0a_2" name="I1" />
+            <blockpin signalname="XLXN_1" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_6">
+            <blockpin signalname="XLXN_17" name="I0" />
+            <blockpin signalname="i1a_3" name="I1" />
+            <blockpin signalname="XLXN_2" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_7">
+            <blockpin signalname="XLXN_20" name="I0" />
+            <blockpin signalname="i0b_5" name="I1" />
+            <blockpin signalname="XLXN_3" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_8">
+            <blockpin signalname="XLXN_17" name="I0" />
+            <blockpin signalname="i1b_6" name="I1" />
+            <blockpin signalname="XLXN_4" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_9">
+            <blockpin signalname="XLXN_20" name="I0" />
+            <blockpin signalname="i0c_11" name="I1" />
+            <blockpin signalname="XLXN_5" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_10">
+            <blockpin signalname="XLXN_17" name="I0" />
+            <blockpin signalname="i1c_10" name="I1" />
+            <blockpin signalname="XLXN_6" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_11">
+            <blockpin signalname="XLXN_20" name="I0" />
+            <blockpin signalname="i0d_14" name="I1" />
+            <blockpin signalname="XLXN_7" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_12">
+            <blockpin signalname="XLXN_17" name="I0" />
+            <blockpin signalname="i1d_13" name="I1" />
+            <blockpin signalname="XLXN_8" name="O" />
+        </block>
+        <block symbolname="bufgce" name="XLXI_13">
+            <blockpin signalname="XLXN_15" name="CE" />
+            <blockpin signalname="XLXN_10" name="I" />
+            <blockpin signalname="Zb_7" name="O" />
+        </block>
+        <block symbolname="bufgce" name="XLXI_14">
+            <blockpin signalname="XLXN_15" name="CE" />
+            <blockpin signalname="XLXN_9" name="I" />
+            <blockpin signalname="Za_4" name="O" />
+        </block>
+        <block symbolname="bufgce" name="XLXI_15">
+            <blockpin signalname="XLXN_15" name="CE" />
+            <blockpin signalname="XLXN_11" name="I" />
+            <blockpin signalname="Zc_9" name="O" />
+        </block>
+        <block symbolname="bufgce" name="XLXI_16">
+            <blockpin signalname="XLXN_15" name="CE" />
+            <blockpin signalname="XLXN_12" name="I" />
+            <blockpin signalname="Zd_12" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_17">
+            <blockpin signalname="En_15" name="I" />
+            <blockpin signalname="XLXN_15" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_18">
+            <blockpin signalname="XLXN_20" name="I" />
+            <blockpin signalname="XLXN_17" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_19">
+            <blockpin signalname="S_1" name="I" />
+            <blockpin signalname="XLXN_20" name="O" />
+        </block>
+    </netlist>
+    <sheet sheetnum="1" width="3520" height="2720">
+        <instance x="2528" y="944" name="XLXI_1" orien="R0" />
+        <instance x="2528" y="1232" name="XLXI_2" orien="R0" />
+        <instance x="2528" y="1824" name="XLXI_4" orien="R0" />
+        <instance x="2160" y="1168" name="XLXI_7" orien="R0" />
+        <instance x="2160" y="1296" name="XLXI_8" orien="R0" />
+        <instance x="2160" y="1472" name="XLXI_9" orien="R0" />
+        <instance x="2160" y="1600" name="XLXI_10" orien="R0" />
+        <instance x="2160" y="1760" name="XLXI_11" orien="R0" />
+        <instance x="2160" y="1888" name="XLXI_12" orien="R0" />
+        <instance x="2160" y="1008" name="XLXI_6" orien="R0" />
+        <instance x="2160" y="880" name="XLXI_5" orien="R0" />
+        <instance x="2528" y="1536" name="XLXI_3" orien="R0" />
+        <branch name="XLXN_1">
+            <wire x2="2464" y1="784" y2="784" x1="2416" />
+            <wire x2="2464" y1="784" y2="816" x1="2464" />
+            <wire x2="2528" y1="816" y2="816" x1="2464" />
+        </branch>
+        <branch name="XLXN_2">
+            <wire x2="2464" y1="912" y2="912" x1="2416" />
+            <wire x2="2464" y1="880" y2="912" x1="2464" />
+            <wire x2="2528" y1="880" y2="880" x1="2464" />
+        </branch>
+        <branch name="XLXN_3">
+            <wire x2="2464" y1="1072" y2="1072" x1="2416" />
+            <wire x2="2464" y1="1072" y2="1104" x1="2464" />
+            <wire x2="2528" y1="1104" y2="1104" x1="2464" />
+        </branch>
+        <branch name="XLXN_4">
+            <wire x2="2464" y1="1200" y2="1200" x1="2416" />
+            <wire x2="2464" y1="1168" y2="1200" x1="2464" />
+            <wire x2="2528" y1="1168" y2="1168" x1="2464" />
+        </branch>
+        <branch name="XLXN_5">
+            <wire x2="2464" y1="1376" y2="1376" x1="2416" />
+            <wire x2="2464" y1="1376" y2="1408" x1="2464" />
+            <wire x2="2528" y1="1408" y2="1408" x1="2464" />
+        </branch>
+        <branch name="XLXN_6">
+            <wire x2="2464" y1="1504" y2="1504" x1="2416" />
+            <wire x2="2464" y1="1472" y2="1504" x1="2464" />
+            <wire x2="2528" y1="1472" y2="1472" x1="2464" />
+        </branch>
+        <branch name="XLXN_7">
+            <wire x2="2464" y1="1664" y2="1664" x1="2416" />
+            <wire x2="2464" y1="1664" y2="1696" x1="2464" />
+            <wire x2="2528" y1="1696" y2="1696" x1="2464" />
+        </branch>
+        <branch name="XLXN_8">
+            <wire x2="2464" y1="1792" y2="1792" x1="2416" />
+            <wire x2="2464" y1="1760" y2="1792" x1="2464" />
+            <wire x2="2528" y1="1760" y2="1760" x1="2464" />
+        </branch>
+        <instance x="2848" y="1168" name="XLXI_13" orien="R0" />
+        <instance x="2848" y="880" name="XLXI_14" orien="R0" />
+        <instance x="2848" y="1472" name="XLXI_15" orien="R0" />
+        <instance x="2848" y="1760" name="XLXI_16" orien="R0" />
+        <branch name="XLXN_9">
+            <wire x2="2848" y1="848" y2="848" x1="2784" />
+        </branch>
+        <branch name="XLXN_10">
+            <wire x2="2848" y1="1136" y2="1136" x1="2784" />
+        </branch>
+        <branch name="XLXN_11">
+            <wire x2="2848" y1="1440" y2="1440" x1="2784" />
+        </branch>
+        <branch name="XLXN_12">
+            <wire x2="2848" y1="1728" y2="1728" x1="2784" />
+        </branch>
+        <branch name="XLXN_15">
+            <wire x2="2832" y1="608" y2="608" x1="1760" />
+            <wire x2="2832" y1="608" y2="784" x1="2832" />
+            <wire x2="2848" y1="784" y2="784" x1="2832" />
+            <wire x2="2832" y1="784" y2="1072" x1="2832" />
+            <wire x2="2848" y1="1072" y2="1072" x1="2832" />
+            <wire x2="2832" y1="1072" y2="1376" x1="2832" />
+            <wire x2="2848" y1="1376" y2="1376" x1="2832" />
+            <wire x2="2832" y1="1376" y2="1664" x1="2832" />
+            <wire x2="2848" y1="1664" y2="1664" x1="2832" />
+        </branch>
+        <instance x="1536" y="640" name="XLXI_17" orien="R0" />
+        <branch name="En_15">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1328" y="608" type="branch" />
+            <wire x2="1328" y1="608" y2="608" x1="1280" />
+            <wire x2="1536" y1="608" y2="608" x1="1328" />
+        </branch>
+        <iomarker fontsize="28" x="1280" y="608" name="En_15" orien="R180" />
+        <text style="fontsize:20;fontname:Arial" x="1296" y="544">Gn instead of En in TTL Bookr</text>
+        <branch name="XLXN_17">
+            <wire x2="2080" y1="1968" y2="1968" x1="2064" />
+            <wire x2="2160" y1="944" y2="944" x1="2080" />
+            <wire x2="2080" y1="944" y2="1232" x1="2080" />
+            <wire x2="2160" y1="1232" y2="1232" x1="2080" />
+            <wire x2="2080" y1="1232" y2="1536" x1="2080" />
+            <wire x2="2160" y1="1536" y2="1536" x1="2080" />
+            <wire x2="2080" y1="1536" y2="1824" x1="2080" />
+            <wire x2="2160" y1="1824" y2="1824" x1="2080" />
+            <wire x2="2080" y1="1824" y2="1968" x1="2080" />
+        </branch>
+        <branch name="XLXN_20">
+            <wire x2="1824" y1="1968" y2="1968" x1="1792" />
+            <wire x2="1840" y1="1968" y2="1968" x1="1824" />
+            <wire x2="1824" y1="816" y2="1104" x1="1824" />
+            <wire x2="1824" y1="1104" y2="1408" x1="1824" />
+            <wire x2="1824" y1="1408" y2="1696" x1="1824" />
+            <wire x2="2160" y1="1696" y2="1696" x1="1824" />
+            <wire x2="1824" y1="1696" y2="1968" x1="1824" />
+            <wire x2="2160" y1="1408" y2="1408" x1="1824" />
+            <wire x2="2160" y1="1104" y2="1104" x1="1824" />
+            <wire x2="2160" y1="816" y2="816" x1="1824" />
+        </branch>
+        <instance x="1840" y="2000" name="XLXI_18" orien="R0" />
+        <instance x="1568" y="2000" name="XLXI_19" orien="R0" />
+        <branch name="S_1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1264" y="1968" type="branch" />
+            <wire x2="1264" y1="1968" y2="1968" x1="1216" />
+            <wire x2="1568" y1="1968" y2="1968" x1="1264" />
+        </branch>
+        <iomarker fontsize="28" x="1216" y="1968" name="S_1" orien="R180" />
+        <text style="fontsize:20;fontname:Arial" x="1248" y="1996">An/B instead of S in TTL Book</text>
+        <branch name="i0a_2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1360" y="752" type="branch" />
+            <wire x2="1360" y1="752" y2="752" x1="1296" />
+            <wire x2="2160" y1="752" y2="752" x1="1360" />
+        </branch>
+        <branch name="i1a_3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="880" type="branch" />
+            <wire x2="1344" y1="880" y2="880" x1="1296" />
+            <wire x2="2160" y1="880" y2="880" x1="1344" />
+        </branch>
+        <branch name="i0b_5">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="1040" type="branch" />
+            <wire x2="1344" y1="1040" y2="1040" x1="1296" />
+            <wire x2="2160" y1="1040" y2="1040" x1="1344" />
+        </branch>
+        <branch name="i1b_6">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1328" y="1168" type="branch" />
+            <wire x2="1328" y1="1168" y2="1168" x1="1296" />
+            <wire x2="2160" y1="1168" y2="1168" x1="1328" />
+        </branch>
+        <branch name="i0c_11">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="1344" type="branch" />
+            <wire x2="1344" y1="1344" y2="1344" x1="1296" />
+            <wire x2="2160" y1="1344" y2="1344" x1="1344" />
+        </branch>
+        <branch name="i1c_10">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1328" y="1472" type="branch" />
+            <wire x2="1328" y1="1472" y2="1472" x1="1296" />
+            <wire x2="2160" y1="1472" y2="1472" x1="1328" />
+        </branch>
+        <branch name="i0d_14">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1360" y="1632" type="branch" />
+            <wire x2="1360" y1="1632" y2="1632" x1="1296" />
+            <wire x2="2160" y1="1632" y2="1632" x1="1360" />
+        </branch>
+        <branch name="i1d_13">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="1760" type="branch" />
+            <wire x2="1344" y1="1760" y2="1760" x1="1296" />
+            <wire x2="2160" y1="1760" y2="1760" x1="1344" />
+        </branch>
+        <iomarker fontsize="28" x="1296" y="752" name="i0a_2" orien="R180" />
+        <iomarker fontsize="28" x="1296" y="880" name="i1a_3" orien="R180" />
+        <iomarker fontsize="28" x="1296" y="1040" name="i0b_5" orien="R180" />
+        <iomarker fontsize="28" x="1296" y="1168" name="i1b_6" orien="R180" />
+        <iomarker fontsize="28" x="1296" y="1344" name="i0c_11" orien="R180" />
+        <iomarker fontsize="28" x="1296" y="1472" name="i1c_10" orien="R180" />
+        <iomarker fontsize="28" x="1296" y="1632" name="i0d_14" orien="R180" />
+        <iomarker fontsize="28" x="1296" y="1760" name="i1d_13" orien="R180" />
+        <text style="fontsize:20;fontname:Arial" x="1344" y="776">1A instead of i0a in TTL book</text>
+        <text style="fontsize:20;fontname:Arial" x="1344" y="900">1B instead of i1a in TTL book</text>
+        <text style="fontsize:20;fontname:Arial" x="1340" y="1056">2A instead of i0a in TTL book</text>
+        <text style="fontsize:20;fontname:Arial" x="1352" y="1184">2B instead of i1b in TTL book</text>
+        <text style="fontsize:20;fontname:Arial" x="1360" y="1368">3A</text>
+        <text style="fontsize:20;fontname:Arial" x="1368" y="1492">3B</text>
+        <text style="fontsize:20;fontname:Arial" x="1368" y="1648">4A</text>
+        <text style="fontsize:20;fontname:Arial" x="1356" y="1780">4B</text>
+        <branch name="Za_4">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3168" y="848" type="branch" />
+            <wire x2="3168" y1="848" y2="848" x1="3072" />
+            <wire x2="3248" y1="848" y2="848" x1="3168" />
+        </branch>
+        <branch name="Zb_7">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3168" y="1136" type="branch" />
+            <wire x2="3168" y1="1136" y2="1136" x1="3072" />
+            <wire x2="3248" y1="1136" y2="1136" x1="3168" />
+        </branch>
+        <branch name="Zc_9">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3168" y="1440" type="branch" />
+            <wire x2="3168" y1="1440" y2="1440" x1="3072" />
+            <wire x2="3232" y1="1440" y2="1440" x1="3168" />
+        </branch>
+        <branch name="Zd_12">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3168" y="1728" type="branch" />
+            <wire x2="3168" y1="1728" y2="1728" x1="3072" />
+            <wire x2="3248" y1="1728" y2="1728" x1="3168" />
+        </branch>
+        <iomarker fontsize="28" x="3248" y="848" name="Za_4" orien="R0" />
+        <iomarker fontsize="28" x="3248" y="1136" name="Zb_7" orien="R0" />
+        <iomarker fontsize="28" x="3232" y="1440" name="Zc_9" orien="R0" />
+        <iomarker fontsize="28" x="3248" y="1728" name="Zd_12" orien="R0" />
+        <text style="fontsize:20;fontname:Arial" x="3140" y="888">1Y in TTL book</text>
+        <text style="fontsize:28;fontname:Arial" x="3160" y="1176">2Y</text>
+        <text style="fontsize:28;fontname:Arial" x="3160" y="1476">3Y</text>
+        <text style="fontsize:28;fontname:Arial" x="3168" y="1756">4Y</text>
+    </sheet>
+</drawing>
\ No newline at end of file
diff --git a/AppleIIGateSch/chip74LS257.sym b/AppleIIGateSch/chip74LS257.sym
new file mode 100644
index 0000000..6299394
--- /dev/null
+++ b/AppleIIGateSch/chip74LS257.sym
@@ -0,0 +1,52 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="chip74LS257">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2018-6-7T7:8:22</timestamp>
+    <pin polarity="Input" x="0" y="-544" name="i0a_2" />
+    <pin polarity="Input" x="0" y="-480" name="i0b_5" />
+    <pin polarity="Input" x="0" y="-416" name="i0c_11" />
+    <pin polarity="Input" x="0" y="-352" name="i0d_14" />
+    <pin polarity="Input" x="0" y="-224" name="i1a_3" />
+    <pin polarity="Input" x="0" y="-160" name="i1b_6" />
+    <pin polarity="Input" x="0" y="-96" name="i1c_10" />
+    <pin polarity="Input" x="0" y="-32" name="i1d_13" />
+    <pin polarity="Input" x="0" y="-288" name="S_1" />
+    <pin polarity="Input" x="384" y="-32" name="En_15" />
+    <pin polarity="Output" x="384" y="-416" name="Za_4" />
+    <pin polarity="Output" x="384" y="-352" name="Zb_7" />
+    <pin polarity="Output" x="384" y="-288" name="Zc_9" />
+    <pin polarity="Output" x="384" y="-224" name="Zd_12" />
+    <graph>
+        <rect width="256" x="64" y="-576" height="576" />
+        <attrtext style="alignment:BCENTER;fontsize:40;fontname:Arial" attrname="SymbolName" x="192" y="-584" type="symbol" />
+        <line x2="0" y1="-544" y2="-544" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-544" type="pin i0a_2" />
+        <line x2="0" y1="-480" y2="-480" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-480" type="pin i0b_5" />
+        <line x2="0" y1="-416" y2="-416" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin i0c_11" />
+        <line x2="0" y1="-352" y2="-352" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin i0d_14" />
+        <line x2="0" y1="-224" y2="-224" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin i1a_3" />
+        <line x2="0" y1="-160" y2="-160" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin i1b_6" />
+        <line x2="0" y1="-96" y2="-96" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin i1c_10" />
+        <line x2="0" y1="-32" y2="-32" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin i1d_13" />
+        <line x2="0" y1="-288" y2="-288" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin S_1" />
+        <line x2="384" y1="-32" y2="-32" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin En_15" />
+        <line x2="384" y1="-416" y2="-416" x1="320" />
+        <line x2="384" y1="-352" y2="-352" x1="320" />
+        <line x2="384" y1="-288" y2="-288" x1="320" />
+        <line x2="384" y1="-224" y2="-224" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin Za_4" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-352" type="pin Zb_7" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin Zc_9" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin Zd_12" />
+        <circle r="10" cx="330" cy="-32" />
+    </graph>
+</symbol>
diff --git a/AppleIIGateSch/chip74LS257_tb.v b/AppleIIGateSch/chip74LS257_tb.v
new file mode 100644
index 0000000..0b5890a
--- /dev/null
+++ b/AppleIIGateSch/chip74LS257_tb.v
@@ -0,0 +1,104 @@
+// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS257.sch - Wed Jun 06 16:37:03 2018
+
+`timescale 1ns / 1ps
+
+module chip74LS257_chip74LS257_sch_tb();
+
+// Inputs
+   reg En_15;
+   reg S_1;
+   reg i0a_2;
+   reg i1a_3;
+   reg i0b_5;
+   reg i1b_6;
+   reg i0c_11;
+   reg i1c_10;
+   reg i0d_14;
+   reg i1d_13;
+
+// Output
+   wire Za_4;
+   wire Zb_7;
+   wire Zc_9;
+   wire Zd_12;
+
+// Bidirs
+  wire expectedA, expectedB, expectedC, expectedD;
+  
+// Instantiate the UUT
+   chip74LS257 UUT (
+		.En_15(En_15), 
+		.S_1(S_1), 
+		.i0a_2(i0a_2), 
+		.i1a_3(i1a_3), 
+		.i0b_5(i0b_5), 
+		.i1b_6(i1b_6), 
+		.i0c_11(i0c_11), 
+		.i1c_10(i1c_10), 
+		.i0d_14(i0d_14), 
+		.i1d_13(i1d_13), 
+		.Za_4(Za_4), 
+		.Zb_7(Zb_7), 
+		.Zc_9(Zc_9), 
+		.Zd_12(Zd_12)
+   );
+   
+// Test Sim
+  integer i, errct;
+  assign expectedA = En_15 ?  1'bx : (S_1 ? i1a_3  : i0a_2 );
+  assign expectedB = En_15 ?  1'bx : (S_1 ? i1b_6  : i0b_5 );
+  assign expectedC = En_15 ?  1'bx : (S_1 ? i1c_10 : i0c_11);
+  assign expectedD = En_15 ?  1'bx : (S_1 ? i1d_13 : i0d_14);
+   
+// Initialize Inputs
+  `ifdef auto_init
+    initial begin
+      $display("auto_init defined");
+    end
+  `else
+    initial begin
+      $display("auto_init not defined");
+    end
+  `endif
+  initial begin
+		En_15 = 0;
+		S_1 = 0;
+		i0a_2 = 0;
+		i1a_3 = 0;
+		i0b_5 = 0;
+		i1b_6 = 0;
+		i0c_11 = 0;
+		i1c_10 = 0;
+		i0d_14 = 0;
+		i1d_13 = 0;
+    errct  = 0;
+    #100;
+    for (i=0; i<1024; i=i+1) begin
+      {En_15, S_1, i1d_13,i1c_10,i1b_6,i1a_3, i0d_14,i0c_11,i0b_5,i0a_2} = i;
+      #9;
+      if ( Za_4 != expectedA ) begin 
+        $display("i:%d  Za_4=%b  expectedA=%b",  i, Za_4, expectedA);
+        errct = errct + 1;
+      end
+      if ( Zb_7 != expectedB ) begin 
+        $display("i:%d  Zb_7=%b  expectedB=%b",  i, Zb_7, expectedB);
+        errct = errct + 1;
+      end
+      if ( Zc_9 != expectedC ) begin 
+        $display("i:%d  Zc_9=%b  expectedA=%b",  i, Zc_9, expectedC);
+        errct = errct + 1;
+      end
+      if ( Zd_12 != expectedD ) begin 
+        $display("i:%d  Zd_12=%b  expectedD=%b", i, Zd_12, expectedD);
+        errct = errct + 1;
+      end      
+      #1;
+    end
+    if ( errct==0 ) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED errct=%d", errct);
+    end
+    $finish;
+  end
+endmodule
diff --git a/AppleIIGateSch/chip74S195.cmd_log b/AppleIIGateSch/chip74S195.cmd_log
new file mode 100644
index 0000000..309d811
--- /dev/null
+++ b/AppleIIGateSch/chip74S195.cmd_log
@@ -0,0 +1 @@
+sch2hdl -intstyle ise -family spartan3e -verilog chip74S195.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74S195.sch 
diff --git a/AppleIIGateSch/chip74S195.jhd b/AppleIIGateSch/chip74S195.jhd
new file mode 100644
index 0000000..754adb2
--- /dev/null
+++ b/AppleIIGateSch/chip74S195.jhd
@@ -0,0 +1 @@
+MODULE chip74S195
diff --git a/AppleIIGateSch/chip74S195.sch b/AppleIIGateSch/chip74S195.sch
new file mode 100644
index 0000000..e3a2de5
--- /dev/null
+++ b/AppleIIGateSch/chip74S195.sch
@@ -0,0 +1,547 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+    <attr value="spartan3e" name="DeviceFamilyName">
+        <trait delete="all:0" />
+        <trait editname="all:0" />
+        <trait edittrait="all:0" />
+    </attr>
+    <netlist>
+        <signal name="XLXN_3" />
+        <signal name="CLRn_1" />
+        <signal name="XLXN_9" />
+        <signal name="XLXN_11" />
+        <signal name="XLXN_12" />
+        <signal name="XLXN_13" />
+        <signal name="CP_10" />
+        <signal name="XLXN_17" />
+        <signal name="XLXN_19" />
+        <signal name="XLXN_20" />
+        <signal name="XLXN_21" />
+        <signal name="XLXN_22" />
+        <signal name="XLXN_23" />
+        <signal name="XLXN_24" />
+        <signal name="XLXN_25" />
+        <signal name="XLXN_26" />
+        <signal name="XLXN_27" />
+        <signal name="XLXN_28" />
+        <signal name="XLXN_29" />
+        <signal name="XLXN_30" />
+        <signal name="XLXN_32" />
+        <signal name="SH_LDn" />
+        <signal name="XLXN_37" />
+        <signal name="XLXN_38" />
+        <signal name="Q0_15" />
+        <signal name="J_2" />
+        <signal name="K_3" />
+        <signal name="XLXN_49" />
+        <signal name="P0_4" />
+        <signal name="P1_5" />
+        <signal name="P2_6" />
+        <signal name="P3_7" />
+        <signal name="Q1_14" />
+        <signal name="Q2_13" />
+        <signal name="Q3_12" />
+        <signal name="Q3n_11" />
+        <port polarity="Input" name="CLRn_1" />
+        <port polarity="Input" name="CP_10" />
+        <port polarity="Input" name="SH_LDn" />
+        <port polarity="Output" name="Q0_15" />
+        <port polarity="Input" name="J_2" />
+        <port polarity="Input" name="K_3" />
+        <port polarity="Input" name="P0_4" />
+        <port polarity="Input" name="P1_5" />
+        <port polarity="Input" name="P2_6" />
+        <port polarity="Input" name="P3_7" />
+        <port polarity="Output" name="Q1_14" />
+        <port polarity="Output" name="Q2_13" />
+        <port polarity="Output" name="Q3_12" />
+        <port polarity="Output" name="Q3n_11" />
+        <blockdef name="fjkc">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="64" y1="-320" y2="-320" x1="0" />
+            <line x2="320" y1="-256" y2="-256" x1="384" />
+            <line x2="64" y1="-256" y2="-256" x1="0" />
+            <line x2="64" y1="-32" y2="-32" x1="192" />
+            <line x2="192" y1="-64" y2="-32" x1="192" />
+            <line x2="64" y1="-128" y2="-144" x1="80" />
+            <line x2="80" y1="-112" y2="-128" x1="64" />
+            <rect width="256" x="64" y="-384" height="320" />
+        </blockdef>
+        <blockdef name="inv">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="160" y1="-32" y2="-32" x1="224" />
+            <line x2="128" y1="-64" y2="-32" x1="64" />
+            <line x2="64" y1="-32" y2="0" x1="128" />
+            <line x2="64" y1="0" y2="-64" x1="64" />
+            <circle r="16" cx="144" cy="-32" />
+        </blockdef>
+        <blockdef name="nor3">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="48" y1="-64" y2="-64" x1="0" />
+            <line x2="72" y1="-128" y2="-128" x1="0" />
+            <line x2="48" y1="-192" y2="-192" x1="0" />
+            <line x2="216" y1="-128" y2="-128" x1="256" />
+            <circle r="12" cx="204" cy="-128" />
+            <line x2="48" y1="-64" y2="-80" x1="48" />
+            <line x2="48" y1="-192" y2="-176" x1="48" />
+            <line x2="48" y1="-80" y2="-80" x1="112" />
+            <line x2="48" y1="-176" y2="-176" x1="112" />
+            <arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
+            <arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
+            <arc ex="112" ey="-176" sx="192" sy="-128" r="88" cx="116" cy="-88" />
+        </blockdef>
+        <blockdef name="and3">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="192" y1="-128" y2="-128" x1="256" />
+            <line x2="144" y1="-176" y2="-176" x1="64" />
+            <line x2="64" y1="-80" y2="-80" x1="144" />
+            <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+            <line x2="64" y1="-64" y2="-192" x1="64" />
+        </blockdef>
+        <blockdef name="and2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="192" y1="-96" y2="-96" x1="256" />
+            <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+            <line x2="64" y1="-48" y2="-48" x1="144" />
+            <line x2="144" y1="-144" y2="-144" x1="64" />
+            <line x2="64" y1="-48" y2="-144" x1="64" />
+        </blockdef>
+        <blockdef name="nor2">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="216" y1="-96" y2="-96" x1="256" />
+            <circle r="12" cx="204" cy="-96" />
+            <arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
+            <arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
+            <arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
+            <line x2="48" y1="-48" y2="-48" x1="112" />
+            <line x2="48" y1="-144" y2="-144" x1="112" />
+        </blockdef>
+        <block symbolname="fjkc" name="XLXI_6">
+            <blockpin signalname="XLXN_17" name="C" />
+            <blockpin signalname="XLXN_3" name="CLR" />
+            <blockpin signalname="XLXN_27" name="J" />
+            <blockpin signalname="XLXN_28" name="K" />
+            <blockpin signalname="Q3_12" name="Q" />
+        </block>
+        <block symbolname="fjkc" name="XLXI_17">
+            <blockpin signalname="XLXN_17" name="C" />
+            <blockpin signalname="XLXN_3" name="CLR" />
+            <blockpin signalname="XLXN_23" name="J" />
+            <blockpin signalname="XLXN_24" name="K" />
+            <blockpin signalname="Q2_13" name="Q" />
+        </block>
+        <block symbolname="fjkc" name="XLXI_18">
+            <blockpin signalname="XLXN_17" name="C" />
+            <blockpin signalname="XLXN_3" name="CLR" />
+            <blockpin signalname="XLXN_9" name="J" />
+            <blockpin signalname="XLXN_38" name="K" />
+            <blockpin signalname="Q0_15" name="Q" />
+        </block>
+        <block symbolname="fjkc" name="XLXI_19">
+            <blockpin signalname="XLXN_17" name="C" />
+            <blockpin signalname="XLXN_3" name="CLR" />
+            <blockpin signalname="XLXN_19" name="J" />
+            <blockpin signalname="XLXN_20" name="K" />
+            <blockpin signalname="Q1_14" name="Q" />
+        </block>
+        <block symbolname="inv" name="XLXI_21">
+            <blockpin signalname="CLRn_1" name="I" />
+            <blockpin signalname="XLXN_3" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_22">
+            <blockpin signalname="XLXN_38" name="I" />
+            <blockpin signalname="XLXN_9" name="O" />
+        </block>
+        <block symbolname="nor3" name="XLXI_23">
+            <blockpin signalname="XLXN_13" name="I0" />
+            <blockpin signalname="XLXN_12" name="I1" />
+            <blockpin signalname="XLXN_11" name="I2" />
+            <blockpin signalname="XLXN_38" name="O" />
+        </block>
+        <block symbolname="and3" name="XLXI_24">
+            <blockpin signalname="XLXN_32" name="I0" />
+            <blockpin signalname="K_3" name="I1" />
+            <blockpin signalname="Q0_15" name="I2" />
+            <blockpin signalname="XLXN_12" name="O" />
+        </block>
+        <block symbolname="and3" name="XLXI_25">
+            <blockpin signalname="XLXN_37" name="I0" />
+            <blockpin signalname="J_2" name="I1" />
+            <blockpin signalname="XLXN_32" name="I2" />
+            <blockpin signalname="XLXN_13" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_26">
+            <blockpin signalname="XLXN_49" name="I0" />
+            <blockpin signalname="P0_4" name="I1" />
+            <blockpin signalname="XLXN_11" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_27">
+            <blockpin signalname="CP_10" name="I0" />
+            <blockpin signalname="CLRn_1" name="I1" />
+            <blockpin signalname="XLXN_17" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_28">
+            <blockpin signalname="XLXN_20" name="I" />
+            <blockpin signalname="XLXN_19" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_30">
+            <blockpin signalname="XLXN_49" name="I0" />
+            <blockpin signalname="P1_5" name="I1" />
+            <blockpin signalname="XLXN_22" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_31">
+            <blockpin signalname="Q0_15" name="I0" />
+            <blockpin signalname="XLXN_32" name="I1" />
+            <blockpin signalname="XLXN_21" name="O" />
+        </block>
+        <block symbolname="nor2" name="XLXI_32">
+            <blockpin signalname="XLXN_21" name="I0" />
+            <blockpin signalname="XLXN_22" name="I1" />
+            <blockpin signalname="XLXN_20" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_33">
+            <blockpin signalname="XLXN_24" name="I" />
+            <blockpin signalname="XLXN_23" name="O" />
+        </block>
+        <block symbolname="nor2" name="XLXI_34">
+            <blockpin signalname="XLXN_26" name="I0" />
+            <blockpin signalname="XLXN_25" name="I1" />
+            <blockpin signalname="XLXN_24" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_35">
+            <blockpin signalname="Q1_14" name="I0" />
+            <blockpin signalname="XLXN_32" name="I1" />
+            <blockpin signalname="XLXN_26" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_36">
+            <blockpin signalname="XLXN_49" name="I0" />
+            <blockpin signalname="P2_6" name="I1" />
+            <blockpin signalname="XLXN_25" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_37">
+            <blockpin signalname="Q2_13" name="I0" />
+            <blockpin signalname="XLXN_32" name="I1" />
+            <blockpin signalname="XLXN_30" name="O" />
+        </block>
+        <block symbolname="and2" name="XLXI_38">
+            <blockpin signalname="XLXN_49" name="I0" />
+            <blockpin signalname="P3_7" name="I1" />
+            <blockpin signalname="XLXN_29" name="O" />
+        </block>
+        <block symbolname="nor2" name="XLXI_39">
+            <blockpin signalname="XLXN_30" name="I0" />
+            <blockpin signalname="XLXN_29" name="I1" />
+            <blockpin signalname="XLXN_28" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_40">
+            <blockpin signalname="XLXN_28" name="I" />
+            <blockpin signalname="XLXN_27" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_41">
+            <blockpin signalname="XLXN_49" name="I" />
+            <blockpin signalname="XLXN_32" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_42">
+            <blockpin signalname="SH_LDn" name="I" />
+            <blockpin signalname="XLXN_49" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_43">
+            <blockpin signalname="Q0_15" name="I" />
+            <blockpin signalname="XLXN_37" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_44">
+            <blockpin signalname="Q3_12" name="I" />
+            <blockpin signalname="Q3n_11" name="O" />
+        </block>
+    </netlist>
+    <sheet sheetnum="1" width="3520" height="2720">
+        <instance x="2720" y="528" name="XLXI_6" orien="R270" />
+        <instance x="2720" y="1136" name="XLXI_17" orien="R270" />
+        <instance x="2720" y="1696" name="XLXI_19" orien="R270" />
+        <instance x="2720" y="2256" name="XLXI_18" orien="R270" />
+        <instance x="2832" y="2592" name="XLXI_21" orien="R270" />
+        <branch name="XLXN_3">
+            <wire x2="2800" y1="528" y2="528" x1="2688" />
+            <wire x2="2800" y1="528" y2="1136" x1="2800" />
+            <wire x2="2800" y1="1136" y2="1696" x1="2800" />
+            <wire x2="2800" y1="1696" y2="2256" x1="2800" />
+            <wire x2="2800" y1="2256" y2="2368" x1="2800" />
+            <wire x2="2800" y1="1136" y2="1136" x1="2688" />
+            <wire x2="2800" y1="1696" y2="1696" x1="2688" />
+            <wire x2="2800" y1="2256" y2="2256" x1="2688" />
+        </branch>
+        <branch name="CLRn_1">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2736" y="2656" type="branch" />
+            <wire x2="2736" y1="2656" y2="2656" x1="2672" />
+            <wire x2="2800" y1="2656" y2="2656" x1="2736" />
+            <wire x2="2800" y1="2592" y2="2608" x1="2800" />
+            <wire x2="2912" y1="2608" y2="2608" x1="2800" />
+            <wire x2="2800" y1="2608" y2="2656" x1="2800" />
+            <wire x2="2912" y1="2560" y2="2608" x1="2912" />
+        </branch>
+        <instance x="2064" y="2336" name="XLXI_22" orien="R0" />
+        <branch name="XLXN_9">
+            <wire x2="2400" y1="2304" y2="2304" x1="2288" />
+            <wire x2="2400" y1="2256" y2="2304" x1="2400" />
+        </branch>
+        <instance x="1456" y="2432" name="XLXI_23" orien="R0" />
+        <instance x="1056" y="2432" name="XLXI_24" orien="R0" />
+        <instance x="1056" y="2624" name="XLXI_25" orien="R0" />
+        <instance x="1056" y="2240" name="XLXI_26" orien="R0" />
+        <branch name="XLXN_11">
+            <wire x2="1456" y1="2144" y2="2144" x1="1312" />
+            <wire x2="1456" y1="2144" y2="2240" x1="1456" />
+        </branch>
+        <branch name="XLXN_12">
+            <wire x2="1456" y1="2304" y2="2304" x1="1312" />
+        </branch>
+        <branch name="XLXN_13">
+            <wire x2="1456" y1="2496" y2="2496" x1="1312" />
+            <wire x2="1456" y1="2368" y2="2496" x1="1456" />
+        </branch>
+        <instance x="3040" y="2560" name="XLXI_27" orien="R270" />
+        <branch name="CP_10">
+            <attrtext style="alignment:SOFT-TCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2976" y="2688" type="branch" />
+            <wire x2="2976" y1="2688" y2="2688" x1="2944" />
+            <wire x2="2976" y1="2560" y2="2688" x1="2976" />
+        </branch>
+        <branch name="XLXN_17">
+            <wire x2="2592" y1="528" y2="576" x1="2592" />
+            <wire x2="2944" y1="576" y2="576" x1="2592" />
+            <wire x2="2944" y1="576" y2="1200" x1="2944" />
+            <wire x2="2944" y1="1200" y2="1776" x1="2944" />
+            <wire x2="2944" y1="1776" y2="2288" x1="2944" />
+            <wire x2="2944" y1="2288" y2="2304" x1="2944" />
+            <wire x2="2592" y1="1136" y2="1200" x1="2592" />
+            <wire x2="2944" y1="1200" y2="1200" x1="2592" />
+            <wire x2="2592" y1="1696" y2="1776" x1="2592" />
+            <wire x2="2944" y1="1776" y2="1776" x1="2592" />
+            <wire x2="2592" y1="2256" y2="2288" x1="2592" />
+            <wire x2="2944" y1="2288" y2="2288" x1="2592" />
+        </branch>
+        <branch name="XLXN_19">
+            <wire x2="2400" y1="1728" y2="1728" x1="2288" />
+            <wire x2="2400" y1="1696" y2="1728" x1="2400" />
+        </branch>
+        <instance x="1056" y="1760" name="XLXI_30" orien="R0" />
+        <instance x="2064" y="1216" name="XLXI_33" orien="R0" />
+        <branch name="XLXN_23">
+            <wire x2="2400" y1="1184" y2="1184" x1="2288" />
+            <wire x2="2400" y1="1136" y2="1184" x1="2400" />
+        </branch>
+        <instance x="1472" y="1280" name="XLXI_34" orien="R0" />
+        <branch name="XLXN_24">
+            <wire x2="1984" y1="1184" y2="1184" x1="1728" />
+            <wire x2="2064" y1="1184" y2="1184" x1="1984" />
+            <wire x2="1984" y1="1184" y2="1232" x1="1984" />
+            <wire x2="2464" y1="1232" y2="1232" x1="1984" />
+            <wire x2="2464" y1="1136" y2="1232" x1="2464" />
+        </branch>
+        <instance x="1072" y="1360" name="XLXI_35" orien="R0" />
+        <instance x="1072" y="1200" name="XLXI_36" orien="R0" />
+        <branch name="XLXN_25">
+            <wire x2="1392" y1="1104" y2="1104" x1="1328" />
+            <wire x2="1392" y1="1104" y2="1152" x1="1392" />
+            <wire x2="1472" y1="1152" y2="1152" x1="1392" />
+        </branch>
+        <branch name="XLXN_26">
+            <wire x2="1392" y1="1264" y2="1264" x1="1328" />
+            <wire x2="1392" y1="1216" y2="1264" x1="1392" />
+            <wire x2="1472" y1="1216" y2="1216" x1="1392" />
+        </branch>
+        <instance x="1072" y="736" name="XLXI_37" orien="R0" />
+        <instance x="1072" y="576" name="XLXI_38" orien="R0" />
+        <instance x="1456" y="656" name="XLXI_39" orien="R0" />
+        <instance x="2080" y="592" name="XLXI_40" orien="R0" />
+        <branch name="XLXN_27">
+            <wire x2="2400" y1="560" y2="560" x1="2304" />
+            <wire x2="2400" y1="528" y2="560" x1="2400" />
+        </branch>
+        <branch name="XLXN_28">
+            <wire x2="1984" y1="560" y2="560" x1="1712" />
+            <wire x2="2080" y1="560" y2="560" x1="1984" />
+            <wire x2="1984" y1="560" y2="608" x1="1984" />
+            <wire x2="2464" y1="608" y2="608" x1="1984" />
+            <wire x2="2464" y1="528" y2="608" x1="2464" />
+        </branch>
+        <branch name="XLXN_29">
+            <wire x2="1392" y1="480" y2="480" x1="1328" />
+            <wire x2="1392" y1="480" y2="528" x1="1392" />
+            <wire x2="1456" y1="528" y2="528" x1="1392" />
+        </branch>
+        <branch name="XLXN_30">
+            <wire x2="1392" y1="640" y2="640" x1="1328" />
+            <wire x2="1392" y1="592" y2="640" x1="1392" />
+            <wire x2="1456" y1="592" y2="592" x1="1392" />
+        </branch>
+        <branch name="XLXN_32">
+            <wire x2="944" y1="2592" y2="2592" x1="848" />
+            <wire x2="1072" y1="608" y2="608" x1="944" />
+            <wire x2="944" y1="608" y2="1232" x1="944" />
+            <wire x2="1072" y1="1232" y2="1232" x1="944" />
+            <wire x2="944" y1="1232" y2="1760" x1="944" />
+            <wire x2="944" y1="1760" y2="2368" x1="944" />
+            <wire x2="944" y1="2368" y2="2432" x1="944" />
+            <wire x2="1056" y1="2432" y2="2432" x1="944" />
+            <wire x2="944" y1="2432" y2="2592" x1="944" />
+            <wire x2="1056" y1="2368" y2="2368" x1="944" />
+            <wire x2="1056" y1="1760" y2="1760" x1="944" />
+        </branch>
+        <instance x="624" y="2624" name="XLXI_41" orien="R0" />
+        <instance x="352" y="2688" name="XLXI_42" orien="R0" />
+        <branch name="SH_LDn">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="320" y="2656" type="branch" />
+            <wire x2="320" y1="2656" y2="2656" x1="304" />
+            <wire x2="352" y1="2656" y2="2656" x1="320" />
+        </branch>
+        <iomarker fontsize="28" x="304" y="2656" name="SH_LDn" orien="R180" />
+        <branch name="XLXN_38">
+            <wire x2="2000" y1="2304" y2="2304" x1="1712" />
+            <wire x2="2064" y1="2304" y2="2304" x1="2000" />
+            <wire x2="2000" y1="2304" y2="2352" x1="2000" />
+            <wire x2="2464" y1="2352" y2="2352" x1="2000" />
+            <wire x2="2464" y1="2256" y2="2352" x1="2464" />
+        </branch>
+        <instance x="2064" y="1760" name="XLXI_28" orien="R0" />
+        <instance x="1456" y="1824" name="XLXI_32" orien="R0" />
+        <branch name="XLXN_22">
+            <wire x2="1328" y1="1664" y2="1664" x1="1312" />
+            <wire x2="1328" y1="1664" y2="1696" x1="1328" />
+            <wire x2="1456" y1="1696" y2="1696" x1="1328" />
+        </branch>
+        <branch name="XLXN_21">
+            <wire x2="1328" y1="1792" y2="1792" x1="1312" />
+            <wire x2="1328" y1="1760" y2="1792" x1="1328" />
+            <wire x2="1456" y1="1760" y2="1760" x1="1328" />
+        </branch>
+        <branch name="XLXN_20">
+            <wire x2="1984" y1="1728" y2="1728" x1="1712" />
+            <wire x2="2064" y1="1728" y2="1728" x1="1984" />
+            <wire x2="1984" y1="1728" y2="1776" x1="1984" />
+            <wire x2="2464" y1="1776" y2="1776" x1="1984" />
+            <wire x2="2464" y1="1696" y2="1776" x1="2464" />
+        </branch>
+        <instance x="1056" y="1888" name="XLXI_31" orien="R0" />
+        <instance x="1856" y="2032" name="XLXI_43" orien="R90" />
+        <branch name="XLXN_37">
+            <wire x2="1056" y1="2560" y2="2608" x1="1056" />
+            <wire x2="1888" y1="2608" y2="2608" x1="1056" />
+            <wire x2="1888" y1="2256" y2="2608" x1="1888" />
+        </branch>
+        <branch name="Q0_15">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3008" y="1856" type="branch" />
+            <wire x2="1056" y1="1824" y2="1824" x1="1024" />
+            <wire x2="1024" y1="1824" y2="1856" x1="1024" />
+            <wire x2="1888" y1="1856" y2="1856" x1="1024" />
+            <wire x2="2464" y1="1856" y2="1856" x1="1888" />
+            <wire x2="2464" y1="1856" y2="1872" x1="2464" />
+            <wire x2="3008" y1="1856" y2="1856" x1="2464" />
+            <wire x2="3120" y1="1856" y2="1856" x1="3008" />
+            <wire x2="1888" y1="1856" y2="2032" x1="1888" />
+            <wire x2="1024" y1="1856" y2="2240" x1="1024" />
+            <wire x2="1056" y1="2240" y2="2240" x1="1024" />
+        </branch>
+        <branch name="J_2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2496" type="branch" />
+            <wire x2="448" y1="2496" y2="2496" x1="384" />
+            <wire x2="1056" y1="2496" y2="2496" x1="448" />
+        </branch>
+        <branch name="K_3">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2304" type="branch" />
+            <wire x2="448" y1="2304" y2="2304" x1="384" />
+            <wire x2="1056" y1="2304" y2="2304" x1="448" />
+        </branch>
+        <iomarker fontsize="28" x="384" y="2304" name="K_3" orien="R180" />
+        <iomarker fontsize="28" x="384" y="2496" name="J_2" orien="R180" />
+        <branch name="XLXN_49">
+            <wire x2="592" y1="2656" y2="2656" x1="576" />
+            <wire x2="1072" y1="512" y2="512" x1="592" />
+            <wire x2="592" y1="512" y2="1136" x1="592" />
+            <wire x2="592" y1="1136" y2="1696" x1="592" />
+            <wire x2="592" y1="1696" y2="2176" x1="592" />
+            <wire x2="592" y1="2176" y2="2592" x1="592" />
+            <wire x2="592" y1="2592" y2="2656" x1="592" />
+            <wire x2="624" y1="2592" y2="2592" x1="592" />
+            <wire x2="1056" y1="2176" y2="2176" x1="592" />
+            <wire x2="1056" y1="1696" y2="1696" x1="592" />
+            <wire x2="1072" y1="1136" y2="1136" x1="592" />
+        </branch>
+        <branch name="P0_4">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="464" y="2112" type="branch" />
+            <wire x2="464" y1="2112" y2="2112" x1="384" />
+            <wire x2="1056" y1="2112" y2="2112" x1="464" />
+        </branch>
+        <iomarker fontsize="28" x="384" y="2112" name="P0_4" orien="R180" />
+        <branch name="P1_5">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="1632" type="branch" />
+            <wire x2="448" y1="1632" y2="1632" x1="384" />
+            <wire x2="1056" y1="1632" y2="1632" x1="448" />
+        </branch>
+        <iomarker fontsize="28" x="384" y="1632" name="P1_5" orien="R180" />
+        <branch name="P2_6">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="464" y="1072" type="branch" />
+            <wire x2="464" y1="1072" y2="1072" x1="384" />
+            <wire x2="1072" y1="1072" y2="1072" x1="464" />
+        </branch>
+        <branch name="P3_7">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="480" y="448" type="branch" />
+            <wire x2="480" y1="448" y2="448" x1="400" />
+            <wire x2="1072" y1="448" y2="448" x1="480" />
+        </branch>
+        <iomarker fontsize="28" x="400" y="448" name="P3_7" orien="R180" />
+        <iomarker fontsize="28" x="384" y="1072" name="P2_6" orien="R180" />
+        <branch name="Q1_14">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3024" y="1296" type="branch" />
+            <wire x2="1072" y1="1296" y2="1296" x1="1056" />
+            <wire x2="1056" y1="1296" y2="1344" x1="1056" />
+            <wire x2="1504" y1="1344" y2="1344" x1="1056" />
+            <wire x2="2464" y1="1296" y2="1296" x1="1504" />
+            <wire x2="2464" y1="1296" y2="1312" x1="2464" />
+            <wire x2="3024" y1="1296" y2="1296" x1="2464" />
+            <wire x2="3120" y1="1296" y2="1296" x1="3024" />
+            <wire x2="1504" y1="1296" y2="1344" x1="1504" />
+        </branch>
+        <branch name="Q2_13">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3024" y="736" type="branch" />
+            <wire x2="1072" y1="672" y2="672" x1="1056" />
+            <wire x2="1056" y1="672" y2="736" x1="1056" />
+            <wire x2="2464" y1="736" y2="736" x1="1056" />
+            <wire x2="2464" y1="736" y2="752" x1="2464" />
+            <wire x2="3024" y1="736" y2="736" x1="2464" />
+            <wire x2="3104" y1="736" y2="736" x1="3024" />
+        </branch>
+        <branch name="Q3_12">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3040" y="112" type="branch" />
+            <wire x2="2464" y1="112" y2="144" x1="2464" />
+            <wire x2="2720" y1="112" y2="112" x1="2464" />
+            <wire x2="3040" y1="112" y2="112" x1="2720" />
+            <wire x2="3104" y1="112" y2="112" x1="3040" />
+            <wire x2="2720" y1="112" y2="224" x1="2720" />
+            <wire x2="2784" y1="224" y2="224" x1="2720" />
+        </branch>
+        <instance x="2784" y="256" name="XLXI_44" orien="R0" />
+        <branch name="Q3n_11">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3024" y="224" type="branch" />
+            <wire x2="3024" y1="224" y2="224" x1="3008" />
+            <wire x2="3104" y1="224" y2="224" x1="3024" />
+        </branch>
+        <iomarker fontsize="28" x="3104" y="224" name="Q3n_11" orien="R0" />
+        <iomarker fontsize="28" x="3104" y="112" name="Q3_12" orien="R0" />
+        <iomarker fontsize="28" x="3104" y="736" name="Q2_13" orien="R0" />
+        <iomarker fontsize="28" x="3120" y="1296" name="Q1_14" orien="R0" />
+        <iomarker fontsize="28" x="3120" y="1856" name="Q0_15" orien="R0" />
+        <iomarker fontsize="28" x="2672" y="2656" name="CLRn_1" orien="R180" />
+        <iomarker fontsize="28" x="2944" y="2688" name="CP_10" orien="R180" />
+        <text style="fontsize:52;fontname:Arial" x="332" y="68">FWK 20180530</text>
+    </sheet>
+</drawing>
\ No newline at end of file
diff --git a/AppleIIGateSch/chip74S195.sym b/AppleIIGateSch/chip74S195.sym
new file mode 100644
index 0000000..f93ecdf
--- /dev/null
+++ b/AppleIIGateSch/chip74S195.sym
@@ -0,0 +1,56 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="chip74S195">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2018-6-3T18:32:16</timestamp>
+    <pin polarity="Input" x="384" y="-96" name="CLRn_1" />
+    <pin polarity="Input" x="0" y="-96" name="CP_10" />
+    <pin polarity="Input" x="0" y="-32" name="J_2" />
+    <pin polarity="Input" x="384" y="-32" name="K_3" />
+    <pin polarity="Input" x="0" y="-288" name="P0_4" />
+    <pin polarity="Input" x="0" y="-352" name="P1_5" />
+    <pin polarity="Input" x="0" y="-416" name="P2_6" />
+    <pin polarity="Input" x="0" y="-480" name="P3_7" />
+    <pin polarity="Output" x="384" y="-224" name="Q0_15" />
+    <pin polarity="Output" x="384" y="-288" name="Q1_14" />
+    <pin polarity="Output" x="384" y="-352" name="Q2_13" />
+    <pin polarity="Output" x="384" y="-480" name="Q3n_11" />
+    <pin polarity="Output" x="384" y="-416" name="Q3_12" />
+    <pin polarity="Input" x="0" y="-224" name="SH_LDn" />
+    <graph>
+        <rect width="256" x="64" y="-512" height="512" />
+        <attrtext style="alignment:BCENTER;fontsize:40;fontname:Arial" attrname="SymbolName" x="192" y="-520" type="symbol" />
+        <line x2="384" y1="-96" y2="-96" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin CLRn_1" />
+        <line x2="0" y1="-96" y2="-96" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin CP_10" />
+        <line x2="0" y1="-32" y2="-32" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin J_2" />
+        <line x2="384" y1="-32" y2="-32" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin K_3" />
+        <line x2="0" y1="-288" y2="-288" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin P0_4" />
+        <line x2="0" y1="-352" y2="-352" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin P1_5" />
+        <line x2="0" y1="-416" y2="-416" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin P2_6" />
+        <line x2="0" y1="-480" y2="-480" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-480" type="pin P3_7" />
+        <line x2="384" y1="-224" y2="-224" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin Q0_15" />
+        <line x2="384" y1="-288" y2="-288" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin Q1_14" />
+        <line x2="384" y1="-352" y2="-352" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-352" type="pin Q2_13" />
+        <line x2="384" y1="-480" y2="-480" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-480" type="pin Q3n_11" />
+        <line x2="384" y1="-416" y2="-416" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin Q3_12" />
+        <line x2="0" y1="-224" y2="-224" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin SH_LDn" />
+        <text style="fontsize:32;fontname:Arial" x="72" y="-196">PE</text>
+        <circle r="12" cx="56" cy="-224" />
+        <circle r="12" cx="332" cy="-98" />
+        <circle r="12" cx="332" cy="-34" />
+        <circle r="12" cx="332" cy="-482" />
+    </graph>
+</symbol>
diff --git a/AppleIIGateSch/chip74S195_tb.v b/AppleIIGateSch/chip74S195_tb.v
new file mode 100644
index 0000000..bbfc53f
--- /dev/null
+++ b/AppleIIGateSch/chip74S195_tb.v
@@ -0,0 +1,108 @@
+// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74S195.sch - Wed May 30 20:53:58 2018
+
+`timescale 1ns / 1ps
+
+module chip74S195_chip74S195_sch_tb();
+
+// Inputs
+   reg CLRn_1;
+   reg CP_10;
+   reg SH_LDn;
+   reg J_2;
+   reg K_3;
+   reg P0_4;
+   reg P1_5;
+   reg P2_6;
+   reg P3_7;
+
+// Output
+   wire Q0_15;
+   wire Q1_14;
+   wire Q2_13;
+   wire Q3_12;
+   wire Q3n_11;
+
+// Bidirs
+
+// simulation vars
+  integer i, errct;
+  wire [4:0] qbus = {Q3n_11,Q3_12,Q2_13,Q1_14,Q0_15};
+  wire [4:0] pbus = {~P3_7,P3_7,P2_6,P1_5,P0_4};
+
+// Instantiate the UUT
+   chip74S195 UUT (
+		.CLRn_1(CLRn_1), 
+		.CP_10(CP_10), 
+		.SH_LDn(SH_LDn), 
+		.J_2(J_2), 
+		.K_3(K_3), 
+		.P0_4(P0_4), 
+		.P1_5(P1_5), 
+		.P2_6(P2_6), 
+		.P3_7(P3_7), 
+		.Q0_15(Q0_15), 
+		.Q1_14(Q1_14), 
+		.Q2_13(Q2_13), 
+		.Q3_12(Q3_12), 
+		.Q3n_11(Q3n_11)
+   );
+// Initialize Inputs
+  `ifdef auto_init
+    initial begin
+      $display("auto_init defined");
+    end
+  `else
+    initial begin
+      $display("not defined auto_init");
+    end
+  `endif
+    initial begin
+		  CLRn_1 = 0;
+		  CP_10 = 0;
+		  SH_LDn = 0;
+		  J_2 = 0;
+		  K_3 = 0;
+		  P0_4 = 0;
+		  P1_5 = 0;
+		  P2_6 = 0;
+		  P3_7 = 0;
+      errct = 0;
+      #105
+      CLRn_1 = 1;
+      #5
+      for (i=0; i<16; i=i+1) begin
+        {P3_7,P2_6,P1_5,P0_4} = i[3:0];
+        CP_10 = 0;
+        #5
+        CP_10 = 1;
+        #5;
+        if ( qbus!= pbus ) begin
+          errct = errct + 1;
+          $display("ERROR: qbus=%b != pbus=%b", qbus, pbus);
+        end
+      end
+      #5;
+      SH_LDn = 1;
+      K_3 = 1;
+      #5;
+      // Test shifting in bits. Not used in APPLE II.
+      for (i=0; i<16; i=i+1) begin
+        if ( i[1:0]==0 ) begin
+          J_2 = 0; K_3 = 1;
+        end else begin
+          J_2 = 1; K_3 = 0;
+        end
+        CP_10 = 0;
+        #5
+        CP_10 = 1;
+        #5;      
+      end
+      #10;
+      if (errct == 0) begin
+        $display("PASSED");
+      end else begin
+        $display("FAILED  errct=%d", errct);
+      end
+      $finish;
+    end
+endmodule
diff --git a/AppleIIGateSch/chipi74LS153.cmd_log b/AppleIIGateSch/chipi74LS153.cmd_log
new file mode 100644
index 0000000..770146b
--- /dev/null
+++ b/AppleIIGateSch/chipi74LS153.cmd_log
@@ -0,0 +1,7 @@
+sch2hdl -intstyle ise -family spartan3e -verilog chipi74LS153.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch 
+sch2sym -intstyle ise -family spartan3e -refsym chipi74LS153 C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sym 
+sch2hdl -intstyle ise -family spartan3e -verilog chipi74LS153_drc.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch 
+sch2hdl -intstyle ise -family spartan3e -verilog chipi74LS153_drc.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch 
+sch2hdl -intstyle ise -family spartan3e -verilog chipi74LS153.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch 
+sch2hdl -intstyle ise -family spartan3e -verilog chipi74LS153_drc.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch 
+sch2verilog -intstyle ise -family spartan3e -tionly {} -tiext tfi -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch chipi74LS153.tfi 
diff --git a/AppleIIGateSch/chipi74LS153.jhd b/AppleIIGateSch/chipi74LS153.jhd
new file mode 100644
index 0000000..5ef490d
--- /dev/null
+++ b/AppleIIGateSch/chipi74LS153.jhd
@@ -0,0 +1 @@
+MODULE chipi74LS153
diff --git a/AppleIIGateSch/chipi74LS153.sch b/AppleIIGateSch/chipi74LS153.sch
new file mode 100644
index 0000000..937d4f8
--- /dev/null
+++ b/AppleIIGateSch/chipi74LS153.sch
@@ -0,0 +1,384 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+    <attr value="spartan3e" name="DeviceFamilyName">
+        <trait delete="all:0" />
+        <trait editname="all:0" />
+        <trait edittrait="all:0" />
+    </attr>
+    <netlist>
+        <signal name="XLXN_1" />
+        <signal name="XLXN_3" />
+        <signal name="XLXN_4" />
+        <signal name="XLXN_5" />
+        <signal name="XLXN_6" />
+        <signal name="XLXN_7" />
+        <signal name="XLXN_8" />
+        <signal name="XLXN_9" />
+        <signal name="Zb_9" />
+        <signal name="Ebn_15" />
+        <signal name="XLXN_14" />
+        <signal name="b0_10" />
+        <signal name="b2_12" />
+        <signal name="b3_13" />
+        <signal name="Za_7" />
+        <signal name="Ean_11" />
+        <signal name="a0_6" />
+        <signal name="a1_5" />
+        <signal name="a2_4" />
+        <signal name="a3_3" />
+        <signal name="XLXN_26" />
+        <signal name="XLXN_42" />
+        <signal name="b1_11" />
+        <signal name="S0_14" />
+        <signal name="XLXN_52" />
+        <signal name="XLXN_53" />
+        <signal name="XLXN_54" />
+        <signal name="S1_2" />
+        <port polarity="Output" name="Zb_9" />
+        <port polarity="Input" name="Ebn_15" />
+        <port polarity="Input" name="b0_10" />
+        <port polarity="Input" name="b2_12" />
+        <port polarity="Input" name="b3_13" />
+        <port polarity="Output" name="Za_7" />
+        <port polarity="Input" name="Ean_11" />
+        <port polarity="Input" name="a0_6" />
+        <port polarity="Input" name="a1_5" />
+        <port polarity="Input" name="a2_4" />
+        <port polarity="Input" name="a3_3" />
+        <port polarity="Input" name="b1_11" />
+        <port polarity="Input" name="S0_14" />
+        <port polarity="Input" name="S1_2" />
+        <blockdef name="or4">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="48" y1="-64" y2="-64" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="48" y1="-256" y2="-256" x1="0" />
+            <line x2="192" y1="-160" y2="-160" x1="256" />
+            <arc ex="112" ey="-208" sx="192" sy="-160" r="88" cx="116" cy="-120" />
+            <line x2="48" y1="-208" y2="-208" x1="112" />
+            <line x2="48" y1="-112" y2="-112" x1="112" />
+            <line x2="48" y1="-256" y2="-208" x1="48" />
+            <line x2="48" y1="-64" y2="-112" x1="48" />
+            <arc ex="48" ey="-208" sx="48" sy="-112" r="56" cx="16" cy="-160" />
+            <arc ex="192" ey="-160" sx="112" sy="-112" r="88" cx="116" cy="-200" />
+        </blockdef>
+        <blockdef name="and4">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-112" y2="-112" x1="144" />
+            <arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
+            <line x2="144" y1="-208" y2="-208" x1="64" />
+            <line x2="64" y1="-64" y2="-256" x1="64" />
+            <line x2="192" y1="-160" y2="-160" x1="256" />
+            <line x2="64" y1="-256" y2="-256" x1="0" />
+            <line x2="64" y1="-192" y2="-192" x1="0" />
+            <line x2="64" y1="-128" y2="-128" x1="0" />
+            <line x2="64" y1="-64" y2="-64" x1="0" />
+        </blockdef>
+        <blockdef name="inv">
+            <timestamp>2000-1-1T10:10:10</timestamp>
+            <line x2="64" y1="-32" y2="-32" x1="0" />
+            <line x2="160" y1="-32" y2="-32" x1="224" />
+            <line x2="128" y1="-64" y2="-32" x1="64" />
+            <line x2="64" y1="-32" y2="0" x1="128" />
+            <line x2="64" y1="0" y2="-64" x1="64" />
+            <circle r="16" cx="144" cy="-32" />
+        </blockdef>
+        <block symbolname="or4" name="XLXI_1">
+            <blockpin signalname="XLXN_5" name="I0" />
+            <blockpin signalname="XLXN_4" name="I1" />
+            <blockpin signalname="XLXN_3" name="I2" />
+            <blockpin signalname="XLXN_1" name="I3" />
+            <blockpin signalname="Za_7" name="O" />
+        </block>
+        <block symbolname="or4" name="XLXI_2">
+            <blockpin signalname="XLXN_9" name="I0" />
+            <blockpin signalname="XLXN_8" name="I1" />
+            <blockpin signalname="XLXN_7" name="I2" />
+            <blockpin signalname="XLXN_6" name="I3" />
+            <blockpin signalname="Zb_9" name="O" />
+        </block>
+        <block symbolname="and4" name="XLXI_3">
+            <blockpin signalname="a1_5" name="I0" />
+            <blockpin signalname="XLXN_26" name="I1" />
+            <blockpin signalname="XLXN_53" name="I2" />
+            <blockpin signalname="XLXN_14" name="I3" />
+            <blockpin signalname="XLXN_3" name="O" />
+        </block>
+        <block symbolname="and4" name="XLXI_4">
+            <blockpin signalname="a0_6" name="I0" />
+            <blockpin signalname="XLXN_52" name="I1" />
+            <blockpin signalname="XLXN_53" name="I2" />
+            <blockpin signalname="XLXN_14" name="I3" />
+            <blockpin signalname="XLXN_1" name="O" />
+        </block>
+        <block symbolname="and4" name="XLXI_5">
+            <blockpin signalname="a2_4" name="I0" />
+            <blockpin signalname="XLXN_52" name="I1" />
+            <blockpin signalname="XLXN_54" name="I2" />
+            <blockpin signalname="XLXN_14" name="I3" />
+            <blockpin signalname="XLXN_4" name="O" />
+        </block>
+        <block symbolname="and4" name="XLXI_6">
+            <blockpin signalname="a3_3" name="I0" />
+            <blockpin signalname="XLXN_26" name="I1" />
+            <blockpin signalname="XLXN_54" name="I2" />
+            <blockpin signalname="XLXN_14" name="I3" />
+            <blockpin signalname="XLXN_5" name="O" />
+        </block>
+        <block symbolname="and4" name="XLXI_8">
+            <blockpin signalname="XLXN_42" name="I0" />
+            <blockpin signalname="XLXN_26" name="I1" />
+            <blockpin signalname="XLXN_53" name="I2" />
+            <blockpin signalname="b1_11" name="I3" />
+            <blockpin signalname="XLXN_7" name="O" />
+        </block>
+        <block symbolname="and4" name="XLXI_9">
+            <blockpin signalname="XLXN_42" name="I0" />
+            <blockpin signalname="XLXN_52" name="I1" />
+            <blockpin signalname="XLXN_54" name="I2" />
+            <blockpin signalname="b2_12" name="I3" />
+            <blockpin signalname="XLXN_8" name="O" />
+        </block>
+        <block symbolname="and4" name="XLXI_10">
+            <blockpin signalname="XLXN_42" name="I0" />
+            <blockpin signalname="XLXN_26" name="I1" />
+            <blockpin signalname="XLXN_54" name="I2" />
+            <blockpin signalname="b3_13" name="I3" />
+            <blockpin signalname="XLXN_9" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_11">
+            <blockpin signalname="Ean_11" name="I" />
+            <blockpin signalname="XLXN_14" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_12">
+            <blockpin signalname="Ebn_15" name="I" />
+            <blockpin signalname="XLXN_42" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_13">
+            <blockpin signalname="XLXN_52" name="I" />
+            <blockpin signalname="XLXN_26" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_14">
+            <blockpin signalname="S0_14" name="I" />
+            <blockpin signalname="XLXN_52" name="O" />
+        </block>
+        <block symbolname="and4" name="XLXI_15">
+            <blockpin signalname="XLXN_42" name="I0" />
+            <blockpin signalname="XLXN_52" name="I1" />
+            <blockpin signalname="XLXN_53" name="I2" />
+            <blockpin signalname="b0_10" name="I3" />
+            <blockpin signalname="XLXN_6" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_16">
+            <blockpin signalname="XLXN_53" name="I" />
+            <blockpin signalname="XLXN_54" name="O" />
+        </block>
+        <block symbolname="inv" name="XLXI_17">
+            <blockpin signalname="S1_2" name="I" />
+            <blockpin signalname="XLXN_53" name="O" />
+        </block>
+    </netlist>
+    <sheet sheetnum="1" width="3520" height="2720">
+        <instance x="2080" y="704" name="XLXI_3" orien="R0" />
+        <instance x="2080" y="400" name="XLXI_4" orien="R0" />
+        <instance x="2080" y="992" name="XLXI_5" orien="R0" />
+        <instance x="2064" y="1296" name="XLXI_6" orien="R0" />
+        <instance x="2768" y="864" name="XLXI_1" orien="R0" />
+        <instance x="2064" y="2608" name="XLXI_10" orien="R0" />
+        <branch name="XLXN_1">
+            <wire x2="2768" y1="240" y2="240" x1="2336" />
+            <wire x2="2768" y1="240" y2="608" x1="2768" />
+        </branch>
+        <branch name="XLXN_3">
+            <wire x2="2544" y1="544" y2="544" x1="2336" />
+            <wire x2="2544" y1="544" y2="672" x1="2544" />
+            <wire x2="2768" y1="672" y2="672" x1="2544" />
+        </branch>
+        <branch name="XLXN_4">
+            <wire x2="2544" y1="832" y2="832" x1="2336" />
+            <wire x2="2544" y1="736" y2="832" x1="2544" />
+            <wire x2="2768" y1="736" y2="736" x1="2544" />
+        </branch>
+        <branch name="XLXN_5">
+            <wire x2="2768" y1="1136" y2="1136" x1="2320" />
+            <wire x2="2768" y1="800" y2="1136" x1="2768" />
+        </branch>
+        <branch name="XLXN_6">
+            <wire x2="2736" y1="1680" y2="1680" x1="2320" />
+            <wire x2="2736" y1="1680" y2="1968" x1="2736" />
+        </branch>
+        <branch name="XLXN_9">
+            <wire x2="2736" y1="2448" y2="2448" x1="2320" />
+            <wire x2="2736" y1="2160" y2="2448" x1="2736" />
+        </branch>
+        <branch name="Za_7">
+            <wire x2="3168" y1="704" y2="704" x1="3024" />
+        </branch>
+        <branch name="Zb_9">
+            <wire x2="3168" y1="2064" y2="2064" x1="2992" />
+        </branch>
+        <instance x="992" y="176" name="XLXI_11" orien="R0" />
+        <branch name="Ean_11">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="864" y="144" type="branch" />
+            <wire x2="864" y1="144" y2="144" x1="784" />
+            <wire x2="992" y1="144" y2="144" x1="864" />
+        </branch>
+        <branch name="XLXN_14">
+            <wire x2="1952" y1="144" y2="144" x1="1216" />
+            <wire x2="2080" y1="144" y2="144" x1="1952" />
+            <wire x2="1952" y1="144" y2="448" x1="1952" />
+            <wire x2="1952" y1="448" y2="736" x1="1952" />
+            <wire x2="1952" y1="736" y2="1040" x1="1952" />
+            <wire x2="2064" y1="1040" y2="1040" x1="1952" />
+            <wire x2="2080" y1="736" y2="736" x1="1952" />
+            <wire x2="2080" y1="448" y2="448" x1="1952" />
+        </branch>
+        <branch name="a0_6">
+            <wire x2="2080" y1="336" y2="336" x1="1024" />
+        </branch>
+        <branch name="a1_5">
+            <wire x2="2080" y1="640" y2="640" x1="1040" />
+        </branch>
+        <branch name="a2_4">
+            <wire x2="2080" y1="928" y2="928" x1="1024" />
+        </branch>
+        <branch name="a3_3">
+            <wire x2="2064" y1="1232" y2="1232" x1="1024" />
+        </branch>
+        <iomarker fontsize="28" x="1024" y="336" name="a0_6" orien="R180" />
+        <iomarker fontsize="28" x="1040" y="640" name="a1_5" orien="R180" />
+        <iomarker fontsize="28" x="1024" y="928" name="a2_4" orien="R180" />
+        <iomarker fontsize="28" x="1024" y="1232" name="a3_3" orien="R180" />
+        <instance x="896" y="2576" name="XLXI_12" orien="R0" />
+        <branch name="Ebn_15">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="672" y="2544" type="branch" />
+            <wire x2="672" y1="2544" y2="2544" x1="592" />
+            <wire x2="896" y1="2544" y2="2544" x1="672" />
+        </branch>
+        <iomarker fontsize="28" x="3168" y="704" name="Za_7" orien="R0" />
+        <branch name="b0_10">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1120" y="1584" type="branch" />
+            <wire x2="1120" y1="1584" y2="1584" x1="1008" />
+            <wire x2="2064" y1="1584" y2="1584" x1="1120" />
+        </branch>
+        <branch name="b2_12">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1120" y="2096" type="branch" />
+            <wire x2="1120" y1="2096" y2="2096" x1="1024" />
+            <wire x2="2064" y1="2096" y2="2096" x1="1120" />
+        </branch>
+        <branch name="b3_13">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1120" y="2352" type="branch" />
+            <wire x2="1120" y1="2352" y2="2352" x1="1040" />
+            <wire x2="2064" y1="2352" y2="2352" x1="1120" />
+        </branch>
+        <iomarker fontsize="28" x="1040" y="2352" name="b3_13" orien="R180" />
+        <branch name="XLXN_26">
+            <wire x2="1744" y1="1456" y2="1456" x1="1264" />
+            <wire x2="1744" y1="1456" y2="1968" x1="1744" />
+            <wire x2="2064" y1="1968" y2="1968" x1="1744" />
+            <wire x2="1744" y1="1968" y2="2480" x1="1744" />
+            <wire x2="2064" y1="2480" y2="2480" x1="1744" />
+            <wire x2="2080" y1="576" y2="576" x1="1744" />
+            <wire x2="1744" y1="576" y2="1168" x1="1744" />
+            <wire x2="2064" y1="1168" y2="1168" x1="1744" />
+            <wire x2="1744" y1="1168" y2="1456" x1="1744" />
+        </branch>
+        <instance x="2064" y="2352" name="XLXI_9" orien="R0" />
+        <instance x="2064" y="2096" name="XLXI_8" orien="R0" />
+        <instance x="2736" y="2224" name="XLXI_2" orien="R0" />
+        <branch name="XLXN_7">
+            <wire x2="2336" y1="1936" y2="1936" x1="2320" />
+            <wire x2="2336" y1="1936" y2="2032" x1="2336" />
+            <wire x2="2736" y1="2032" y2="2032" x1="2336" />
+        </branch>
+        <branch name="XLXN_8">
+            <wire x2="2336" y1="2192" y2="2192" x1="2320" />
+            <wire x2="2736" y1="2096" y2="2096" x1="2336" />
+            <wire x2="2336" y1="2096" y2="2192" x1="2336" />
+        </branch>
+        <iomarker fontsize="28" x="3168" y="2064" name="Zb_9" orien="R0" />
+        <iomarker fontsize="28" x="1008" y="1584" name="b0_10" orien="R180" />
+        <instance x="2064" y="1840" name="XLXI_15" orien="R0" />
+        <branch name="XLXN_42">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1536" y="2544" type="branch" />
+            <wire x2="1536" y1="2544" y2="2544" x1="1120" />
+            <wire x2="1952" y1="2544" y2="2544" x1="1536" />
+            <wire x2="2064" y1="2544" y2="2544" x1="1952" />
+            <wire x2="2064" y1="1776" y2="1776" x1="1952" />
+            <wire x2="1952" y1="1776" y2="2032" x1="1952" />
+            <wire x2="1952" y1="2032" y2="2288" x1="1952" />
+            <wire x2="1952" y1="2288" y2="2544" x1="1952" />
+            <wire x2="2064" y1="2288" y2="2288" x1="1952" />
+            <wire x2="2064" y1="2032" y2="2032" x1="1952" />
+        </branch>
+        <iomarker fontsize="28" x="1024" y="2096" name="b2_12" orien="R180" />
+        <branch name="b1_11">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1104" y="1840" type="branch" />
+            <wire x2="1104" y1="1840" y2="1840" x1="1008" />
+            <wire x2="2064" y1="1840" y2="1840" x1="1104" />
+        </branch>
+        <iomarker fontsize="28" x="1008" y="1840" name="b1_11" orien="R180" />
+        <branch name="S0_14">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="592" y="1456" type="branch" />
+            <wire x2="592" y1="1456" y2="1456" x1="528" />
+            <wire x2="720" y1="1456" y2="1456" x1="592" />
+        </branch>
+        <instance x="1040" y="1488" name="XLXI_13" orien="R0" />
+        <instance x="720" y="1488" name="XLXI_14" orien="R0" />
+        <iomarker fontsize="28" x="528" y="1456" name="S0_14" orien="R180" />
+        <branch name="XLXN_52">
+            <wire x2="992" y1="1456" y2="1456" x1="944" />
+            <wire x2="1040" y1="1456" y2="1456" x1="992" />
+            <wire x2="992" y1="1456" y2="1504" x1="992" />
+            <wire x2="1888" y1="1504" y2="1504" x1="992" />
+            <wire x2="1888" y1="1504" y2="1712" x1="1888" />
+            <wire x2="1888" y1="1712" y2="2224" x1="1888" />
+            <wire x2="2064" y1="2224" y2="2224" x1="1888" />
+            <wire x2="2064" y1="1712" y2="1712" x1="1888" />
+            <wire x2="2080" y1="272" y2="272" x1="1888" />
+            <wire x2="1888" y1="272" y2="864" x1="1888" />
+            <wire x2="2080" y1="864" y2="864" x1="1888" />
+            <wire x2="1888" y1="864" y2="1504" x1="1888" />
+        </branch>
+        <branch name="XLXN_53">
+            <wire x2="992" y1="1360" y2="1360" x1="944" />
+            <wire x2="1040" y1="1360" y2="1360" x1="992" />
+            <wire x2="1824" y1="1312" y2="1312" x1="992" />
+            <wire x2="1824" y1="1312" y2="1648" x1="1824" />
+            <wire x2="1824" y1="1648" y2="1904" x1="1824" />
+            <wire x2="2064" y1="1904" y2="1904" x1="1824" />
+            <wire x2="2064" y1="1648" y2="1648" x1="1824" />
+            <wire x2="992" y1="1312" y2="1360" x1="992" />
+            <wire x2="2080" y1="208" y2="208" x1="1824" />
+            <wire x2="1824" y1="208" y2="512" x1="1824" />
+            <wire x2="2080" y1="512" y2="512" x1="1824" />
+            <wire x2="1824" y1="512" y2="1312" x1="1824" />
+        </branch>
+        <branch name="XLXN_54">
+            <wire x2="1328" y1="1360" y2="1360" x1="1264" />
+            <wire x2="1664" y1="1360" y2="1360" x1="1328" />
+            <wire x2="1664" y1="1360" y2="2160" x1="1664" />
+            <wire x2="1664" y1="2160" y2="2416" x1="1664" />
+            <wire x2="2064" y1="2416" y2="2416" x1="1664" />
+            <wire x2="2064" y1="2160" y2="2160" x1="1664" />
+            <wire x2="2080" y1="800" y2="800" x1="1664" />
+            <wire x2="1664" y1="800" y2="1104" x1="1664" />
+            <wire x2="2064" y1="1104" y2="1104" x1="1664" />
+            <wire x2="1664" y1="1104" y2="1360" x1="1664" />
+        </branch>
+        <instance x="1040" y="1392" name="XLXI_16" orien="R0" />
+        <instance x="720" y="1392" name="XLXI_17" orien="R0" />
+        <branch name="S1_2">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="592" y="1360" type="branch" />
+            <wire x2="592" y1="1360" y2="1360" x1="512" />
+            <wire x2="720" y1="1360" y2="1360" x1="592" />
+        </branch>
+        <iomarker fontsize="28" x="512" y="1360" name="S1_2" orien="R180" />
+        <text style="fontsize:52;fontname:Arial" x="2712" y="72">74LS153 from TI TTL Data Book</text>
+        <text style="fontsize:52;fontname:Arial" x="2788" y="156">Made for APPLE II schematic</text>
+        <text style="fontsize:52;fontname:Arial" x="3108" y="248">FWK 20180527</text>
+        <iomarker fontsize="28" x="784" y="144" name="Ean_11" orien="R180" />
+        <iomarker fontsize="28" x="592" y="2544" name="Ebn_15" orien="R180" />
+    </sheet>
+</drawing>
\ No newline at end of file
diff --git a/AppleIIGateSch/chipi74LS153.sym b/AppleIIGateSch/chipi74LS153.sym
new file mode 100644
index 0000000..c281c68
--- /dev/null
+++ b/AppleIIGateSch/chipi74LS153.sym
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="chipi74LS153">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2018-6-4T6:43:36</timestamp>
+    <pin polarity="Input" x="384" y="-224" name="a0_6" />
+    <pin polarity="Input" x="384" y="-160" name="a1_5" />
+    <pin polarity="Input" x="384" y="-96" name="a2_4" />
+    <pin polarity="Input" x="384" y="-32" name="a3_3" />
+    <pin polarity="Input" x="384" y="-544" name="b0_10" />
+    <pin polarity="Input" x="384" y="-480" name="b1_11" />
+    <pin polarity="Input" x="384" y="-416" name="b2_12" />
+    <pin polarity="Input" x="384" y="-352" name="b3_13" />
+    <pin polarity="Input" x="0" y="-288" name="Ean_11" />
+    <pin polarity="Input" x="0" y="-352" name="Ebn_15" />
+    <pin polarity="Input" x="0" y="-544" name="S0_14" />
+    <pin polarity="Input" x="0" y="-32" name="S1_2" />
+    <pin polarity="Output" x="0" y="-224" name="Za_7" />
+    <pin polarity="Output" x="0" y="-480" name="Zb_9" />
+    <graph>
+        <rect width="256" x="64" y="-576" height="576" />
+        <attrtext style="alignment:BCENTER;fontsize:40;fontname:Arial" attrname="SymbolName" x="192" y="-584" type="symbol" />
+        <line x2="384" y1="-224" y2="-224" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin a0_6" />
+        <line x2="384" y1="-160" y2="-160" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin a1_5" />
+        <line x2="384" y1="-96" y2="-96" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin a2_4" />
+        <line x2="384" y1="-32" y2="-32" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin a3_3" />
+        <line x2="384" y1="-544" y2="-544" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-544" type="pin b0_10" />
+        <line x2="384" y1="-480" y2="-480" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-480" type="pin b1_11" />
+        <line x2="384" y1="-416" y2="-416" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin b2_12" />
+        <line x2="384" y1="-352" y2="-352" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-352" type="pin b3_13" />
+        <line x2="0" y1="-288" y2="-288" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin Ean_11" />
+        <line x2="0" y1="-352" y2="-352" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin Ebn_15" />
+        <line x2="0" y1="-544" y2="-544" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-544" type="pin S0_14" />
+        <line x2="0" y1="-32" y2="-32" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin S1_2" />
+        <line x2="0" y1="-224" y2="-224" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin Za_7" />
+        <line x2="0" y1="-480" y2="-480" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-480" type="pin Zb_9" />
+        <circle r="12" cx="56" cy="-352" />
+        <circle r="12" cx="56" cy="-288" />
+    </graph>
+</symbol>
diff --git a/AppleIIGateSch/fuse.xmsgs b/AppleIIGateSch/fuse.xmsgs
new file mode 100644
index 0000000..c42b14a
--- /dev/null
+++ b/AppleIIGateSch/fuse.xmsgs
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+</messages>
+
diff --git a/AppleIIGateSch/fuseRelaunch.cmd b/AppleIIGateSch/fuseRelaunch.cmd
new file mode 100644
index 0000000..8fe9466
--- /dev/null
+++ b/AppleIIGateSch/fuseRelaunch.cmd
@@ -0,0 +1 @@
+-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -o "C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS257_chip74LS257_sch_tb_isim_beh.exe" -prj "C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS257_chip74LS257_sch_tb_beh.prj" "work.chip74LS257_chip74LS257_sch_tb" "work.glbl" 
diff --git a/AppleIIGateSch/iseconfig/AppleIIGateSch.projectmgr b/AppleIIGateSch/iseconfig/AppleIIGateSch.projectmgr
new file mode 100644
index 0000000..584544a
--- /dev/null
+++ b/AppleIIGateSch/iseconfig/AppleIIGateSch.projectmgr
@@ -0,0 +1,133 @@
+<?xml version='1.0' encoding='utf-8'?>
+<!--This is an ISE project configuration file.-->
+<!--It holds project specific layout data for the projectmgr plugin.-->
+<!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
+<Project version="2" owner="projectmgr" name="AppleIIGateSch" >
+   <!--This is an ISE project configuration file.-->
+   <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
+      <ClosedNodes>
+         <ClosedNodesVersion>2</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>chip74LS257 (C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS257.sch)</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >4</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000154000000020000000000000000000000000200000064ffffffff000000810000000300000002000001540000000100000003000000000000000100000003</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
+      <CurrentItem>chip74LS257 (C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS257.sch)</CurrentItem>
+   </ItemView>
+   <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+         <ClosedNode>Design Utilities</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem/>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000108000000010000000100000000000000000000000064ffffffff000000810000000000000001000001080000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem/>
+   </ItemView>
+   <ItemView guiview="File" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>chip74LS161.sch</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000028e000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001c20000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>chip74LS161.sch</CurrentItem>
+   </ItemView>
+   <ItemView guiview="Library" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>chip74LS153_tb.v</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>chip74LS153_tb.v</CurrentItem>
+   </ItemView>
+   <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
+      <ClosedNodes>
+         <ClosedNodesVersion>2</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>chip74LS257_chip74LS257_sch_tb (C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS257_tb.v)</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >15</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
+      <CurrentItem>chip74LS257_chip74LS257_sch_tb (C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS257_tb.v)</CurrentItem>
+   </ItemView>
+   <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem/>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000108000000010000000100000000000000000000000064ffffffff000000810000000000000001000001080000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem/>
+   </ItemView>
+   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_SCHEMATIC" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+         <ClosedNode>Configure Target Device</ClosedNode>
+         <ClosedNode>Implement Design/Map</ClosedNode>
+         <ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
+         <ClosedNode>Implement Design/Translate</ClosedNode>
+         <ClosedNode>Synthesize - XST</ClosedNode>
+         <ClosedNode>User Constraints</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>Design Utilities</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000108000000010000000100000000000000000000000064ffffffff000000810000000000000001000001080000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>Design Utilities</CurrentItem>
+   </ItemView>
+   <ItemView engineview="BehavioralSim" sourcetype="DESUT_VERILOG" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>Simulate Behavioral Model</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000108000000010000000100000000000000000000000064ffffffff000000810000000000000001000001080000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>Simulate Behavioral Model</CurrentItem>
+   </ItemView>
+   <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
+   <CurrentView>Behavioral Simulation</CurrentView>
+   <ItemView engineview="BehavioralSim" sourcetype="DESUT_SCHEMATIC" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem></SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000108000000010000000100000000000000000000000064ffffffff000000810000000000000001000001080000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem></CurrentItem>
+   </ItemView>
+</Project>
diff --git a/AppleIIGateSch/iseconfig/ClockVideoGenerator.xreport b/AppleIIGateSch/iseconfig/ClockVideoGenerator.xreport
new file mode 100644
index 0000000..aac3582
--- /dev/null
+++ b/AppleIIGateSch/iseconfig/ClockVideoGenerator.xreport
@@ -0,0 +1,215 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2018-06-07T15:05:13</DateModified>
+  <ModuleName>ClockVideoGenerator</ModuleName>
+  <SummaryTimeStamp>2018-06-04T00:17:34</SummaryTimeStamp>
+  <SavedFilePath>C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/iseconfig/ClockVideoGenerator.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch\</ImplementationReportsDirectory>
+  <DateInitialized>2018-06-03T23:03:36</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="ClockVideoGenerator_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="ClockVideoGenerator_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="ClockVideoGenerator_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="ClockVideoGenerator_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="ClockVideoGenerator_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="ClockVideoGenerator.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="ClockVideoGenerator_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="ClockVideoGenerator_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="ClockVideoGenerator.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ClockVideoGenerator_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ClockVideoGenerator_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="ClockVideoGenerator.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="ClockVideoGenerator.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="ClockVideoGenerator.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="ClockVideoGenerator.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="ClockVideoGenerator.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="ClockVideoGenerator_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="ClockVideoGenerator.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="ClockVideoGenerator.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="ClockVideoGenerator.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="ClockVideoGenerator.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="ClockVideoGenerator.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="ClockVideoGenerator.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/ClockVideoGenerator_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/ClockVideoGenerator_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ClockVideoGenerator_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/ClockVideoGenerator_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_map.psr" label="Physical Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="ClockVideoGenerator_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ClockVideoGenerator.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.tsi" label="Post-Place and Route Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/ClockVideoGenerator_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/ClockVideoGenerator_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
diff --git a/AppleIIGateSch/iseconfig/chip74LS161.xreport b/AppleIIGateSch/iseconfig/chip74LS161.xreport
new file mode 100644
index 0000000..14818ef
--- /dev/null
+++ b/AppleIIGateSch/iseconfig/chip74LS161.xreport
@@ -0,0 +1,215 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2018-06-03T22:59:28</DateModified>
+  <ModuleName>ClockVideoGenerator</ModuleName>
+  <SummaryTimeStamp>2018-05-23T17:00:46</SummaryTimeStamp>
+  <SavedFilePath>C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/iseconfig/chip74LS161.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch\</ImplementationReportsDirectory>
+  <DateInitialized>2018-06-03T22:59:27</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="ClockVideoGenerator_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="ClockVideoGenerator_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="ClockVideoGenerator_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="ClockVideoGenerator_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="ClockVideoGenerator_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="ClockVideoGenerator.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="ClockVideoGenerator_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="ClockVideoGenerator_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="ClockVideoGenerator.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ClockVideoGenerator_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ClockVideoGenerator_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="ClockVideoGenerator.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="ClockVideoGenerator.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="ClockVideoGenerator.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="ClockVideoGenerator.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="ClockVideoGenerator.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="ClockVideoGenerator_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="ClockVideoGenerator.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="ClockVideoGenerator.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="ClockVideoGenerator.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="ClockVideoGenerator.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="ClockVideoGenerator.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="ClockVideoGenerator.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/ClockVideoGenerator_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/ClockVideoGenerator_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ClockVideoGenerator_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/ClockVideoGenerator_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_map.psr" label="Physical Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="ClockVideoGenerator_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ClockVideoGenerator.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.tsi" label="Post-Place and Route Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/ClockVideoGenerator_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ClockVideoGenerator.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/ClockVideoGenerator_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
diff --git a/AppleIIGateSch/isim.log b/AppleIIGateSch/isim.log
new file mode 100644
index 0000000..0d773f4
--- /dev/null
+++ b/AppleIIGateSch/isim.log
@@ -0,0 +1,18 @@
+ISim log file
+Running: C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS257_chip74LS257_sch_tb_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS257_chip74LS257_sch_tb_isim_beh.wdb 
+ISim P.20131013 (signature 0x7708f090)
+----------------------------------------------------------------------
+WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
+
+
+----------------------------------------------------------------------
+This is a Full version of ISim.
+Time resolution is 1 ps
+# onerror resume
+# wave add /
+# run 30000 ns
+Simulator is doing circuit initialization process.
+auto_init not defined
+Finished circuit initialization process.
+PASSED
+Stopped at time : 10340 ns : File "C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS257_tb.v" Line 102