Apple-2-HW/Apple2-IO-RPi
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Apple2-IO-RPi/Hardware/Apple2IORPi.kicad_pcb

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Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(kicad_pcb (version 20171130) (host pcbnew 5.1.5+dfsg1-2build2)
(general
(thickness 1.6)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(drawings 78)
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(tracks 764)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(zones 0)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(modules 14)
(nets 97)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(page USLetter)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(title_block
(title "Apple II I/O RPi")
(date 2020-11-19)
(rev 0.1)
(company "Terence J. Boldt")
)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user hide)
(33 F.Adhes user hide)
(34 B.Paste user hide)
(35 F.Paste user hide)
(36 B.SilkS user)
(37 F.SilkS user)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(38 B.Mask user hide)
(39 F.Mask user hide)
Update schematic and create rough PCB layout
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(40 Dwgs.User user hide)
(41 Cmts.User user hide)
(42 Eco1.User user hide)
(43 Eco2.User user hide)
(44 Edge.Cuts user)
(45 Margin user hide)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(46 B.CrtYd user hide)
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(47 F.CrtYd user hide)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(48 B.Fab user hide)
(49 F.Fab user hide)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
(setup
Update PCB component layout
2020-11-17 00:21:56 +00:00
(last_trace_width 0.1778)
(trace_clearance 0.1778)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(zone_clearance 0.508)
(zone_45_only no)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(trace_min 0.1778)
(via_size 0.762)
(via_drill 0.50038)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.051)
(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(layerselection 0x010f0_ffffffff)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(outputformat 4)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(mirror false)
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(drillshape 0)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 "Net-(U0-Pad15)")
(net 2 "Net-(U1-Pad2)")
(net 3 "Net-(U0-Pad14)")
(net 4 "Net-(J0-Pad9)")
(net 5 "Net-(U0-Pad13)")
(net 6 "Net-(J0-Pad8)")
(net 7 "Net-(U0-Pad12)")
(net 8 "Net-(J0-Pad7)")
(net 9 "Net-(U0-Pad11)")
(net 10 "Net-(J0-Pad6)")
(net 11 "Net-(J0-Pad1)")
(net 12 "Net-(J0-Pad5)")
(net 13 "Net-(J0-Pad12)")
(net 14 "Net-(J0-Pad4)")
(net 15 "Net-(J0-Pad3)")
(net 16 "Net-(U1-Pad23)")
(net 17 "Net-(J0-Pad2)")
(net 18 "Net-(J0-Pad11)")
(net 19 "Net-(U0-Pad18)")
(net 20 "Net-(J0-Pad10)")
(net 21 "Net-(U0-Pad17)")
(net 22 "Net-(U1-Pad26)")
(net 23 "Net-(U0-Pad16)")
(net 24 "Net-(J0-Pad13)")
(net 25 "Net-(J0-Pad14)")
(net 26 "Net-(J0-Pad15)")
(net 27 "Net-(J0-Pad16)")
(net 28 "Net-(J0-Pad17)")
(net 29 "Net-(J0-Pad18)")
(net 30 "Net-(J0-Pad19)")
(net 31 "Net-(J0-Pad20)")
(net 32 "Net-(J0-Pad21)")
(net 33 "Net-(J0-Pad22)")
(net 34 "Net-(J0-Pad23)")
(net 35 "Net-(J0-Pad24)")
(net 36 "Net-(J0-Pad29)")
(net 37 "Net-(J0-Pad30)")
(net 38 "Net-(J0-Pad31)")
(net 39 "Net-(J0-Pad32)")
(net 40 "Net-(J0-Pad33)")
(net 41 "Net-(J0-Pad34)")
(net 42 "Net-(J0-Pad35)")
(net 43 "Net-(J0-Pad36)")
(net 44 "Net-(J0-Pad37)")
(net 45 "Net-(J0-Pad38)")
(net 46 "Net-(J0-Pad39)")
(net 47 "Net-(J0-Pad40)")
(net 48 "Net-(J0-Pad43)")
(net 49 "Net-(J0-Pad44)")
(net 50 "Net-(J0-Pad45)")
(net 51 "Net-(J0-Pad46)")
(net 52 "Net-(J0-Pad47)")
(net 53 "Net-(J0-Pad48)")
(net 54 "Net-(J0-Pad49)")
(net 55 "Net-(J0-Pad50)")
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 56 "Net-(J1-Pad3)")
(net 57 "Net-(J1-Pad5)")
(net 58 "Net-(J1-Pad7)")
(net 59 "Net-(J1-Pad8)")
(net 60 "Net-(J1-Pad10)")
(net 61 "Net-(J1-Pad11)")
(net 62 "Net-(J1-Pad12)")
(net 63 "Net-(J1-Pad13)")
(net 64 "Net-(J1-Pad15)")
(net 65 "Net-(J1-Pad16)")
(net 66 "Net-(J1-Pad18)")
(net 67 "Net-(J1-Pad19)")
(net 68 "Net-(J1-Pad21)")
(net 69 "Net-(J1-Pad22)")
(net 70 "Net-(J1-Pad23)")
(net 71 "Net-(J1-Pad24)")
(net 72 "Net-(J1-Pad26)")
(net 73 "Net-(J1-Pad27)")
(net 74 "Net-(J1-Pad28)")
(net 75 "Net-(J1-Pad29)")
(net 76 "Net-(J1-Pad31)")
(net 77 "Net-(J1-Pad32)")
(net 78 "Net-(J1-Pad33)")
(net 79 "Net-(J1-Pad35)")
(net 80 "Net-(J1-Pad36)")
(net 81 "Net-(J1-Pad37)")
(net 82 "Net-(J1-Pad38)")
(net 83 "Net-(J1-Pad40)")
(net 84 "Net-(U0-Pad1)")
(net 85 "Net-(J0-Pad42)")
(net 86 "Net-(U0-Pad19)")
(net 87 "Net-(U2-Pad3)")
(net 88 "Net-(U2-Pad8)")
(net 89 "Net-(J0-Pad41)")
(net 90 "Net-(U3-Pad1)")
(net 91 "Net-(U3-Pad10)")
(net 92 "Net-(C1-Pad2)")
(net 93 "Net-(C1-Pad1)")
(net 94 "Net-(C5-Pad1)")
(net 95 "Net-(U3-Pad3)")
(net 96 "Net-(U3-Pad8)")
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(net_class Default "This is the default net class."
Update PCB component layout
2020-11-17 00:21:56 +00:00
(clearance 0.1778)
(trace_width 0.1778)
(via_dia 0.762)
(via_drill 0.50038)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "Net-(J0-Pad1)")
(add_net "Net-(J0-Pad10)")
(add_net "Net-(J0-Pad11)")
(add_net "Net-(J0-Pad12)")
(add_net "Net-(J0-Pad13)")
(add_net "Net-(J0-Pad14)")
(add_net "Net-(J0-Pad15)")
(add_net "Net-(J0-Pad16)")
(add_net "Net-(J0-Pad17)")
(add_net "Net-(J0-Pad18)")
(add_net "Net-(J0-Pad19)")
(add_net "Net-(J0-Pad2)")
(add_net "Net-(J0-Pad20)")
(add_net "Net-(J0-Pad21)")
(add_net "Net-(J0-Pad22)")
(add_net "Net-(J0-Pad23)")
(add_net "Net-(J0-Pad24)")
(add_net "Net-(J0-Pad29)")
(add_net "Net-(J0-Pad3)")
(add_net "Net-(J0-Pad30)")
(add_net "Net-(J0-Pad31)")
(add_net "Net-(J0-Pad32)")
(add_net "Net-(J0-Pad33)")
(add_net "Net-(J0-Pad34)")
(add_net "Net-(J0-Pad35)")
(add_net "Net-(J0-Pad36)")
(add_net "Net-(J0-Pad37)")
(add_net "Net-(J0-Pad38)")
(add_net "Net-(J0-Pad39)")
(add_net "Net-(J0-Pad4)")
(add_net "Net-(J0-Pad40)")
(add_net "Net-(J0-Pad41)")
(add_net "Net-(J0-Pad42)")
(add_net "Net-(J0-Pad43)")
(add_net "Net-(J0-Pad44)")
(add_net "Net-(J0-Pad45)")
(add_net "Net-(J0-Pad46)")
(add_net "Net-(J0-Pad47)")
(add_net "Net-(J0-Pad48)")
(add_net "Net-(J0-Pad49)")
(add_net "Net-(J0-Pad5)")
(add_net "Net-(J0-Pad50)")
(add_net "Net-(J0-Pad6)")
(add_net "Net-(J0-Pad7)")
(add_net "Net-(J0-Pad8)")
(add_net "Net-(J0-Pad9)")
(add_net "Net-(J1-Pad10)")
(add_net "Net-(J1-Pad11)")
(add_net "Net-(J1-Pad12)")
(add_net "Net-(J1-Pad13)")
(add_net "Net-(J1-Pad15)")
(add_net "Net-(J1-Pad16)")
(add_net "Net-(J1-Pad18)")
(add_net "Net-(J1-Pad19)")
(add_net "Net-(J1-Pad21)")
(add_net "Net-(J1-Pad22)")
(add_net "Net-(J1-Pad23)")
(add_net "Net-(J1-Pad24)")
(add_net "Net-(J1-Pad26)")
(add_net "Net-(J1-Pad27)")
(add_net "Net-(J1-Pad28)")
(add_net "Net-(J1-Pad29)")
(add_net "Net-(J1-Pad3)")
(add_net "Net-(J1-Pad31)")
(add_net "Net-(J1-Pad32)")
(add_net "Net-(J1-Pad33)")
(add_net "Net-(J1-Pad35)")
(add_net "Net-(J1-Pad36)")
(add_net "Net-(J1-Pad37)")
(add_net "Net-(J1-Pad38)")
(add_net "Net-(J1-Pad40)")
(add_net "Net-(J1-Pad5)")
(add_net "Net-(J1-Pad7)")
(add_net "Net-(J1-Pad8)")
(add_net "Net-(U0-Pad1)")
(add_net "Net-(U0-Pad11)")
(add_net "Net-(U0-Pad12)")
(add_net "Net-(U0-Pad13)")
(add_net "Net-(U0-Pad14)")
(add_net "Net-(U0-Pad15)")
(add_net "Net-(U0-Pad16)")
(add_net "Net-(U0-Pad17)")
(add_net "Net-(U0-Pad18)")
(add_net "Net-(U0-Pad19)")
(add_net "Net-(U1-Pad2)")
(add_net "Net-(U1-Pad23)")
(add_net "Net-(U1-Pad26)")
(add_net "Net-(U2-Pad3)")
(add_net "Net-(U2-Pad8)")
(add_net "Net-(U3-Pad1)")
(add_net "Net-(U3-Pad10)")
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(add_net "Net-(U3-Pad3)")
(add_net "Net-(U3-Pad8)")
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(net_class 3V3 ""
(clearance 0.1778)
(trace_width 0.3556)
(via_dia 0.762)
(via_drill 0.50038)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "Net-(C5-Pad1)")
)
(net_class 5V ""
Update PCB component layout
2020-11-17 00:21:56 +00:00
(clearance 0.254)
(trace_width 0.8128)
(via_dia 0.762)
(via_drill 0.7112)
(uvia_dia 0.3)
(uvia_drill 0.1)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(add_net "Net-(C1-Pad1)")
Update PCB component layout
2020-11-17 00:21:56 +00:00
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(net_class Ground ""
Update PCB component layout
2020-11-17 00:21:56 +00:00
(clearance 0.254)
(trace_width 0.8128)
(via_dia 0.762)
(via_drill 0.7112)
(uvia_dia 0.3)
(uvia_drill 0.1)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(add_net "Net-(C1-Pad2)")
Update PCB component layout
2020-11-17 00:21:56 +00:00
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(module Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm (layer F.Cu) (tedit 5FB6E1BD) (tstamp 5FB68750)
(at 121.285 66.675 270)
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(path /5FB87862)
(fp_text reference C6 (at 1.25 -2.55 270) (layer F.Fab)
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(fp_text value C (at 1.25 2.55 270) (layer F.Fab)
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(fp_text user %R (at 1.25 0 270) (layer F.Fab)
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(effects (font (size 0.76 0.76) (thickness 0.114)))
)
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(net 92 "Net-(C1-Pad2)"))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 94 "Net-(C5-Pad1)"))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(module Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm (layer F.Cu) (tedit 5FB6E185) (tstamp 5FB6873B)
(at 121.285 81.28 270)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(path /5FB8694D)
(fp_text reference C5 (at 1.25 -2.55 270) (layer F.Fab)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(fp_text value C (at 1.25 2.55 270) (layer F.Fab)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(fp_text user %R (at 1.25 0 270) (layer F.Fab)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(effects (font (size 0.76 0.76) (thickness 0.114)))
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(net 94 "Net-(C5-Pad1)"))
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 92 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
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(at 121.285 94.615 270)
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(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
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(fp_line (start 48.895 1.27) (end 49.53 1.27) (layer F.Fab) (width 0.15))
(fp_line (start 48.895 7.62) (end 48.895 1.27) (layer F.Fab) (width 0.15))
(pad 50 connect roundrect (at -13.97 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 55 "Net-(J0-Pad50)"))
(pad 49 connect roundrect (at -11.43 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 54 "Net-(J0-Pad49)"))
(pad 48 connect roundrect (at -8.89 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 53 "Net-(J0-Pad48)"))
(pad 47 connect roundrect (at -6.35 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 52 "Net-(J0-Pad47)"))
(pad 46 connect roundrect (at -3.81 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 51 "Net-(J0-Pad46)"))
(pad 45 connect roundrect (at -1.27 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 50 "Net-(J0-Pad45)"))
(pad 44 connect roundrect (at 1.27 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 49 "Net-(J0-Pad44)"))
(pad 43 connect roundrect (at 3.81 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 48 "Net-(J0-Pad43)"))
(pad 42 connect roundrect (at 6.35 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 85 "Net-(J0-Pad42)"))
(pad 41 connect roundrect (at 8.89 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 89 "Net-(J0-Pad41)"))
(pad 40 connect roundrect (at 11.43 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 47 "Net-(J0-Pad40)"))
(pad 39 connect roundrect (at 13.97 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 46 "Net-(J0-Pad39)"))
(pad 37 connect roundrect (at 19.05 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 44 "Net-(J0-Pad37)"))
(pad 38 connect roundrect (at 16.51 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 45 "Net-(J0-Pad38)"))
(pad 36 connect roundrect (at 21.59 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 43 "Net-(J0-Pad36)"))
(pad 35 connect roundrect (at 24.13 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 42 "Net-(J0-Pad35)"))
(pad 34 connect roundrect (at 26.67 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 41 "Net-(J0-Pad34)"))
(pad 33 connect roundrect (at 29.21 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 40 "Net-(J0-Pad33)"))
(pad 32 connect roundrect (at 31.75 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 39 "Net-(J0-Pad32)"))
(pad 31 connect roundrect (at 34.29 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 38 "Net-(J0-Pad31)"))
(pad 30 connect roundrect (at 36.83 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 37 "Net-(J0-Pad30)"))
(pad 29 connect roundrect (at 39.37 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 36 "Net-(J0-Pad29)"))
(pad 28 connect roundrect (at 41.91 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 34 "Net-(J0-Pad23)"))
(pad 27 connect roundrect (at 44.45 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 35 "Net-(J0-Pad24)"))
(pad 26 connect roundrect (at 46.99 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
(net 92 "Net-(C1-Pad2)"))
(pad 25 connect roundrect (at 46.99 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 93 "Net-(C1-Pad1)"))
(pad 24 connect roundrect (at 44.45 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 35 "Net-(J0-Pad24)"))
(pad 23 connect roundrect (at 41.91 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 34 "Net-(J0-Pad23)"))
(pad 22 connect roundrect (at 39.37 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 33 "Net-(J0-Pad22)"))
(pad 21 connect roundrect (at 36.83 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 32 "Net-(J0-Pad21)"))
(pad 20 connect roundrect (at 34.29 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 31 "Net-(J0-Pad20)"))
(pad 19 connect roundrect (at 31.75 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 30 "Net-(J0-Pad19)"))
(pad 18 connect roundrect (at 29.21 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 29 "Net-(J0-Pad18)"))
(pad 17 connect roundrect (at 26.67 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 28 "Net-(J0-Pad17)"))
(pad 16 connect roundrect (at 24.13 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 27 "Net-(J0-Pad16)"))
(pad 15 connect roundrect (at 21.59 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 26 "Net-(J0-Pad15)"))
(pad 14 connect roundrect (at 19.05 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 25 "Net-(J0-Pad14)"))
(pad 13 connect roundrect (at 16.51 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 24 "Net-(J0-Pad13)"))
(pad 12 connect roundrect (at 13.97 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 13 "Net-(J0-Pad12)"))
(pad 11 connect roundrect (at 11.43 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 18 "Net-(J0-Pad11)"))
(pad 10 connect roundrect (at 8.89 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 20 "Net-(J0-Pad10)"))
(pad 9 connect roundrect (at 6.35 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 4 "Net-(J0-Pad9)"))
(pad 8 connect roundrect (at 3.81 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 6 "Net-(J0-Pad8)"))
(pad 7 connect roundrect (at 1.27 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 8 "Net-(J0-Pad7)"))
(pad 6 connect roundrect (at -1.27 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 10 "Net-(J0-Pad6)"))
(pad 5 connect roundrect (at -3.81 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 12 "Net-(J0-Pad5)"))
(pad 4 connect roundrect (at -6.35 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 14 "Net-(J0-Pad4)"))
(pad 3 connect roundrect (at -8.89 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 15 "Net-(J0-Pad3)"))
(pad 2 connect roundrect (at -11.43 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 17 "Net-(J0-Pad2)"))
(pad 1 connect roundrect (at -13.97 5.08) (size 1.27 7.62) (layers F.Cu F.Mask) (roundrect_rratio 0.25)
(net 11 "Net-(J0-Pad1)"))
)
(module Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm (layer F.Cu) (tedit 5FB6AB23) (tstamp 5FB68726)
(at 168.275 62.865 180)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /5FB82906)
(fp_text reference C4 (at 1.25 -2.55) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value C (at 1.25 2.55) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.25 0) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
)
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.5 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-14_W7.62mm (layer F.Cu) (tedit 5FB6A63A) (tstamp 5FB68898)
(at 163.195 66.04)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FB50A31)
(fp_text reference U3 (at 3.81 -2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS32 (at 3.875 7.55 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_arc (start 2 2) (end 1.450001 2.774999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 2.775) (end 1.45 3.35) (layer F.SilkS) (width 0.12))
(fp_line (start 2.55 3.35) (end 2.55 2.8) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.55 3.35) (end 1.45 3.35) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.448537 3.320952) (end 2.548537 3.320952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.475 4.825) (end 4.925001 5.599999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_arc (start 6.025 6.175) (end 4.925 6.175) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_arc (start 4.923537 6.145952) (end 6.023537 6.145952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_line (start 6.025 6.175) (end 6.025 5.625) (layer F.SilkS) (width 0.12))
(fp_line (start 4.925 5.6) (end 4.925 6.175) (layer F.SilkS) (width 0.12))
(fp_line (start 1.175 2.375) (end 1.75 2.375) (layer F.SilkS) (width 0.12))
(fp_line (start 1.75 2.375) (end 1.75 2.925) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 2.875) (end 2.225 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 0) (end 1.175 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 4.275) (end 1.95 5.025) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 5.025) (end 1.175 5.025) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 7.15) (end 5.475 7.675) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 7.675) (end 6.425 7.675) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 5.1) (end 5.725 5.1) (layer F.SilkS) (width 0.12))
(fp_line (start 5.725 5.1) (end 5.725 5.75) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 2.55) (end 5.25 2.55) (layer F.SilkS) (width 0.12))
(fp_line (start 5.25 2.55) (end 5.25 5.7) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 12.772) (end 1.175 12.772) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 12.022) (end 1.95 12.772) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 7.747) (end 1.175 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 10.622) (end 2.225 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 1.75 10.122) (end 1.75 10.672) (layer F.SilkS) (width 0.12))
(fp_line (start 1.175 10.122) (end 1.75 10.122) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.448537 11.067952) (end 2.548537 11.067952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.55 11.097) (end 1.45 11.097) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_line (start 2.55 11.097) (end 2.55 10.547) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 10.522) (end 1.45 11.097) (layer F.SilkS) (width 0.12))
(fp_arc (start 2 9.747) (end 1.450001 10.521999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.475 12.445) (end 4.925001 13.219999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_line (start 4.925 13.22) (end 4.925 13.795) (layer F.SilkS) (width 0.12))
(fp_line (start 6.025 13.795) (end 6.025 13.245) (layer F.SilkS) (width 0.12))
(fp_arc (start 4.923537 13.765952) (end 6.023537 13.765952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 10.17) (end 5.25 10.17) (layer F.SilkS) (width 0.12))
(fp_line (start 5.725 12.72) (end 5.725 13.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 12.72) (end 5.725 12.72) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 15.295) (end 6.425 15.295) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 14.77) (end 5.475 15.295) (layer F.SilkS) (width 0.12))
(fp_line (start 5.25 10.17) (end 5.25 13.32) (layer F.SilkS) (width 0.12))
(fp_arc (start 6.025 13.795) (end 4.925 13.795) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(U3-Pad1)"))
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 96 "Net-(U3-Pad8)"))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(J0-Pad41)"))
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(J0-Pad41)"))
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 95 "Net-(U3-Pad3)"))
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(U3-Pad10)"))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(U0-Pad1)"))
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(U3-Pad10)"))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(J0-Pad2)"))
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 88 "Net-(U2-Pad8)"))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(U3-Pad1)"))
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(J0-Pad3)"))
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-14_W7.62mm (layer F.Cu) (tedit 5FB69AA2) (tstamp 5FB68876)
(at 177.8 66.04)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FD4E618)
(fp_text reference U2 (at 3.81 -2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS00 (at 3.875 7.75 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 7.62) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.55194 3.06832) (end 2.50444 3.06832) (layer F.SilkS) (width 0.12))
(fp_line (start 1.5494 3.08102) (end 1.5494 3.66776) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.03454 3.683) (end 1.5494 3.683) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.04724 4.35864) (end 2.062479 4.221481) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 2.52476 3.67538) (end 2.52476 3.0734) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.99898 11.72718) (end 1.51384 11.72718) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.01168 12.40282) (end 2.026919 12.265661) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 1.51638 11.1125) (end 2.46888 11.1125) (layer F.SilkS) (width 0.12))
(fp_line (start 2.4892 11.71956) (end 2.4892 11.11758) (layer F.SilkS) (width 0.12))
(fp_line (start 1.51384 11.1252) (end 1.51384 11.71194) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6769 6.4897) (end 5.19176 6.4897) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6896 7.16534) (end 5.704839 7.028181) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 5.1943 5.87502) (end 6.1468 5.87502) (layer F.SilkS) (width 0.12))
(fp_line (start 6.16712 6.48208) (end 6.16712 5.8801) (layer F.SilkS) (width 0.12))
(fp_line (start 5.19176 5.88772) (end 5.19176 6.47446) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6769 13.79982) (end 5.19176 13.79982) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6896 14.47546) (end 5.704839 14.338301) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 5.1943 13.18514) (end 6.1468 13.18514) (layer F.SilkS) (width 0.12))
(fp_line (start 6.16712 13.7922) (end 6.16712 13.19022) (layer F.SilkS) (width 0.12))
(fp_line (start 5.19176 13.19784) (end 5.19176 13.78458) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 0) (end 2.286 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 0) (end 2.286 3.048) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 2.54) (end 1.905 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 1.905 2.54) (end 1.905 3.048) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 5.08) (end 2.032 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 5.08) (end 2.032 4.572) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 11.049) (end 2.286 7.62) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 7.62) (end 1.143 7.62) (layer F.SilkS) (width 0.12))
(fp_line (start 1.778 11.049) (end 1.778 10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 1.778 10.16) (end 1.143 10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 12.573) (end 2.032 12.954) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 12.954) (end 1.143 12.954) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 5.842) (end 5.461 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 2.54) (end 6.477 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 5.842) (end 5.842 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 5.08) (end 6.477 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 6.477 7.747) (end 5.715 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 5.715 7.747) (end 5.715 7.366) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 13.081) (end 5.461 10.287) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 10.287) (end 6.477 10.287) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 13.081) (end 5.842 12.7) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 12.7) (end 6.477 12.7) (layer F.SilkS) (width 0.12))
(fp_line (start 6.477 15.367) (end 5.715 15.367) (layer F.SilkS) (width 0.12))
(fp_line (start 5.715 15.367) (end 5.715 14.605) (layer F.SilkS) (width 0.12))
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 "Net-(J0-Pad18)"))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(U0-Pad19)"))
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 "Net-(J0-Pad18)"))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 87 "Net-(U2-Pad3)"))
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(U0-Pad1)"))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 87 "Net-(U2-Pad3)"))
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(U0-Pad1)"))
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 87 "Net-(U2-Pad3)"))
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(U0-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(J0-Pad1)"))
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 88 "Net-(U2-Pad8)"))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(J0-Pad41)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm (layer F.Cu) (tedit 5FB69523) (tstamp 5FB68711)
(at 182.88 62.865 180)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /5FB81404)
(fp_text reference C3 (at 1.25 -2.55 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(fp_text value C (at 1.25 2.55 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 180) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 2 thru_hole circle (at 2.5 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
)
(module Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm (layer F.Cu) (tedit 5FB68D99) (tstamp 5FB686FC)
(at 188.595 93.98 270)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /5FB849D8)
(fp_text reference C2 (at 1.25 -2.55 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(fp_text value C (at 1.25 2.55 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 270) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 93 "Net-(C1-Pad1)"))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(module Connector_PinSocket_2.54mm:PinSocket_2x20_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A433) (tstamp 5FB687FC)
(at 110.49 108.585 180)
(descr "Through hole straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 2x20 2.54mm double row")
(path /5FA19C2C)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(fp_text reference J1 (at -1.27 -2.77) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text value Raspberry_Pi_2_3 (at -1.27 51.03) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_line (start -3.81 -1.27) (end 0.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.27 -1.27) (end 1.27 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.27) (end 1.27 49.53) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 49.53) (end -3.81 49.53) (layer F.Fab) (width 0.1))
(fp_line (start -3.81 49.53) (end -3.81 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -3.87 -1.33) (end -1.27 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -3.87 -1.33) (end -3.87 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start -3.87 49.59) (end 1.33 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -1.33) (end -1.27 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -4.34 -1.8) (end 1.76 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.76 -1.8) (end 1.76 50) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.76 50) (end -4.34 50) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.34 50) (end -4.34 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at -1.27 24.13 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 94 "Net-(C5-Pad1)"))
(pad 2 thru_hole oval (at -2.54 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 3 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 56 "Net-(J1-Pad3)"))
(pad 4 thru_hole oval (at -2.54 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 5 thru_hole oval (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 57 "Net-(J1-Pad5)"))
(pad 6 thru_hole oval (at -2.54 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 7 thru_hole oval (at 0 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 58 "Net-(J1-Pad7)"))
(pad 8 thru_hole oval (at -2.54 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 59 "Net-(J1-Pad8)"))
(pad 9 thru_hole oval (at 0 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 10 thru_hole oval (at -2.54 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 60 "Net-(J1-Pad10)"))
(pad 11 thru_hole oval (at 0 12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 61 "Net-(J1-Pad11)"))
(pad 12 thru_hole oval (at -2.54 12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 62 "Net-(J1-Pad12)"))
(pad 13 thru_hole oval (at 0 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 63 "Net-(J1-Pad13)"))
(pad 14 thru_hole oval (at -2.54 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 15 thru_hole oval (at 0 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 64 "Net-(J1-Pad15)"))
(pad 16 thru_hole oval (at -2.54 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 65 "Net-(J1-Pad16)"))
(pad 17 thru_hole oval (at 0 20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 94 "Net-(C5-Pad1)"))
(pad 18 thru_hole oval (at -2.54 20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 66 "Net-(J1-Pad18)"))
(pad 19 thru_hole oval (at 0 22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 67 "Net-(J1-Pad19)"))
(pad 20 thru_hole oval (at -2.54 22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 21 thru_hole oval (at 0 25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 68 "Net-(J1-Pad21)"))
(pad 22 thru_hole oval (at -2.54 25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 69 "Net-(J1-Pad22)"))
(pad 23 thru_hole oval (at 0 27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 70 "Net-(J1-Pad23)"))
(pad 24 thru_hole oval (at -2.54 27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 71 "Net-(J1-Pad24)"))
(pad 25 thru_hole oval (at 0 30.48 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 26 thru_hole oval (at -2.54 30.48 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 72 "Net-(J1-Pad26)"))
(pad 27 thru_hole oval (at 0 33.02 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 73 "Net-(J1-Pad27)"))
(pad 28 thru_hole oval (at -2.54 33.02 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 74 "Net-(J1-Pad28)"))
(pad 29 thru_hole oval (at 0 35.56 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 75 "Net-(J1-Pad29)"))
(pad 30 thru_hole oval (at -2.54 35.56 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 31 thru_hole oval (at 0 38.1 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 76 "Net-(J1-Pad31)"))
(pad 32 thru_hole oval (at -2.54 38.1 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 77 "Net-(J1-Pad32)"))
(pad 33 thru_hole oval (at 0 40.64 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 78 "Net-(J1-Pad33)"))
(pad 34 thru_hole oval (at -2.54 40.64 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 35 thru_hole oval (at 0 43.18 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 79 "Net-(J1-Pad35)"))
(pad 36 thru_hole oval (at -2.54 43.18 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 80 "Net-(J1-Pad36)"))
(pad 37 thru_hole oval (at 0 45.72 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 81 "Net-(J1-Pad37)"))
(pad 38 thru_hole oval (at -2.54 45.72 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 82 "Net-(J1-Pad38)"))
(pad 39 thru_hole oval (at 0 48.26 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 40 thru_hole oval (at -2.54 48.26 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 83 "Net-(J1-Pad40)"))
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_2x20_P2.54mm_Vertical.wrl
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB68824)
(at 124.46 99.695 90)
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FA15F43)
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(fp_text reference U0 (at 3.81 -2.33 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text value 74LS245 (at 3.81 25.19 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(U0-Pad1)"))
(pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(U0-Pad11)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 54 "Net-(J0-Pad49)"))
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(U0-Pad12)"))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 53 "Net-(J0-Pad48)"))
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(U0-Pad13)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 52 "Net-(J0-Pad47)"))
(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 "Net-(U0-Pad14)"))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 51 "Net-(J0-Pad46)"))
(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 50 "Net-(J0-Pad45)"))
(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U0-Pad16)"))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 49 "Net-(J0-Pad44)"))
(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(U0-Pad17)"))
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 48 "Net-(J0-Pad43)"))
(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U0-Pad18)"))
(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 85 "Net-(J0-Pad42)"))
(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(U0-Pad19)"))
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(module Package_DIP:DIP-28_W15.24mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB68854)
(at 185.42 87.63 270)
(descr "28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils)")
(tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil")
(path /5FA0EF8B)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(fp_text reference U1 (at 7.62 -2.33 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text value 2764 (at 7.62 35.35 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 -1.27) (end 14.985 34.29) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 34.29) (end 0.255 34.29) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 34.29) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.62 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 34.35) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 34.35) (end 14.08 34.35) (layer F.SilkS) (width 0.12))
(fp_line (start 14.08 34.35) (end 14.08 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 14.08 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 34.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 34.55) (end 16.3 34.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.3 34.55) (end 16.3 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.3 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 7.62 16.51 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 15 thru_hole oval (at 15.24 33.02 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 1 "Net-(U0-Pad15)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 "Net-(U1-Pad2)"))
(pad 16 thru_hole oval (at 15.24 30.48 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 3 "Net-(U0-Pad14)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(J0-Pad9)"))
(pad 17 thru_hole oval (at 15.24 27.94 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 5 "Net-(U0-Pad13)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(J0-Pad8)"))
(pad 18 thru_hole oval (at 15.24 25.4 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 7 "Net-(U0-Pad12)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 5 thru_hole oval (at 0 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 "Net-(J0-Pad7)"))
(pad 19 thru_hole oval (at 15.24 22.86 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 9 "Net-(U0-Pad11)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 6 thru_hole oval (at 0 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(J0-Pad6)"))
(pad 20 thru_hole oval (at 15.24 20.32 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(J0-Pad1)"))
(pad 7 thru_hole oval (at 0 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 "Net-(J0-Pad5)"))
(pad 21 thru_hole oval (at 15.24 17.78 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(J0-Pad12)"))
(pad 8 thru_hole oval (at 0 17.78 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(J0-Pad4)"))
(pad 22 thru_hole oval (at 15.24 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(J0-Pad1)"))
(pad 9 thru_hole oval (at 0 20.32 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(J0-Pad3)"))
(pad 23 thru_hole oval (at 15.24 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 "Net-(U1-Pad23)"))
(pad 10 thru_hole oval (at 0 22.86 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(J0-Pad2)"))
(pad 24 thru_hole oval (at 15.24 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 "Net-(J0-Pad11)"))
(pad 11 thru_hole oval (at 0 25.4 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U0-Pad18)"))
(pad 25 thru_hole oval (at 15.24 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(J0-Pad10)"))
(pad 12 thru_hole oval (at 0 27.94 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(U0-Pad17)"))
(pad 26 thru_hole oval (at 15.24 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 "Net-(U1-Pad26)"))
(pad 13 thru_hole oval (at 0 30.48 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U0-Pad16)"))
(pad 27 thru_hole oval (at 15.24 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(pad 14 thru_hole oval (at 0 33.02 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 28 thru_hole oval (at 15.24 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(C1-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-28_W15.24mm.wrl
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB688C0)
(at 124.46 86.36 90)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FA19168)
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(fp_text reference U4 (at 3.81 -2.33 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text value 74LVC245 (at 3.81 25.19 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 94 "Net-(C5-Pad1)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 92 "Net-(C1-Pad2)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 95 "Net-(U3-Pad3)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(U0-Pad11)"))
(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 58 "Net-(J1-Pad7)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(U0-Pad12)"))
(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 61 "Net-(J1-Pad11)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(U0-Pad13)"))
(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 63 "Net-(J1-Pad13)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 "Net-(U0-Pad14)"))
(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 64 "Net-(J1-Pad15)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 67 "Net-(J1-Pad19)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U0-Pad16)"))
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 68 "Net-(J1-Pad21)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(U0-Pad17)"))
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 70 "Net-(J1-Pad23)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U0-Pad18)"))
(pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 75 "Net-(J1-Pad29)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(net 92 "Net-(C1-Pad2)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB688E8)
(at 124.46 71.755 90)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FA1EB22)
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(fp_text reference U5 (at 3.81 -2.33 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_text value 74LVC374 (at 3.81 25.19 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 96 "Net-(U3-Pad8)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 76 "Net-(J1-Pad31)"))
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 83 "Net-(J1-Pad40)"))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update PCB component layout
2020-11-17 00:21:56 +00:00
(net 19 "Net-(U0-Pad18)"))
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 "Net-(U0-Pad14)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 "Net-(U0-Pad17)"))
(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 "Net-(U0-Pad13)"))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 78 "Net-(J1-Pad33)"))
(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 82 "Net-(J1-Pad38)"))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 79 "Net-(J1-Pad35)"))
(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 80 "Net-(J1-Pad36)"))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(U0-Pad16)"))
(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(U0-Pad12)"))
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(U0-Pad11)"))
(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 81 "Net-(J1-Pad37)"))
(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 77 "Net-(J1-Pad32)"))
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(C1-Pad2)"))
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 94 "Net-(C5-Pad1)"))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(gr_text "Initial Protoype 2020-Nov-19\n(c)2020 Terence J. Boldt" (at 142.367 106.68) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Update PCB footprints and layout
2020-11-19 16:18:17 +00:00
(gr_line (start 191.77 111.125) (end 191.77 58.42) (layer Edge.Cuts) (width 0.05) (tstamp 5FB6D31C))
(gr_text "74LVC374 Output Level Shifter" (at 136.144 67.945) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_text "74LVC245 Input Level Shifter" (at 135.89 82.677) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_text "74LS245 Data Bus Buffer" (at 135.636 96.012) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_text "Attach Raspberry Pi Zero W facing outward from card" (at 115.951 84.709 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_line (start 164.6355 68.718) (end 164.6355 67.794) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 165.633 74.7135) (xy 165.234 74.8815) (xy 164.7195 75.3855) (xy 164.6355 76.131)) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 169.2555 71.385) (xy 169.1715 72.1305) (xy 168.657 72.6345) (xy 168.258 72.8025)) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 168.258 72.8025) (xy 167.859 72.6345) (xy 167.3445 72.1305) (xy 167.2605 71.385)) (layer Dwgs.User) (width 0.14))
(gr_line (start 164.142 68.424) (end 164.142 66.744) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 68.424) (end 164.142 68.424) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 164.6355 67.794) (xy 165.213 68.0985) (xy 166.053 68.0985) (xy 166.6305 67.794)) (layer Dwgs.User) (width 0.14))
(gr_line (start 167.2605 78.798) (end 167.2605 79.722) (layer Dwgs.User) (width 0.14))
(gr_line (start 168.258 76.425) (end 168.258 77.349) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.749 79.092) (end 169.749 80.772) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 73.758) (end 165.633 73.758) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 167.2605 79.722) (xy 167.838 79.4175) (xy 168.678 79.4175) (xy 169.2555 79.722)) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 168.258 77.3805) (xy 167.859 77.5485) (xy 167.3445 78.0525) (xy 167.2605 78.798)) (layer Dwgs.User) (width 0.14))
(gr_line (start 164.142 78.105) (end 165.108 78.105) (layer Dwgs.User) (width 0.14))
(gr_line (start 167.733 81.759) (end 167.733 79.512) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 167.2605 70.461) (xy 167.838 70.7655) (xy 168.678 70.7655) (xy 169.2555 70.461)) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 65.757) (end 166.158 65.757) (layer Dwgs.User) (width 0.14))
(gr_line (start 166.158 79.092) (end 166.158 76.845) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 81.759) (end 167.733 81.759) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 68.424) (end 167.733 68.424) (layer Dwgs.User) (width 0.14))
(gr_line (start 167.2605 71.385) (end 167.2605 70.461) (layer Dwgs.User) (width 0.14))
(gr_line (start 164.142 76.425) (end 164.142 78.105) (layer Dwgs.User) (width 0.14))
(gr_line (start 164.6355 76.131) (end 164.6355 77.055) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 71.091) (end 165.633 71.091) (layer Dwgs.User) (width 0.14))
(gr_line (start 164.142 66.744) (end 165.108 66.744) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 169.2555 78.798) (xy 169.1715 78.0525) (xy 168.657 77.5485) (xy 168.258 77.3805)) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.749 80.772) (end 168.783 80.772) (layer Dwgs.User) (width 0.14))
(gr_line (start 167.733 68.424) (end 167.733 70.671) (layer Dwgs.User) (width 0.14))
(gr_line (start 165.108 66.744) (end 165.108 68.004) (layer Dwgs.User) (width 0.14))
(gr_line (start 165.633 71.091) (end 165.633 70.167) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 166.6305 68.718) (xy 166.5465 69.4635) (xy 166.032 69.9675) (xy 165.633 70.1355)) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 71.091) (end 169.749 71.091) (layer Dwgs.User) (width 0.14))
(gr_line (start 168.258 73.758) (end 168.258 72.834) (layer Dwgs.User) (width 0.14))
(gr_line (start 168.783 69.411) (end 168.783 70.671) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 79.092) (end 166.158 79.092) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 165.633 70.1355) (xy 165.234 69.9675) (xy 164.7195 69.4635) (xy 164.6355 68.718)) (layer Dwgs.User) (width 0.14))
(gr_line (start 165.633 73.758) (end 165.633 74.682) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 164.6355 77.055) (xy 165.213 76.7505) (xy 166.053 76.7505) (xy 166.6305 77.055)) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 76.425) (end 168.258 76.425) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 79.092) (end 169.749 79.092) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.2555 79.722) (end 169.2555 78.798) (layer Dwgs.User) (width 0.14))
(gr_line (start 166.6305 67.794) (end 166.6305 68.718) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.749 71.091) (end 169.749 69.411) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.749 69.411) (end 168.783 69.411) (layer Dwgs.User) (width 0.14))
(gr_curve (pts (xy 166.6305 76.131) (xy 166.5465 75.3855) (xy 166.032 74.8815) (xy 165.633 74.7135)) (layer Dwgs.User) (width 0.14))
(gr_line (start 163.5435 76.425) (end 164.142 76.425) (layer Dwgs.User) (width 0.14))
(gr_line (start 166.6305 77.055) (end 166.6305 76.131) (layer Dwgs.User) (width 0.14))
(gr_line (start 169.2555 70.461) (end 169.2555 71.385) (layer Dwgs.User) (width 0.14))
(gr_line (start 165.108 78.105) (end 165.108 76.845) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 73.758) (end 168.258 73.758) (layer Dwgs.User) (width 0.14))
(gr_line (start 166.158 65.757) (end 166.158 68.004) (layer Dwgs.User) (width 0.14))
(gr_line (start 168.783 80.772) (end 168.783 79.512) (layer Dwgs.User) (width 0.14))
(gr_text "27C64 EPROM\nFirmware at $Cn00 - $CnFF\nWhere n = slot number" (at 160.02 95.25) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify left))
)
Update schematics and board - Remove resistor voltage dividers - Change to 74LVC parts with +3.3V VCC - Remove control lines
2020-11-19 14:00:27 +00:00
(gr_line (start 123.19 119.38) (end 186.69 119.38) (layer Edge.Cuts) (width 0.05) (tstamp 5FB6A4EB))
(gr_line (start 122.555 118.745) (end 123.19 119.38) (layer Edge.Cuts) (width 0.05))
(gr_line (start 122.555 111.76) (end 122.555 118.745) (layer Edge.Cuts) (width 0.05))
(gr_line (start 107.95 111.76) (end 122.555 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 107.315 111.125) (end 107.95 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 107.315 58.42) (end 107.315 111.125) (layer Edge.Cuts) (width 0.05))
(gr_line (start 107.95 57.785) (end 107.315 58.42) (layer Edge.Cuts) (width 0.05))
(gr_line (start 191.135 57.785) (end 107.95 57.785) (layer Edge.Cuts) (width 0.05))
(gr_line (start 191.77 58.42) (end 191.135 57.785) (layer Edge.Cuts) (width 0.05))
(gr_line (start 191.135 111.76) (end 191.77 111.125) (layer Edge.Cuts) (width 0.05))
(gr_line (start 187.325 111.76) (end 191.135 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 187.325 118.745) (end 187.325 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 186.69 119.38) (end 187.325 118.745) (layer Edge.Cuts) (width 0.05))
(gr_line (start 191.77 57.785) (end 191.77 111.76) (layer Dwgs.User) (width 0.15))
(gr_line (start 107.315 57.785) (end 213.995 57.785) (layer Dwgs.User) (width 0.15))
(gr_line (start 107.315 113.03) (end 107.315 55.245) (layer Dwgs.User) (width 0.15))
(gr_line (start 121.285 111.76) (end 101.6 111.76) (layer Dwgs.User) (width 0.15))
(gr_line (start 189.23 111.76) (end 207.645 111.76) (layer Dwgs.User) (width 0.15))
(gr_line (start 188.595 111.76) (end 189.865 111.76) (layer Dwgs.User) (width 0.15))
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 137.16 88.9) (end 134.62 86.36) (width 0.1778) (layer B.Cu) (net 1))
(segment (start 137.16 92.075) (end 137.16 88.9) (width 0.1778) (layer B.Cu) (net 1))
(segment (start 135.686701 84.161929) (end 135.686701 77.266701) (width 0.1778) (layer B.Cu) (net 1))
(segment (start 134.62 85.22863) (end 135.686701 84.161929) (width 0.1778) (layer B.Cu) (net 1))
(segment (start 134.62 86.36) (end 134.62 85.22863) (width 0.1778) (layer B.Cu) (net 1))
(via (at 135.763 74.422) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 1))
(segment (start 135.763 77.190402) (end 135.763 74.422) (width 0.1778) (layer B.Cu) (net 1))
(segment (start 135.686701 77.266701) (end 135.763 77.190402) (width 0.1778) (layer B.Cu) (net 1))
(segment (start 141.440001 72.554999) (end 142.24 71.755) (width 0.1778) (layer F.Cu) (net 1))
(segment (start 139.953999 74.041001) (end 141.440001 72.554999) (width 0.1778) (layer F.Cu) (net 1))
(segment (start 136.143999 74.041001) (end 139.953999 74.041001) (width 0.1778) (layer F.Cu) (net 1))
(segment (start 135.763 74.422) (end 136.143999 74.041001) (width 0.1778) (layer F.Cu) (net 1))
(via (at 152.527 98.044) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 1))
(segment (start 152.4 98.171) (end 152.527 98.044) (width 0.1778) (layer B.Cu) (net 1))
(segment (start 152.4 102.87) (end 152.4 98.171) (width 0.1778) (layer B.Cu) (net 1))
(segment (start 137.287 92.202) (end 137.16 92.075) (width 0.1778) (layer B.Cu) (net 1))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(via (at 137.287 95.758) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 1))
(segment (start 139.573 98.044) (end 137.287 95.758) (width 0.1778) (layer F.Cu) (net 1))
(segment (start 140.97 98.044) (end 139.573 98.044) (width 0.1778) (layer F.Cu) (net 1))
(segment (start 152.527 98.044) (end 140.97 98.044) (width 0.1778) (layer F.Cu) (net 1))
(segment (start 137.16 95.631) (end 137.287 95.758) (width 0.1778) (layer B.Cu) (net 1))
(segment (start 137.16 92.075) (end 137.16 95.631) (width 0.1778) (layer B.Cu) (net 1))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 139.7 88.9) (end 137.16 86.36) (width 0.1778) (layer B.Cu) (net 3))
(segment (start 139.7 92.075) (end 139.7 88.9) (width 0.1778) (layer B.Cu) (net 3))
(segment (start 138.226701 85.293299) (end 138.226701 66.217701) (width 0.1778) (layer B.Cu) (net 3))
(segment (start 137.16 86.36) (end 138.226701 85.293299) (width 0.1778) (layer B.Cu) (net 3))
(via (at 138.176 66.167) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 3))
(segment (start 138.226701 66.217701) (end 138.176 66.167) (width 0.1778) (layer B.Cu) (net 3))
(segment (start 140.208 66.167) (end 142.24 64.135) (width 0.1778) (layer F.Cu) (net 3))
(segment (start 138.176 66.167) (end 140.208 66.167) (width 0.1778) (layer F.Cu) (net 3))
(via (at 153.67 97.409) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 3))
(segment (start 154.94 98.679) (end 153.67 97.409) (width 0.1778) (layer B.Cu) (net 3))
(segment (start 154.94 102.87) (end 154.94 98.679) (width 0.1778) (layer B.Cu) (net 3))
(segment (start 153.67 97.409) (end 153.289001 97.028001) (width 0.1778) (layer F.Cu) (net 3))
(segment (start 139.827 92.202) (end 139.7 92.075) (width 0.1778) (layer B.Cu) (net 3))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 139.7 95.123) (end 140.081 95.504) (width 0.1778) (layer B.Cu) (net 3))
(via (at 140.081 95.504) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 3))
(segment (start 139.7 92.075) (end 139.7 95.123) (width 0.1778) (layer B.Cu) (net 3))
(segment (start 142.113 97.028) (end 140.080999 97.028001) (width 0.1778) (layer F.Cu) (net 3))
(segment (start 153.289001 97.028001) (end 142.113 97.028) (width 0.1778) (layer F.Cu) (net 3))
(segment (start 141.605 97.028) (end 140.081 95.504) (width 0.1778) (layer F.Cu) (net 3))
(segment (start 142.113 97.028) (end 141.605 97.028) (width 0.1778) (layer F.Cu) (net 3))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(via (at 180.467 108.204) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 4))
(segment (start 181.406701 107.264299) (end 180.467 108.204) (width 0.1778) (layer B.Cu) (net 4))
(segment (start 181.406701 88.696701) (end 181.406701 107.264299) (width 0.1778) (layer B.Cu) (net 4))
(segment (start 180.34 87.63) (end 181.406701 88.696701) (width 0.1778) (layer B.Cu) (net 4))
(segment (start 180.467 108.204) (end 147.574 108.204) (width 0.1778) (layer F.Cu) (net 4))
(segment (start 144.855001 110.922999) (end 144.855001 115.57) (width 0.1778) (layer F.Cu) (net 4))
(segment (start 147.574 108.204) (end 144.855001 110.922999) (width 0.1778) (layer F.Cu) (net 4))
(segment (start 142.24 88.9) (end 139.7 86.36) (width 0.1778) (layer B.Cu) (net 5))
(segment (start 142.24 92.075) (end 142.24 88.9) (width 0.1778) (layer B.Cu) (net 5))
(via (at 156.718 96.901) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 5))
(segment (start 157.48 97.663) (end 156.718 96.901) (width 0.1778) (layer B.Cu) (net 5))
(segment (start 157.48 102.87) (end 157.48 97.663) (width 0.1778) (layer B.Cu) (net 5))
(segment (start 156.337001 96.520001) (end 143.382999 96.520001) (width 0.1778) (layer F.Cu) (net 5))
(segment (start 156.718 96.901) (end 156.337001 96.520001) (width 0.1778) (layer F.Cu) (net 5))
(via (at 142.367 96.139) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 5))
(segment (start 143.001998 96.139) (end 142.367 96.139) (width 0.1778) (layer F.Cu) (net 5))
(segment (start 143.382999 96.520001) (end 143.001998 96.139) (width 0.1778) (layer F.Cu) (net 5))
(segment (start 142.367 92.202) (end 142.24 92.075) (width 0.1778) (layer B.Cu) (net 5))
(segment (start 142.367 96.139) (end 142.367 92.202) (width 0.1778) (layer B.Cu) (net 5))
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(segment (start 138.900001 64.934999) (end 139.7 64.135) (width 0.1778) (layer B.Cu) (net 5))
(segment (start 138.900001 70.976281) (end 138.900001 64.934999) (width 0.1778) (layer B.Cu) (net 5))
(segment (start 138.633299 71.242983) (end 138.900001 70.976281) (width 0.1778) (layer B.Cu) (net 5))
(segment (start 138.633299 85.293299) (end 138.633299 71.242983) (width 0.1778) (layer B.Cu) (net 5))
(segment (start 139.7 86.36) (end 138.633299 85.293299) (width 0.1778) (layer B.Cu) (net 5))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 142.315001 115.57) (end 142.315001 111.76) (width 0.1778) (layer F.Cu) (net 6))
(segment (start 142.315001 111.76) (end 146.252001 107.823) (width 0.1778) (layer F.Cu) (net 6))
(via (at 178.562 107.315) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 6))
(segment (start 178.054 107.823) (end 178.562 107.315) (width 0.1778) (layer F.Cu) (net 6))
(segment (start 146.252001 107.823) (end 178.054 107.823) (width 0.1778) (layer F.Cu) (net 6))
(segment (start 178.866701 88.696701) (end 177.8 87.63) (width 0.1778) (layer B.Cu) (net 6))
(segment (start 178.866701 106.471484) (end 178.866701 88.696701) (width 0.1778) (layer B.Cu) (net 6))
(segment (start 178.562 106.776185) (end 178.866701 106.471484) (width 0.1778) (layer B.Cu) (net 6))
(segment (start 178.562 107.315) (end 178.562 106.776185) (width 0.1778) (layer B.Cu) (net 6))
(segment (start 144.78 88.9) (end 142.24 86.36) (width 0.1778) (layer B.Cu) (net 7))
(segment (start 144.78 92.075) (end 144.78 88.9) (width 0.1778) (layer B.Cu) (net 7))
(via (at 145.288 95.758) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 7))
(segment (start 144.78 95.25) (end 145.288 95.758) (width 0.1778) (layer B.Cu) (net 7))
(segment (start 144.78 92.075) (end 144.78 95.25) (width 0.1778) (layer B.Cu) (net 7))
(via (at 159.258 96.266) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 7))
(segment (start 158.75 95.758) (end 159.258 96.266) (width 0.1778) (layer F.Cu) (net 7))
(segment (start 145.288 95.758) (end 158.75 95.758) (width 0.1778) (layer F.Cu) (net 7))
(segment (start 160.02 97.028) (end 160.02 102.87) (width 0.1778) (layer B.Cu) (net 7))
(segment (start 159.258 96.266) (end 160.02 97.028) (width 0.1778) (layer B.Cu) (net 7))
(segment (start 142.24 86.36) (end 141.173299 85.293299) (width 0.1778) (layer B.Cu) (net 7))
(via (at 141.351 66.802) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 7))
(segment (start 141.173299 66.979701) (end 141.351 66.802) (width 0.1778) (layer B.Cu) (net 7))
(segment (start 132.207 64.262) (end 132.08 64.135) (width 0.1778) (layer B.Cu) (net 7))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 140.970001 67.182999) (end 141.351 66.802) (width 0.1778) (layer F.Cu) (net 7))
(segment (start 138.233401 67.182999) (end 140.970001 67.182999) (width 0.1778) (layer F.Cu) (net 7))
(segment (start 136.093299 65.042897) (end 138.233401 67.182999) (width 0.1778) (layer F.Cu) (net 7))
(segment (start 136.093299 64.084299) (end 136.093299 65.042897) (width 0.1778) (layer F.Cu) (net 7))
(segment (start 135.077299 63.068299) (end 136.093299 64.084299) (width 0.1778) (layer F.Cu) (net 7))
(segment (start 133.146701 63.068299) (end 135.077299 63.068299) (width 0.1778) (layer F.Cu) (net 7))
(segment (start 132.08 64.135) (end 133.146701 63.068299) (width 0.1778) (layer F.Cu) (net 7))
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(segment (start 140.817689 81.000689) (end 141.224 81.407) (width 0.1778) (layer B.Cu) (net 7))
(segment (start 140.817689 67.335311) (end 140.817689 81.000689) (width 0.1778) (layer B.Cu) (net 7))
(segment (start 141.351 66.802) (end 140.817689 67.335311) (width 0.1778) (layer B.Cu) (net 7))
(segment (start 141.173299 85.293299) (end 141.224 81.407) (width 0.1778) (layer B.Cu) (net 7))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 139.775001 115.57) (end 139.775001 111.887) (width 0.1778) (layer F.Cu) (net 8))
(segment (start 139.775001 111.887) (end 144.194611 107.46739) (width 0.1778) (layer F.Cu) (net 8))
(via (at 174.244 106.807) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 8))
(segment (start 173.58361 107.46739) (end 174.244 106.807) (width 0.1778) (layer F.Cu) (net 8))
(segment (start 144.194611 107.46739) (end 173.58361 107.46739) (width 0.1778) (layer F.Cu) (net 8))
(segment (start 174.460001 88.429999) (end 175.26 87.63) (width 0.1778) (layer B.Cu) (net 8))
(segment (start 173.863001 89.026999) (end 174.460001 88.429999) (width 0.1778) (layer B.Cu) (net 8))
(segment (start 173.863001 106.426001) (end 173.863001 89.026999) (width 0.1778) (layer B.Cu) (net 8))
(segment (start 174.244 106.807) (end 173.863001 106.426001) (width 0.1778) (layer B.Cu) (net 8))
(segment (start 147.32 88.9) (end 144.78 86.36) (width 0.1778) (layer B.Cu) (net 9))
(segment (start 147.32 92.075) (end 147.32 88.9) (width 0.1778) (layer B.Cu) (net 9))
(via (at 161.544 95.25) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 9))
(segment (start 162.56 96.266) (end 161.544 95.25) (width 0.1778) (layer B.Cu) (net 9))
(segment (start 162.56 102.87) (end 162.56 96.266) (width 0.1778) (layer B.Cu) (net 9))
(via (at 146.939 95.0214) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 9))
(segment (start 147.1676 95.25) (end 146.939 95.0214) (width 0.1778) (layer F.Cu) (net 9))
(segment (start 161.544 95.25) (end 147.1676 95.25) (width 0.1778) (layer F.Cu) (net 9))
(segment (start 147.32 94.6404) (end 147.32 92.075) (width 0.1778) (layer B.Cu) (net 9))
(segment (start 146.939 95.0214) (end 147.32 94.6404) (width 0.1778) (layer B.Cu) (net 9))
(via (at 131.699 69.088) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 9))
(segment (start 129.54 66.929) (end 131.699 69.088) (width 0.1778) (layer B.Cu) (net 9))
(segment (start 129.54 64.135) (end 129.54 66.929) (width 0.1778) (layer B.Cu) (net 9))
(via (at 143.002 69.088) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 9))
(segment (start 143.980001 85.560001) (end 144.78 86.36) (width 0.1778) (layer B.Cu) (net 9))
(segment (start 143.306701 84.886701) (end 143.980001 85.560001) (width 0.1778) (layer B.Cu) (net 9))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 132.321211 69.088) (end 131.699 69.088) (width 0.1778) (layer F.Cu) (net 9))
(segment (start 132.842 69.608789) (end 132.321211 69.088) (width 0.1778) (layer F.Cu) (net 9))
(segment (start 142.481211 69.608789) (end 132.842 69.608789) (width 0.1778) (layer F.Cu) (net 9))
(segment (start 143.002 69.088) (end 142.481211 69.608789) (width 0.1778) (layer F.Cu) (net 9))
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(segment (start 143.383 78.304282) (end 143.383 78.74) (width 0.1778) (layer B.Cu) (net 9))
(segment (start 141.173299 76.094581) (end 143.383 78.304282) (width 0.1778) (layer B.Cu) (net 9))
(segment (start 141.173299 70.916701) (end 141.173299 76.094581) (width 0.1778) (layer B.Cu) (net 9))
(segment (start 143.002 69.088) (end 141.173299 70.916701) (width 0.1778) (layer B.Cu) (net 9))
(segment (start 143.383 78.74) (end 143.306701 84.886701) (width 0.1778) (layer B.Cu) (net 9))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(via (at 171.704 106.68) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 10))
(segment (start 171.653299 88.696701) (end 171.653299 106.629299) (width 0.1778) (layer B.Cu) (net 10))
(segment (start 171.653299 106.629299) (end 171.704 106.68) (width 0.1778) (layer B.Cu) (net 10))
(segment (start 172.72 87.63) (end 171.653299 88.696701) (width 0.1778) (layer B.Cu) (net 10))
(segment (start 137.235001 111.76) (end 137.235001 115.57) (width 0.1778) (layer F.Cu) (net 10))
(segment (start 142.315001 106.68) (end 137.235001 111.76) (width 0.1778) (layer F.Cu) (net 10))
(segment (start 171.704 106.68) (end 142.315001 106.68) (width 0.1778) (layer F.Cu) (net 10))
(segment (start 165.899999 102.070001) (end 165.1 102.87) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 166.166701 101.803299) (end 165.899999 102.070001) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 169.113299 101.803299) (end 166.166701 101.803299) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 170.18 102.87) (end 169.113299 101.803299) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 165.1 102.87) (end 163.576 104.394) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 124.333 115.367999) (end 124.535001 115.57) (width 0.1778) (layer F.Cu) (net 11))
(via (at 176.784 99.187) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 11))
(segment (start 176.657099 99.060099) (end 176.784 99.187) (width 0.1778) (layer B.Cu) (net 11))
(segment (start 176.657099 69.722901) (end 176.657099 99.060099) (width 0.1778) (layer B.Cu) (net 11))
(segment (start 177.8 68.58) (end 176.657099 69.722901) (width 0.1778) (layer B.Cu) (net 11))
(segment (start 176.784 99.187) (end 171.323 99.187) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 170.18 100.33) (end 170.18 102.87) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 171.323 99.187) (end 170.18 100.33) (width 0.1778) (layer F.Cu) (net 11))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 125.526701 110.439299) (end 124.333 111.633) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 127.959103 94.856299) (end 125.526701 97.288701) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 125.526701 97.288701) (end 125.526701 110.439299) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 128.580897 94.856299) (end 127.959103 94.856299) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 130.606701 100.207017) (end 130.606701 96.882103) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 130.606701 96.882103) (end 128.580897 94.856299) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 134.793684 104.394) (end 130.606701 100.207017) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 163.576 104.394) (end 134.793684 104.394) (width 0.1778) (layer F.Cu) (net 11))
(segment (start 124.333 111.633) (end 124.333 115.367999) (width 0.1778) (layer F.Cu) (net 11))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(via (at 169.037 105.918) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 12))
(segment (start 169.037 88.773) (end 169.037 105.918) (width 0.1778) (layer B.Cu) (net 12))
(segment (start 170.18 87.63) (end 169.037 88.773) (width 0.1778) (layer B.Cu) (net 12))
(segment (start 169.037 105.918) (end 168.63061 106.32439) (width 0.1778) (layer F.Cu) (net 12))
(segment (start 134.695001 111.76) (end 134.695001 115.57) (width 0.1778) (layer F.Cu) (net 12))
(segment (start 140.130611 106.32439) (end 134.695001 111.76) (width 0.1778) (layer F.Cu) (net 12))
(segment (start 168.63061 106.32439) (end 140.130611 106.32439) (width 0.1778) (layer F.Cu) (net 12))
(via (at 166.751 110.871) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 13))
(segment (start 167.64 109.982) (end 166.751 110.871) (width 0.1778) (layer B.Cu) (net 13))
(segment (start 167.64 102.87) (end 167.64 109.982) (width 0.1778) (layer B.Cu) (net 13))
(segment (start 152.475001 111.430999) (end 152.475001 115.57) (width 0.1778) (layer F.Cu) (net 13))
(segment (start 153.035 110.871) (end 152.475001 111.430999) (width 0.1778) (layer F.Cu) (net 13))
(segment (start 166.751 110.871) (end 153.035 110.871) (width 0.1778) (layer F.Cu) (net 13))
(via (at 166.624 105.537) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 14))
(segment (start 166.573299 105.486299) (end 166.624 105.537) (width 0.1778) (layer B.Cu) (net 14))
(segment (start 166.573299 88.696701) (end 166.573299 105.486299) (width 0.1778) (layer B.Cu) (net 14))
(segment (start 167.64 87.63) (end 166.573299 88.696701) (width 0.1778) (layer B.Cu) (net 14))
(segment (start 132.155001 111.76) (end 132.155001 115.57) (width 0.1778) (layer F.Cu) (net 14))
(segment (start 138.378001 105.537) (end 132.155001 111.76) (width 0.1778) (layer F.Cu) (net 14))
(segment (start 166.624 105.537) (end 138.378001 105.537) (width 0.1778) (layer F.Cu) (net 14))
(via (at 164.465 104.8893) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 15))
(segment (start 164.033299 104.457599) (end 164.465 104.8893) (width 0.1778) (layer B.Cu) (net 15))
(segment (start 164.033299 88.696701) (end 164.033299 104.457599) (width 0.1778) (layer B.Cu) (net 15))
(segment (start 165.1 87.63) (end 164.033299 88.696701) (width 0.1778) (layer B.Cu) (net 15))
(segment (start 129.615001 111.76) (end 129.615001 115.57) (width 0.1778) (layer F.Cu) (net 15))
(segment (start 136.485701 104.8893) (end 129.615001 111.76) (width 0.1778) (layer F.Cu) (net 15))
(segment (start 164.465 104.8893) (end 136.485701 104.8893) (width 0.1778) (layer F.Cu) (net 15))
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(segment (start 165.1 74.295) (end 165.1 87.63) (width 0.1778) (layer B.Cu) (net 15))
(segment (start 168.148 71.247) (end 168.2115 71.1835) (width 0.1778) (layer B.Cu) (net 15))
(segment (start 168.2115 71.1835) (end 165.1 74.295) (width 0.1778) (layer B.Cu) (net 15))
(segment (start 168.2115 71.1835) (end 170.815 68.58) (width 0.1778) (layer B.Cu) (net 15))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(via (at 160.147 76.835) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 17))
(segment (start 160.782 76.2) (end 160.147 76.835) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 163.195 76.2) (end 160.782 76.2) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 160.147 85.217) (end 162.56 87.63) (width 0.1778) (layer B.Cu) (net 17))
(segment (start 160.147 76.835) (end 160.147 85.217) (width 0.1778) (layer B.Cu) (net 17))
(via (at 127.635 89.789) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 17))
(segment (start 127.075001 111.76) (end 127.075001 115.57) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 127.075001 110.765184) (end 127.075001 111.76) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 127.731185 110.109) (end 127.075001 110.765184) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 127.635 89.789) (end 128.27 89.154) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 141.351 89.154) (end 141.986 89.789) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 128.27 89.154) (end 141.351 89.154) (width 0.1778) (layer F.Cu) (net 17))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(via (at 128.27 95.504) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 17))
(segment (start 128.27 109.570185) (end 128.27 95.504) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 127.731185 110.109) (end 128.27 109.570185) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 128.27 90.424) (end 127.635 89.789) (width 0.1778) (layer B.Cu) (net 17))
(segment (start 128.27 95.504) (end 128.27 90.424) (width 0.1778) (layer B.Cu) (net 17))
(via (at 161.29 91.821) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 17))
(segment (start 162.56 90.551) (end 161.29 91.821) (width 0.1778) (layer B.Cu) (net 17))
(segment (start 162.56 87.63) (end 162.56 90.551) (width 0.1778) (layer B.Cu) (net 17))
(segment (start 148.971 91.821) (end 146.939 89.789) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 161.29 91.821) (end 148.971 91.821) (width 0.1778) (layer F.Cu) (net 17))
(segment (start 146.939 89.789) (end 141.986 89.789) (width 0.1778) (layer F.Cu) (net 17))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 149.935001 115.57) (end 149.935001 111.76) (width 0.1778) (layer F.Cu) (net 18))
(segment (start 149.935001 111.76) (end 149.935001 111.684999) (width 0.1778) (layer F.Cu) (net 18))
(segment (start 151.638 109.982) (end 175.387 109.982) (width 0.1778) (layer F.Cu) (net 18))
(via (at 175.387 109.982) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 18))
(segment (start 149.935001 111.684999) (end 151.638 109.982) (width 0.1778) (layer F.Cu) (net 18))
(segment (start 175.387 102.997) (end 175.26 102.87) (width 0.1778) (layer B.Cu) (net 18))
(segment (start 175.387 109.982) (end 175.387 102.997) (width 0.1778) (layer B.Cu) (net 18))
(segment (start 129.54 88.9) (end 127 86.36) (width 0.1778) (layer B.Cu) (net 19))
(segment (start 129.54 92.075) (end 129.54 88.9) (width 0.1778) (layer B.Cu) (net 19))
(segment (start 128.473299 84.886701) (end 128.473299 75.234701) (width 0.1778) (layer B.Cu) (net 19))
(segment (start 127 86.36) (end 128.473299 84.886701) (width 0.1778) (layer B.Cu) (net 19))
(segment (start 129.54 74.168) (end 129.54 71.755) (width 0.1778) (layer B.Cu) (net 19))
(segment (start 128.473299 75.234701) (end 129.54 74.168) (width 0.1778) (layer B.Cu) (net 19))
(segment (start 127.799999 87.159999) (end 127 86.36) (width 0.1778) (layer F.Cu) (net 19))
(segment (start 129.412901 88.772901) (end 127.799999 87.159999) (width 0.1778) (layer F.Cu) (net 19))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 156.006701 87.117983) (end 154.461427 85.572709) (width 0.1778) (layer F.Cu) (net 19))
(segment (start 129.413 88.773) (end 127 86.36) (width 0.1778) (layer F.Cu) (net 19))
(segment (start 156.006701 87.807503) (end 156.006701 87.117983) (width 0.1778) (layer F.Cu) (net 19))
(segment (start 156.972099 88.772901) (end 156.006701 87.807503) (width 0.1778) (layer F.Cu) (net 19))
(segment (start 158.877099 88.772901) (end 156.972099 88.772901) (width 0.1778) (layer F.Cu) (net 19))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 160.02 87.63) (end 158.877099 88.772901) (width 0.1778) (layer F.Cu) (net 19))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(via (at 153.289 86.233) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 19))
(segment (start 153.949291 85.572709) (end 153.289 86.233) (width 0.1778) (layer F.Cu) (net 19))
(segment (start 154.461427 85.572709) (end 153.949291 85.572709) (width 0.1778) (layer F.Cu) (net 19))
(via (at 150.622 89.027) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 19))
(segment (start 150.622 87.716506) (end 150.622 89.027) (width 0.1778) (layer B.Cu) (net 19))
(segment (start 152.105506 86.233) (end 150.622 87.716506) (width 0.1778) (layer B.Cu) (net 19))
(segment (start 153.289 86.233) (end 152.105506 86.233) (width 0.1778) (layer B.Cu) (net 19))
(segment (start 140.334999 88.646001) (end 140.208 88.773) (width 0.1778) (layer F.Cu) (net 19))
(segment (start 150.241001 88.646001) (end 140.334999 88.646001) (width 0.1778) (layer F.Cu) (net 19))
(segment (start 150.622 89.027) (end 150.241001 88.646001) (width 0.1778) (layer F.Cu) (net 19))
(segment (start 140.208 88.773) (end 129.413 88.773) (width 0.1778) (layer F.Cu) (net 19))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(via (at 176.657 109.347) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 20))
(segment (start 177.8 108.204) (end 176.657 109.347) (width 0.1778) (layer B.Cu) (net 20))
(segment (start 177.8 102.87) (end 177.8 108.204) (width 0.1778) (layer B.Cu) (net 20))
(segment (start 147.395001 111.76) (end 147.395001 115.57) (width 0.1778) (layer F.Cu) (net 20))
(segment (start 150.189 108.966001) (end 147.395001 111.76) (width 0.1778) (layer F.Cu) (net 20))
(segment (start 176.276001 108.966001) (end 150.189 108.966001) (width 0.1778) (layer F.Cu) (net 20))
(segment (start 176.657 109.347) (end 176.276001 108.966001) (width 0.1778) (layer F.Cu) (net 20))
(segment (start 132.08 88.9) (end 129.54 86.36) (width 0.1778) (layer B.Cu) (net 21))
(segment (start 132.08 92.075) (end 132.08 88.9) (width 0.1778) (layer B.Cu) (net 21))
(segment (start 130.606701 85.293299) (end 130.606701 76.504701) (width 0.1778) (layer B.Cu) (net 21))
(segment (start 129.54 86.36) (end 130.606701 85.293299) (width 0.1778) (layer B.Cu) (net 21))
(segment (start 132.08 75.031402) (end 132.08 71.755) (width 0.1778) (layer B.Cu) (net 21))
(segment (start 130.606701 76.504701) (end 132.08 75.031402) (width 0.1778) (layer B.Cu) (net 21))
(segment (start 130.682901 85.217099) (end 130.339999 85.560001) (width 0.1778) (layer F.Cu) (net 21))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 141.859 85.217) (end 130.682901 85.217099) (width 0.1778) (layer F.Cu) (net 21))
(segment (start 142.24 85.217) (end 141.859 85.217) (width 0.1778) (layer F.Cu) (net 21))
(segment (start 130.339999 85.560001) (end 129.54 86.36) (width 0.1778) (layer F.Cu) (net 21))
(segment (start 153.883506 90.805) (end 157.607 90.805) (width 0.1778) (layer F.Cu) (net 21))
(segment (start 151.257099 88.178593) (end 153.883506 90.805) (width 0.1778) (layer F.Cu) (net 21))
(segment (start 147.447099 88.178593) (end 151.257099 88.178593) (width 0.1778) (layer F.Cu) (net 21))
(segment (start 146.177099 86.908593) (end 147.447099 88.178593) (width 0.1778) (layer F.Cu) (net 21))
(segment (start 146.177099 85.811407) (end 146.177099 86.908593) (width 0.1778) (layer F.Cu) (net 21))
(segment (start 145.582692 85.217) (end 146.177099 85.811407) (width 0.1778) (layer F.Cu) (net 21))
(via (at 157.607 90.805) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 21))
(segment (start 142.24 85.217) (end 145.582692 85.217) (width 0.1778) (layer F.Cu) (net 21))
(segment (start 157.607 87.757) (end 157.48 87.63) (width 0.1778) (layer B.Cu) (net 21))
(segment (start 157.607 90.805) (end 157.607 87.757) (width 0.1778) (layer B.Cu) (net 21))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 134.62 88.9) (end 132.08 86.36) (width 0.1778) (layer B.Cu) (net 23))
(segment (start 134.62 92.075) (end 134.62 88.9) (width 0.1778) (layer B.Cu) (net 23))
(via (at 132.969 73.406) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 23))
(segment (start 133.146701 73.583701) (end 132.969 73.406) (width 0.1778) (layer B.Cu) (net 23))
(segment (start 133.146701 85.293299) (end 133.146701 73.583701) (width 0.1778) (layer B.Cu) (net 23))
(segment (start 132.08 86.36) (end 133.146701 85.293299) (width 0.1778) (layer B.Cu) (net 23))
(segment (start 138.049 73.406) (end 139.7 71.755) (width 0.1778) (layer F.Cu) (net 23))
(segment (start 132.969 73.406) (end 138.049 73.406) (width 0.1778) (layer F.Cu) (net 23))
(segment (start 154.94 87.63) (end 154.813 87.757) (width 0.1778) (layer F.Cu) (net 23))
(via (at 155.194 74.295) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 23))
(segment (start 154.94 74.549) (end 155.194 74.295) (width 0.1778) (layer B.Cu) (net 23))
(segment (start 154.94 87.63) (end 154.94 74.549) (width 0.1778) (layer B.Cu) (net 23))
(segment (start 140.766701 70.688299) (end 140.499999 70.955001) (width 0.1778) (layer F.Cu) (net 23))
(segment (start 140.499999 70.955001) (end 139.7 71.755) (width 0.1778) (layer F.Cu) (net 23))
(segment (start 142.752017 70.688299) (end 140.766701 70.688299) (width 0.1778) (layer F.Cu) (net 23))
(segment (start 143.306701 71.242983) (end 142.752017 70.688299) (width 0.1778) (layer F.Cu) (net 23))
(segment (start 143.306701 72.267017) (end 143.306701 71.242983) (width 0.1778) (layer F.Cu) (net 23))
(segment (start 145.334684 74.295) (end 143.306701 72.267017) (width 0.1778) (layer F.Cu) (net 23))
(segment (start 155.194 74.295) (end 145.334684 74.295) (width 0.1778) (layer F.Cu) (net 23))
(segment (start 167.715001 115.57) (end 167.715001 111.887) (width 0.1778) (layer F.Cu) (net 29))
(segment (start 167.715001 111.887) (end 167.715001 111.557999) (width 0.1778) (layer F.Cu) (net 29))
(segment (start 176.898299 110.629701) (end 178.054 109.474) (width 0.1778) (layer F.Cu) (net 29))
(segment (start 168.643299 110.629701) (end 176.898299 110.629701) (width 0.1778) (layer F.Cu) (net 29))
(via (at 178.054 109.474) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 29))
(segment (start 167.715001 111.557999) (end 168.643299 110.629701) (width 0.1778) (layer F.Cu) (net 29))
(segment (start 185.42 68.58) (end 185.42 68.707) (width 0.1778) (layer B.Cu) (net 29))
(segment (start 185.42 68.707) (end 185.42 71.12) (width 0.1778) (layer B.Cu) (net 29))
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(segment (start 179.273299 85.775701) (end 179.273299 108.254701) (width 0.1778) (layer B.Cu) (net 29))
(segment (start 183.769 85.09) (end 179.959 85.09) (width 0.1778) (layer B.Cu) (net 29))
(segment (start 179.273299 108.254701) (end 178.054 109.474) (width 0.1778) (layer B.Cu) (net 29))
(segment (start 184.149999 72.390001) (end 184.149999 84.709001) (width 0.1778) (layer B.Cu) (net 29))
(segment (start 179.959 85.09) (end 179.273299 85.775701) (width 0.1778) (layer B.Cu) (net 29))
(segment (start 184.149999 84.709001) (end 183.769 85.09) (width 0.1778) (layer B.Cu) (net 29))
(segment (start 185.42 71.12) (end 184.149999 72.390001) (width 0.1778) (layer B.Cu) (net 29))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 180.415001 115.57) (end 180.415001 110.871) (width 0.1778) (layer B.Cu) (net 34))
(via (at 180.415001 110.871) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 34))
(segment (start 180.415001 110.871) (end 180.415001 115.57) (width 0.1778) (layer F.Cu) (net 34))
(segment (start 182.955001 115.57) (end 182.955001 110.871) (width 0.1778) (layer F.Cu) (net 35))
(via (at 182.955001 110.871) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 35))
(segment (start 182.955001 110.871) (end 182.955001 115.57) (width 0.1778) (layer B.Cu) (net 35))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 152.475001 115.57) (end 152.475001 112.268) (width 0.1778) (layer B.Cu) (net 46))
(segment (start 142.315001 99.770001) (end 142.24 99.695) (width 0.1778) (layer B.Cu) (net 48))
(segment (start 142.315001 115.57) (end 142.315001 99.770001) (width 0.1778) (layer B.Cu) (net 48))
(segment (start 139.775001 99.770001) (end 139.7 99.695) (width 0.1778) (layer B.Cu) (net 49))
(segment (start 139.775001 115.57) (end 139.775001 99.770001) (width 0.1778) (layer B.Cu) (net 49))
(segment (start 137.235001 99.770001) (end 137.16 99.695) (width 0.1778) (layer B.Cu) (net 50))
(segment (start 137.235001 115.57) (end 137.235001 99.770001) (width 0.1778) (layer B.Cu) (net 50))
(segment (start 134.695001 99.770001) (end 134.62 99.695) (width 0.1778) (layer B.Cu) (net 51))
(segment (start 134.695001 115.57) (end 134.695001 99.770001) (width 0.1778) (layer B.Cu) (net 51))
(segment (start 132.155001 99.770001) (end 132.08 99.695) (width 0.1778) (layer B.Cu) (net 52))
(segment (start 132.155001 115.57) (end 132.155001 99.770001) (width 0.1778) (layer B.Cu) (net 52))
(segment (start 129.615001 99.770001) (end 129.54 99.695) (width 0.1778) (layer B.Cu) (net 53))
(segment (start 129.615001 115.57) (end 129.615001 99.770001) (width 0.1778) (layer B.Cu) (net 53))
(segment (start 127.075001 99.770001) (end 127 99.695) (width 0.1778) (layer B.Cu) (net 54))
(segment (start 127.075001 115.57) (end 127.075001 99.770001) (width 0.1778) (layer B.Cu) (net 54))
(segment (start 128.066701 85.847983) (end 128.066701 86.872017) (width 0.1778) (layer F.Cu) (net 58))
(via (at 132.715 88.125201) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 58))
(segment (start 127.512017 85.293299) (end 128.066701 85.847983) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 126.487983 85.293299) (end 127.512017 85.293299) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 128.066701 86.872017) (end 129.319885 88.125201) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 125.933299 85.847983) (end 126.487983 85.293299) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 125.933299 87.481017) (end 125.933299 85.847983) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 129.319885 88.125201) (end 132.715 88.125201) (width 0.1778) (layer F.Cu) (net 58))
(via (at 131.953 76.2) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 58))
(segment (start 131.013299 77.139701) (end 131.953 76.2) (width 0.1778) (layer B.Cu) (net 58))
(segment (start 131.013299 86.962315) (end 131.013299 77.139701) (width 0.1778) (layer B.Cu) (net 58))
(segment (start 132.176185 88.125201) (end 131.013299 86.962315) (width 0.1778) (layer B.Cu) (net 58))
(segment (start 132.715 88.125201) (end 132.176185 88.125201) (width 0.1778) (layer B.Cu) (net 58))
(via (at 129.54 76.4413) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 58))
(segment (start 129.7813 76.2) (end 129.54 76.4413) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 131.953 76.2) (end 129.7813 76.2) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 129.54 76.4413) (end 129.54 78.74) (width 0.1778) (layer B.Cu) (net 58))
(via (at 125.222 88.265) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 58))
(segment (start 125.249158 88.165158) (end 125.249158 88.237842) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 125.249158 88.237842) (end 125.222 88.265) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 125.249158 88.165158) (end 125.933299 87.481017) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 125.222 88.265) (end 125.222 90.678) (width 0.1778) (layer B.Cu) (net 58))
(via (at 125.222 90.678) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 58))
(segment (start 122.809 90.678) (end 125.222 90.678) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 113.638701 99.848299) (end 122.809 90.678) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 111.606701 99.848299) (end 113.638701 99.848299) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 110.49 100.965) (end 111.606701 99.848299) (width 0.1778) (layer F.Cu) (net 58))
(segment (start 120.777 91.890598) (end 120.777 91.567) (width 0.1778) (layer F.Cu) (net 61))
(segment (start 115.665897 97.001701) (end 120.777 91.890598) (width 0.1778) (layer F.Cu) (net 61))
(via (at 120.777 91.567) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 61))
(segment (start 111.606701 97.001701) (end 115.665897 97.001701) (width 0.1778) (layer F.Cu) (net 61))
(segment (start 110.49 95.885) (end 111.606701 97.001701) (width 0.1778) (layer F.Cu) (net 61))
(via (at 118.618 80.645) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 61))
(segment (start 121.589701 77.673299) (end 118.618 80.645) (width 0.1778) (layer F.Cu) (net 61))
(segment (start 125.378615 77.673299) (end 121.589701 77.673299) (width 0.1778) (layer F.Cu) (net 61))
(segment (start 125.933299 78.227983) (end 125.378615 77.673299) (width 0.1778) (layer F.Cu) (net 61))
(segment (start 126.487983 77.673299) (end 125.933299 78.227983) (width 0.1778) (layer F.Cu) (net 61))
(segment (start 131.013299 77.673299) (end 126.487983 77.673299) (width 0.1778) (layer F.Cu) (net 61))
(segment (start 132.08 78.74) (end 131.013299 77.673299) (width 0.1778) (layer F.Cu) (net 61))
(segment (start 120.777 92.105815) (end 120.777 91.567) (width 0.1778) (layer B.Cu) (net 61))
(segment (start 120.033114 92.849701) (end 120.777 92.105815) (width 0.1778) (layer B.Cu) (net 61))
(segment (start 119.196103 92.849701) (end 120.033114 92.849701) (width 0.1778) (layer B.Cu) (net 61))
(segment (start 118.859299 92.512897) (end 119.196103 92.849701) (width 0.1778) (layer B.Cu) (net 61))
(segment (start 118.859299 88.130391) (end 118.859299 92.512897) (width 0.1778) (layer B.Cu) (net 61))
(segment (start 116.446299 85.717391) (end 118.859299 88.130391) (width 0.1778) (layer B.Cu) (net 61))
(segment (start 116.446299 80.588103) (end 116.446299 85.717391) (width 0.1778) (layer B.Cu) (net 61))
(segment (start 118.224299 80.251299) (end 116.783103 80.251299) (width 0.1778) (layer B.Cu) (net 61))
(segment (start 116.783103 80.251299) (end 116.446299 80.588103) (width 0.1778) (layer B.Cu) (net 61))
(segment (start 118.618 80.645) (end 118.224299 80.251299) (width 0.1778) (layer B.Cu) (net 61))
(via (at 119.761 84.582) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 63))
(via (at 119.507 92.202) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 63))
(segment (start 119.761 91.948) (end 119.507 92.202) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 119.761 84.582) (end 119.761 91.948) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 111.682901 92.152099) (end 111.339999 92.495001) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 118.918284 92.152099) (end 111.682901 92.152099) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 118.968185 92.202) (end 118.918284 92.152099) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 111.339999 92.495001) (end 110.49 93.345) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 119.507 92.202) (end 118.968185 92.202) (width 0.1778) (layer F.Cu) (net 63))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 131.559299 81.800701) (end 133.820001 79.539999) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 125.742701 81.800701) (end 131.559299 81.800701) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 125.73 81.788) (end 125.742701 81.800701) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 123.19 84.328) (end 125.73 81.788) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 123.19 84.406962) (end 123.19 84.328) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 122.633962 84.963) (end 123.19 84.406962) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 133.820001 79.539999) (end 134.62 78.74) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 120.142 84.963) (end 122.633962 84.963) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 119.761 84.582) (end 120.142 84.963) (width 0.1778) (layer F.Cu) (net 63))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 137.8077 88.586418) (end 137.8077 90.4367) (width 0.1778) (layer B.Cu) (net 64))
(via (at 137.8077 90.4367) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 64))
(segment (start 136.093299 86.872017) (end 137.8077 88.586418) (width 0.1778) (layer B.Cu) (net 64))
(segment (start 136.093299 79.806701) (end 136.093299 86.872017) (width 0.1778) (layer B.Cu) (net 64))
(segment (start 137.16 78.74) (end 136.093299 79.806701) (width 0.1778) (layer B.Cu) (net 64))
(segment (start 126.307598 90.805) (end 127.767092 90.805) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 127.767092 90.805) (end 128.541793 90.030299) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 125.190897 89.688299) (end 126.307598 90.805) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 128.541793 90.030299) (end 134.988299 90.030299) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 111.606701 89.688299) (end 125.190897 89.688299) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 110.49 90.805) (end 111.606701 89.688299) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 135.3947 90.4367) (end 137.8077 90.4367) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 134.988299 90.030299) (end 135.3947 90.4367) (width 0.1778) (layer F.Cu) (net 64))
(via (at 115.697 85.471) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 67))
(segment (start 114.758099 84.532099) (end 115.697 85.471) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 111.682901 84.532099) (end 114.758099 84.532099) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 110.49 85.725) (end 111.682901 84.532099) (width 0.1778) (layer F.Cu) (net 67))
(via (at 116.713 77.216) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 67))
(segment (start 115.697 78.232) (end 116.713 77.216) (width 0.1778) (layer B.Cu) (net 67))
(segment (start 115.697 85.471) (end 115.697 78.232) (width 0.1778) (layer B.Cu) (net 67))
(via (at 139.280999 75.8317) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 67))
(segment (start 139.001598 75.552299) (end 139.280999 75.8317) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 118.376701 75.552299) (end 139.001598 75.552299) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 116.713 77.216) (end 118.376701 75.552299) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 139.7 76.250701) (end 139.7 78.74) (width 0.1778) (layer B.Cu) (net 67))
(segment (start 139.280999 75.8317) (end 139.7 76.250701) (width 0.1778) (layer B.Cu) (net 67))
(via (at 118.661874 85.146078) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 68))
(via (at 117.7417 83.439) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 68))
(segment (start 117.7417 84.225904) (end 117.7417 83.439) (width 0.1778) (layer B.Cu) (net 68))
(segment (start 118.661874 85.146078) (end 117.7417 84.225904) (width 0.1778) (layer B.Cu) (net 68))
(segment (start 111.339999 82.335001) (end 110.49 83.185) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 111.606701 82.068299) (end 111.339999 82.335001) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 116.370999 82.068299) (end 111.606701 82.068299) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 117.7417 83.439) (end 116.370999 82.068299) (width 0.1778) (layer F.Cu) (net 68))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 133.725908 80.137) (end 140.843 80.137) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 141.351 79.629) (end 142.24 78.74) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 125.864597 82.156311) (end 131.706597 82.156311) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 131.706597 82.156311) (end 133.725908 80.137) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 124.814435 83.206473) (end 125.864597 82.156311) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 124.814435 83.285435) (end 124.814435 83.206473) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 140.843 80.137) (end 141.351 79.629) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 122.661702 85.438168) (end 124.814435 83.285435) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 118.953964 85.438168) (end 122.661702 85.438168) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 118.661874 85.146078) (end 118.953964 85.438168) (width 0.1778) (layer F.Cu) (net 68))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(via (at 117.856 85.852) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 70))
(via (at 117.094 80.899) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 70))
(segment (start 117.094 85.09) (end 117.094 80.899) (width 0.1778) (layer B.Cu) (net 70))
(segment (start 117.856 85.852) (end 117.094 85.09) (width 0.1778) (layer B.Cu) (net 70))
(segment (start 111.339999 79.795001) (end 110.49 80.645) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 111.606701 79.528299) (end 111.339999 79.795001) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 115.723299 79.528299) (end 111.606701 79.528299) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 117.094 80.899) (end 115.723299 79.528299) (width 0.1778) (layer F.Cu) (net 70))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 134.366 80.772) (end 134.64539 80.49261) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 133.604 80.772) (end 134.366 80.772) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 131.864079 82.511921) (end 133.604 80.772) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 143.256 80.264) (end 144.78 78.74) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 125.170044 83.363956) (end 126.022079 82.511921) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 143.02739 80.49261) (end 143.256 80.264) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 125.170044 83.432734) (end 125.170044 83.363956) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 126.022079 82.511921) (end 131.864079 82.511921) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 122.809 85.793778) (end 125.170044 83.432734) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 134.64539 80.49261) (end 143.02739 80.49261) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 117.914222 85.793778) (end 122.809 85.793778) (width 0.1778) (layer F.Cu) (net 70))
(segment (start 117.856 85.852) (end 117.914222 85.793778) (width 0.1778) (layer F.Cu) (net 70))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(via (at 146.939 75.184) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 75))
(segment (start 114.568692 75.184) (end 146.939 75.184) (width 0.1778) (layer F.Cu) (net 75))
(segment (start 113.602593 74.217901) (end 114.568692 75.184) (width 0.1778) (layer F.Cu) (net 75))
(segment (start 111.682901 74.217901) (end 113.602593 74.217901) (width 0.1778) (layer F.Cu) (net 75))
(segment (start 110.49 73.025) (end 111.682901 74.217901) (width 0.1778) (layer F.Cu) (net 75))
(segment (start 146.939 78.359) (end 147.32 78.74) (width 0.1778) (layer B.Cu) (net 75))
(segment (start 146.939 75.184) (end 146.939 78.359) (width 0.1778) (layer B.Cu) (net 75))
(segment (start 126.200001 72.554999) (end 127 71.755) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 123.385679 72.897901) (end 125.857099 72.897901) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 125.857099 72.897901) (end 126.200001 72.554999) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 122.089479 71.601701) (end 123.385679 72.897901) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 111.606701 71.601701) (end 122.089479 71.601701) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 110.49 70.485) (end 111.606701 71.601701) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 128.066701 73.355299) (end 127.635 73.787) (width 0.1778) (layer B.Cu) (net 77))
(segment (start 128.066701 65.201701) (end 128.066701 73.355299) (width 0.1778) (layer B.Cu) (net 77))
(via (at 127.635 73.787) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 77))
(segment (start 127 64.135) (end 128.066701 65.201701) (width 0.1778) (layer B.Cu) (net 77))
(via (at 116.332 73.152) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 77))
(segment (start 116.967 73.787) (end 116.332 73.152) (width 0.1778) (layer F.Cu) (net 77))
(segment (start 127.635 73.787) (end 116.967 73.787) (width 0.1778) (layer F.Cu) (net 77))
(via (at 116.205 70.739) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 77))
(segment (start 116.332 70.866) (end 116.205 70.739) (width 0.1778) (layer B.Cu) (net 77))
(segment (start 116.332 73.152) (end 116.332 70.866) (width 0.1778) (layer B.Cu) (net 77))
(segment (start 113.284 70.739) (end 113.03 70.485) (width 0.1778) (layer F.Cu) (net 77))
(segment (start 116.205 70.739) (end 113.284 70.739) (width 0.1778) (layer F.Cu) (net 77))
(segment (start 133.820001 70.955001) (end 134.62 71.755) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 121.030605 70.612099) (end 133.477099 70.612099) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 119.556407 69.137901) (end 121.030605 70.612099) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 111.682901 69.137901) (end 119.556407 69.137901) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 133.477099 70.612099) (end 133.820001 70.955001) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 110.49 67.945) (end 111.682901 69.137901) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 137.287 68.199) (end 137.287 71.628) (width 0.1778) (layer B.Cu) (net 79))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(via (at 137.287 67.462401) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 79))
(segment (start 137.134599 67.31) (end 137.287 67.462401) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 137.287 71.628) (end 137.16 71.755) (width 0.1778) (layer B.Cu) (net 79))
(segment (start 137.287 67.462401) (end 137.287 71.628) (width 0.1778) (layer B.Cu) (net 79))
(segment (start 133.223 67.31) (end 132.264402 67.31) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 133.223 67.31) (end 137.134599 67.31) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 132.264402 67.31) (end 131.375402 66.421) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 131.375402 66.421) (end 123.317 66.421) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 111.606701 66.521701) (end 110.49 65.405) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 119.552983 66.521701) (end 111.606701 66.521701) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 120.772983 67.741701) (end 119.552983 66.521701) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 121.996299 67.741701) (end 120.772983 67.741701) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 123.317 66.421) (end 121.996299 67.741701) (width 0.1778) (layer F.Cu) (net 79))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 133.35 65.405) (end 113.03 65.405) (width 0.1778) (layer F.Cu) (net 80))
(segment (start 134.62 64.135) (end 133.35 65.405) (width 0.1778) (layer F.Cu) (net 80))
(via (at 141.986 62.103) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 81))
(segment (start 141.631299 61.748299) (end 141.986 62.103) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 111.606701 61.748299) (end 141.631299 61.748299) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 110.49 62.865) (end 111.606701 61.748299) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 143.980001 70.955001) (end 144.78 71.755) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 143.713299 63.830299) (end 143.713299 70.688299) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 143.713299 70.688299) (end 143.980001 70.955001) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 141.986 62.103) (end 143.713299 63.830299) (width 0.1778) (layer B.Cu) (net 81))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 136.271 63.246) (end 137.16 64.135) (width 0.1778) (layer F.Cu) (net 82))
(segment (start 132.206091 62.103909) (end 136.271 62.103909) (width 0.1778) (layer F.Cu) (net 82))
(segment (start 136.271 62.103909) (end 136.271 63.246) (width 0.1778) (layer F.Cu) (net 82))
(segment (start 131.445 62.865) (end 132.206091 62.103909) (width 0.1778) (layer F.Cu) (net 82))
(segment (start 113.03 62.865) (end 131.445 62.865) (width 0.1778) (layer F.Cu) (net 82))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 114.232081 60.325) (end 113.03 60.325) (width 0.1778) (layer F.Cu) (net 83))
(segment (start 142.10137 60.325) (end 114.232081 60.325) (width 0.1778) (layer F.Cu) (net 83))
(segment (start 144.78 63.00363) (end 142.10137 60.325) (width 0.1778) (layer F.Cu) (net 83))
(segment (start 144.78 64.135) (end 144.78 63.00363) (width 0.1778) (layer F.Cu) (net 83))
(segment (start 185.42 73.66) (end 185.42 76.2) (width 0.1778) (layer B.Cu) (net 84))
(segment (start 185.42 77.33137) (end 185.42 78.74) (width 0.1778) (layer B.Cu) (net 84))
(segment (start 185.42 76.2) (end 185.42 77.33137) (width 0.1778) (layer B.Cu) (net 84))
(segment (start 163.994999 74.459999) (end 163.195 73.66) (width 0.1778) (layer F.Cu) (net 84))
(segment (start 164.261701 74.726701) (end 163.994999 74.459999) (width 0.1778) (layer F.Cu) (net 84))
(segment (start 184.353299 74.726701) (end 164.261701 74.726701) (width 0.1778) (layer F.Cu) (net 84))
(segment (start 185.42 73.66) (end 184.353299 74.726701) (width 0.1778) (layer F.Cu) (net 84))
(via (at 125.984 77.089) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 84))
(segment (start 125.984 77.089) (end 125.933299 77.139701) (width 0.1778) (layer B.Cu) (net 84))
(segment (start 158.623 77.089) (end 158.623 75.438) (width 0.1778) (layer F.Cu) (net 84))
(segment (start 158.623 77.089) (end 125.984 77.089) (width 0.1778) (layer F.Cu) (net 84))
(segment (start 160.401 73.66) (end 163.195 73.66) (width 0.1778) (layer F.Cu) (net 84))
(segment (start 158.623 75.438) (end 160.401 73.66) (width 0.1778) (layer F.Cu) (net 84))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(via (at 124.46 96.647) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 84))
(segment (start 125.933299 95.173701) (end 124.46 96.647) (width 0.1778) (layer B.Cu) (net 84))
(segment (start 125.984 77.627815) (end 125.933299 77.678516) (width 0.1778) (layer B.Cu) (net 84))
(segment (start 125.933299 77.678516) (end 125.933299 95.173701) (width 0.1778) (layer B.Cu) (net 84))
(segment (start 125.984 77.089) (end 125.984 77.627815) (width 0.1778) (layer B.Cu) (net 84))
(segment (start 124.46 97.185815) (end 124.46 99.695) (width 0.1778) (layer F.Cu) (net 84))
(segment (start 124.46 96.647) (end 124.46 97.185815) (width 0.1778) (layer F.Cu) (net 84))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 144.855001 99.770001) (end 144.78 99.695) (width 0.1778) (layer B.Cu) (net 85))
(segment (start 144.855001 115.57) (end 144.855001 99.770001) (width 0.1778) (layer B.Cu) (net 85))
(via (at 129.54 81.153) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 86))
(segment (start 131.245718 81.153) (end 129.54 81.153) (width 0.1778) (layer F.Cu) (net 86))
(segment (start 133.146701 79.252017) (end 131.245718 81.153) (width 0.1778) (layer F.Cu) (net 86))
(segment (start 133.146701 78.634581) (end 133.146701 79.252017) (width 0.1778) (layer F.Cu) (net 86))
(segment (start 134.107983 77.673299) (end 133.146701 78.634581) (width 0.1778) (layer F.Cu) (net 86))
(segment (start 176.733299 77.673299) (end 134.107983 77.673299) (width 0.1778) (layer F.Cu) (net 86))
(segment (start 177.8 78.74) (end 176.733299 77.673299) (width 0.1778) (layer F.Cu) (net 86))
(segment (start 128.066701 86.923793) (end 130.606701 89.463793) (width 0.1778) (layer B.Cu) (net 86))
(segment (start 128.066701 86.254581) (end 128.066701 86.923793) (width 0.1778) (layer B.Cu) (net 86))
(segment (start 128.828909 85.492373) (end 128.066701 86.254581) (width 0.1778) (layer B.Cu) (net 86))
(segment (start 128.828909 81.864091) (end 128.828909 85.492373) (width 0.1778) (layer B.Cu) (net 86))
(segment (start 129.54 81.153) (end 128.828909 81.864091) (width 0.1778) (layer B.Cu) (net 86))
(via (at 130.556 90.678) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 86))
(segment (start 130.606701 90.627299) (end 130.556 90.678) (width 0.1778) (layer B.Cu) (net 86))
(segment (start 130.606701 90.246299) (end 130.606701 90.627299) (width 0.1778) (layer B.Cu) (net 86))
(segment (start 130.606701 89.463793) (end 130.606701 90.246299) (width 0.1778) (layer B.Cu) (net 86))
(segment (start 128.397 90.678) (end 127 92.075) (width 0.1778) (layer F.Cu) (net 86))
(segment (start 130.556 90.678) (end 128.397 90.678) (width 0.1778) (layer F.Cu) (net 86))
(segment (start 177.8 71.12) (end 177.8 73.66) (width 0.1778) (layer B.Cu) (net 87))
(segment (start 177.8 73.66) (end 177.8 76.2) (width 0.1778) (layer B.Cu) (net 87))
(via (at 187.071 72.517) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 88))
(segment (start 187.071 79.629) (end 187.071 72.517) (width 0.1778) (layer B.Cu) (net 88))
(segment (start 185.42 81.28) (end 187.071 79.629) (width 0.1778) (layer B.Cu) (net 88))
(segment (start 172.212 72.517) (end 170.815 71.12) (width 0.1778) (layer F.Cu) (net 88))
(segment (start 187.071 72.517) (end 172.212 72.517) (width 0.1778) (layer F.Cu) (net 88))
(segment (start 148.030001 100.676493) (end 149.733 98.973494) (width 0.1778) (layer B.Cu) (net 89))
(segment (start 148.030001 114.935) (end 148.030001 100.676493) (width 0.1778) (layer B.Cu) (net 89))
(segment (start 147.395001 115.57) (end 148.030001 114.935) (width 0.1778) (layer B.Cu) (net 89))
(via (at 150.622 80.01) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 89))
(segment (start 149.733 80.899) (end 150.622 80.01) (width 0.1778) (layer B.Cu) (net 89))
(segment (start 149.733 98.973494) (end 149.733 80.899) (width 0.1778) (layer B.Cu) (net 89))
(segment (start 169.545 80.01) (end 170.815 78.74) (width 0.1778) (layer F.Cu) (net 89))
(segment (start 150.622 80.01) (end 169.545 80.01) (width 0.1778) (layer F.Cu) (net 89))
(segment (start 177.8 66.04) (end 177.8 66.167) (width 0.1778) (layer B.Cu) (net 89))
(segment (start 176.8222 66.04) (end 175.641 67.2212) (width 0.1778) (layer B.Cu) (net 89))
(segment (start 177.8 66.04) (end 176.8222 66.04) (width 0.1778) (layer B.Cu) (net 89))
(segment (start 171.069 78.994) (end 170.815 78.74) (width 0.1778) (layer F.Cu) (net 89))
(segment (start 163.994999 67.780001) (end 163.195 68.58) (width 0.1778) (layer F.Cu) (net 89))
(segment (start 164.261701 67.513299) (end 163.994999 67.780001) (width 0.1778) (layer F.Cu) (net 89))
(segment (start 175.348901 67.513299) (end 164.261701 67.513299) (width 0.1778) (layer F.Cu) (net 89))
(segment (start 176.8222 66.04) (end 175.348901 67.513299) (width 0.1778) (layer F.Cu) (net 89))
(segment (start 177.8 66.04) (end 176.8222 66.04) (width 0.1778) (layer F.Cu) (net 89))
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(segment (start 171.94637 78.74) (end 175.641 75.04537) (width 0.1778) (layer B.Cu) (net 89))
(segment (start 170.815 78.74) (end 171.94637 78.74) (width 0.1778) (layer B.Cu) (net 89))
(segment (start 175.641 75.04537) (end 175.641 72.898) (width 0.1778) (layer B.Cu) (net 89))
(segment (start 175.641 67.2212) (end 175.641 72.898) (width 0.1778) (layer B.Cu) (net 89))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 164.261701 77.673299) (end 163.994999 77.940001) (width 0.1778) (layer B.Cu) (net 90))
(segment (start 164.261701 66.128901) (end 164.261701 77.673299) (width 0.1778) (layer B.Cu) (net 90))
(segment (start 163.994999 77.940001) (end 163.195 78.74) (width 0.1778) (layer B.Cu) (net 90))
(segment (start 164.1728 66.04) (end 164.261701 66.128901) (width 0.1778) (layer B.Cu) (net 90))
(segment (start 163.195 66.04) (end 164.1728 66.04) (width 0.1778) (layer B.Cu) (net 90))
(segment (start 170.815 73.66) (end 170.815 76.2) (width 0.1778) (layer B.Cu) (net 91))
(segment (start 188.595 108.839) (end 188.595 96.48) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 185.495001 111.938999) (end 188.595 108.839) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 185.495001 115.57) (end 185.495001 111.938999) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 180.38 62.865) (end 171.577 62.865) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 166.574999 62.065001) (end 165.775 62.865) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 167.235401 61.404599) (end 166.574999 62.065001) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 170.116599 61.404599) (end 167.235401 61.404599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 171.577 62.865) (end 170.116599 61.404599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 111.339999 59.475001) (end 110.49 60.325) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 112.000401 58.814599) (end 111.339999 59.475001) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 165.775 62.865) (end 161.724599 58.814599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.821599 58.814599) (end 114.821599 66.153401) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.821599 66.153401) (end 113.03 67.945) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.821599 58.814599) (end 112.000401 58.814599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 113.879999 72.175001) (end 113.03 73.025) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.540401 71.514599) (end 113.879999 72.175001) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.540401 69.455401) (end 114.540401 71.514599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 113.03 67.945) (end 114.540401 69.455401) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 109.640001 77.255001) (end 110.49 78.105) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 108.979599 76.594599) (end 109.640001 77.255001) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 108.979599 61.835401) (end 108.979599 76.594599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 110.49 60.325) (end 108.979599 61.835401) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.540401 84.214599) (end 113.03 85.725) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.540401 71.514599) (end 114.540401 84.214599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.540401 91.834599) (end 113.03 93.345) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.540401 84.214599) (end 114.540401 91.834599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 117.515 93.345) (end 121.285 97.115) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 113.03 93.345) (end 117.515 93.345) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 108.979599 96.914599) (end 110.49 98.425) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 108.979599 76.594599) (end 108.979599 96.914599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.540401 101.994599) (end 113.03 103.505) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.540401 91.834599) (end 114.540401 101.994599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 151.13 86.36) (end 152.4 87.63) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 147.32 86.36) (end 151.13 86.36) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 164.64363 62.865) (end 165.775 62.865) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 163.581278 62.865) (end 164.64363 62.865) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 161.734599 64.711679) (end 163.581278 62.865) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 161.734599 79.819599) (end 161.734599 64.711679) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 163.195 81.28) (end 161.734599 79.819599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 121.88 69.175) (end 124.46 71.755) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 121.285 69.175) (end 121.88 69.175) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 114.26 69.175) (end 113.03 67.945) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 123.865 86.36) (end 121.285 83.78) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 124.46 86.36) (end 123.865 86.36) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 120.485001 69.974999) (end 121.285 69.175) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 119.824599 70.635401) (end 120.485001 69.974999) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 119.824599 82.319599) (end 119.824599 70.635401) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 121.285 83.78) (end 119.824599 82.319599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 119.824599 67.714599) (end 119.824599 60.134599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 121.285 69.175) (end 119.824599 67.714599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 119.874401 60.084797) (end 119.824599 60.134599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 119.874401 58.814599) (end 119.874401 60.084797) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 119.874401 58.814599) (end 114.821599 58.814599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 180.38 78.7) (end 180.38 62.865) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 177.8 81.28) (end 180.38 78.7) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 161.724599 58.814599) (end 148.730599 58.814599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 148.730599 58.814599) (end 119.874401 58.814599) (width 0.8128) (layer B.Cu) (net 92))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 122.084999 97.914999) (end 121.285 97.115) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 145.161393 97.914999) (end 122.084999 97.914999) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 146.941394 99.695) (end 145.161393 97.914999) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 147.32 99.695) (end 146.941394 99.695) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 190.055401 95.019599) (end 188.595 96.48) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 190.055401 67.879007) (end 190.055401 95.019599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 183.580993 61.404599) (end 190.055401 67.879007) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 181.840401 61.404599) (end 183.580993 61.404599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 180.38 62.865) (end 181.840401 61.404599) (width 0.8128) (layer B.Cu) (net 92))
(segment (start 153.199999 88.429999) (end 152.4 87.63) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 154.292211 89.522211) (end 153.199999 88.429999) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 190.055401 93.279007) (end 186.298605 89.522211) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 190.055401 95.019599) (end 190.055401 93.279007) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 186.298605 89.522211) (end 154.292211 89.522211) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 188.595 96.48) (end 190.055401 95.019599) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 131.065028 67.17031) (end 124.42106 67.17031) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 131.954028 68.05931) (end 131.065028 67.17031) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 122.41637 69.175) (end 121.285 69.175) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 124.42106 67.17031) (end 122.41637 69.175) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 136.448802 68.503802) (end 136.00431 68.05931) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 137.786873 68.503802) (end 136.448802 68.503802) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 138.244076 68.046599) (end 137.786873 68.503802) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 144.742969 68.046599) (end 138.244076 68.046599) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 136.00431 68.05931) (end 131.954028 68.05931) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 147.32 70.62363) (end 144.742969 68.046599) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 147.32 71.755) (end 147.32 70.62363) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 124.46 86.261598) (end 124.46 86.36) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 126.647598 84.074) (end 124.46 86.261598) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 147.32 85.894624) (end 145.499376 84.074) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 145.499376 84.074) (end 126.647598 84.074) (width 0.8128) (layer F.Cu) (net 92))
(segment (start 147.32 86.36) (end 147.32 85.894624) (width 0.8128) (layer F.Cu) (net 92))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 185.495001 115.57) (end 185.495001 102.87) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 185.42 102.87) (end 182.88 102.87) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 185.42 65.405) (end 182.88 62.865) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 185.42 66.04) (end 185.42 65.405) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 181.419599 61.404599) (end 174.815401 61.404599) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 182.88 62.865) (end 181.419599 61.404599) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 174.815401 62.039599) (end 170.815 66.04) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 174.815401 61.404599) (end 174.815401 62.039599) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 170.815 65.405) (end 168.275 62.865) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 170.815 66.04) (end 170.815 65.405) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 126.365 93.98) (end 124.46 92.075) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 188.595 93.98) (end 126.365 93.98) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 123.825 92.075) (end 121.285 94.615) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 124.46 92.075) (end 123.825 92.075) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 113.879999 105.195001) (end 113.03 106.045) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 114.540401 104.534599) (end 113.879999 105.195001) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 114.540401 101.359599) (end 114.540401 104.534599) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 121.285 94.615) (end 114.540401 101.359599) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 113.03 106.045) (end 113.03 108.585) (width 0.8128) (layer F.Cu) (net 93))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 188.595 93.98) (end 186.944 93.98) (width 0.8128) (layer B.Cu) (net 93))
(segment (start 185.42 92.456) (end 185.42 87.63) (width 0.8128) (layer B.Cu) (net 93))
(segment (start 186.944 93.98) (end 185.42 92.456) (width 0.8128) (layer B.Cu) (net 93))
(segment (start 185.42 97.155) (end 188.595 93.98) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 185.42 102.87) (end 185.42 97.155) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 187.0328 87.63) (end 185.42 87.63) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 188.112401 86.550399) (end 187.0328 87.63) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 188.112401 68.732401) (end 188.112401 86.550399) (width 0.8128) (layer F.Cu) (net 93))
(segment (start 185.42 66.04) (end 188.112401 68.732401) (width 0.8128) (layer F.Cu) (net 93))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(segment (start 110.49 88.265) (end 110.49 88.392) (width 0.1778) (layer B.Cu) (net 94))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 111.6956 108.585) (end 110.49 108.585) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 111.748199 108.532401) (end 111.6956 108.585) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 111.771801 102.866133) (end 111.748199 102.889735) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 111.771801 97.809735) (end 111.771801 102.866133) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 111.748199 102.889735) (end 111.748199 108.532401) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 111.748199 97.786133) (end 111.771801 97.809735) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 111.748199 90.278909) (end 111.748199 97.786133) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 110.49 89.02071) (end 111.748199 90.278909) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 110.49 88.265) (end 110.49 89.02071) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 115.558199 87.006801) (end 120.485001 82.079999) (width 0.3556) (layer F.Cu) (net 94))
(segment (start 120.485001 82.079999) (end 121.285 81.28) (width 0.3556) (layer F.Cu) (net 94))
(segment (start 111.748199 87.006801) (end 115.558199 87.006801) (width 0.3556) (layer F.Cu) (net 94))
(segment (start 110.49 88.265) (end 111.748199 87.006801) (width 0.3556) (layer F.Cu) (net 94))
(segment (start 123.825 78.74) (end 124.46 78.74) (width 0.3556) (layer F.Cu) (net 94))
(segment (start 121.285 81.28) (end 123.825 78.74) (width 0.3556) (layer F.Cu) (net 94))
(segment (start 125.259999 64.934999) (end 124.46 64.135) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 125.691801 65.366801) (end 125.259999 64.934999) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 125.691801 72.900441) (end 125.691801 65.366801) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 124.46 74.132242) (end 125.691801 72.900441) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 124.46 78.74) (end 124.46 74.132242) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 121.92 66.675) (end 121.285 66.675) (width 0.3556) (layer B.Cu) (net 94))
(segment (start 124.46 64.135) (end 121.92 66.675) (width 0.3556) (layer B.Cu) (net 94))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(via (at 129.159 69.964399) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 95))
(segment (start 127 77.60863) (end 127 78.74) (width 0.1778) (layer B.Cu) (net 95))
(segment (start 127 76.205092) (end 127 77.60863) (width 0.1778) (layer B.Cu) (net 95))
(segment (start 128.473299 74.731793) (end 127 76.205092) (width 0.1778) (layer B.Cu) (net 95))
(segment (start 128.473299 70.6501) (end 128.473299 74.731793) (width 0.1778) (layer B.Cu) (net 95))
(segment (start 129.159 69.964399) (end 128.473299 70.6501) (width 0.1778) (layer B.Cu) (net 95))
Update power and ground wiring
2020-11-19 21:27:50 +00:00
(segment (start 162.395001 71.919999) (end 163.195 71.12) (width 0.1778) (layer F.Cu) (net 95))
(segment (start 146.771407 72.897901) (end 161.417099 72.897901) (width 0.1778) (layer F.Cu) (net 95))
(segment (start 161.417099 72.897901) (end 162.395001 71.919999) (width 0.1778) (layer F.Cu) (net 95))
(segment (start 146.177099 72.303593) (end 146.771407 72.897901) (width 0.1778) (layer F.Cu) (net 95))
(segment (start 146.177099 71.573381) (end 146.177099 72.303593) (width 0.1778) (layer F.Cu) (net 95))
(segment (start 144.936408 70.33269) (end 146.177099 71.573381) (width 0.1778) (layer F.Cu) (net 95))
(segment (start 142.84969 70.33269) (end 144.936408 70.33269) (width 0.1778) (layer F.Cu) (net 95))
(segment (start 142.506601 69.989601) (end 142.84969 70.33269) (width 0.1778) (layer F.Cu) (net 95))
(segment (start 142.506601 69.964399) (end 142.506601 69.989601) (width 0.1778) (layer F.Cu) (net 95))
(segment (start 142.506601 69.964399) (end 129.159 69.964399) (width 0.1778) (layer F.Cu) (net 95))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
(via (at 152.273 81.661) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 96))
(segment (start 153.034901 82.422901) (end 152.273 81.661) (width 0.1778) (layer F.Cu) (net 96))
(segment (start 169.672099 82.422901) (end 153.034901 82.422901) (width 0.1778) (layer F.Cu) (net 96))
(segment (start 170.815 81.28) (end 169.672099 82.422901) (width 0.1778) (layer F.Cu) (net 96))
(segment (start 152.273 81.661) (end 151.765 81.153) (width 0.1778) (layer B.Cu) (net 96))
(segment (start 147.447 64.262) (end 147.32 64.135) (width 0.1778) (layer F.Cu) (net 96))
Remove unnecessary vias
2020-11-20 00:06:00 +00:00
(segment (start 151.765 68.58) (end 147.32 64.135) (width 0.1778) (layer B.Cu) (net 96))
(segment (start 151.765 71.247) (end 151.765 68.58) (width 0.1778) (layer B.Cu) (net 96))
(segment (start 151.765 81.153) (end 151.765 71.247) (width 0.1778) (layer B.Cu) (net 96))
Complete initial PCB layout
2020-11-19 17:31:19 +00:00
Update schematic and create rough PCB layout
2020-11-16 03:44:31 +00:00
)
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