Apple-2-HW/Apple2-IO-RPi
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Apple2-IO-RPi/Hardware/Apple2IORPi.kicad_pcb

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Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(kicad_pcb (version 20171130) (host pcbnew "(5.0.2)-1")
(general
(thickness 1.6)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(drawings 81)
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(tracks 1274)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(zones 0)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(modules 20)
(nets 102)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
(page USLetter)
(title_block
(title "Apple II I/O RPi")
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(date 2020-12-29)
(rev 0.3)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(company "Terence J. Boldt")
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(comment 1 "Third Prototype")
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user hide)
(33 F.Adhes user hide)
(34 B.Paste user hide)
(35 F.Paste user hide)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user hide)
(39 F.Mask user hide)
(40 Dwgs.User user hide)
(41 Cmts.User user hide)
(42 Eco1.User user hide)
(43 Eco2.User user hide)
(44 Edge.Cuts user)
(45 Margin user hide)
(46 B.CrtYd user hide)
(47 F.CrtYd user hide)
(48 B.Fab user hide)
(49 F.Fab user hide)
)
(setup
(last_trace_width 0.1778)
(trace_clearance 0.1778)
(zone_clearance 0.508)
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(uvias_allowed no)
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(pcb_text_size 1.5 1.5)
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(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
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(aux_axis_origin 0 0)
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(pcbplotparams
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(usegerberextensions false)
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(psnegative false)
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(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(outputdirectory "."))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
(net 0 "")
(net 1 "Net-(U0-Pad15)")
(net 2 "Net-(U0-Pad14)")
(net 3 "Net-(J0-Pad9)")
(net 4 "Net-(U0-Pad13)")
(net 5 "Net-(J0-Pad8)")
(net 6 "Net-(U0-Pad12)")
(net 7 "Net-(J0-Pad7)")
(net 8 "Net-(U0-Pad11)")
(net 9 "Net-(J0-Pad6)")
(net 10 "Net-(J0-Pad1)")
(net 11 "Net-(J0-Pad5)")
(net 12 "Net-(J0-Pad12)")
(net 13 "Net-(J0-Pad4)")
(net 14 "Net-(J0-Pad3)")
(net 15 "Net-(J0-Pad2)")
(net 16 "Net-(J0-Pad11)")
(net 17 "Net-(U0-Pad18)")
(net 18 "Net-(J0-Pad10)")
(net 19 "Net-(U0-Pad17)")
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 20 "Net-(U0-Pad16)")
(net 21 "Net-(J0-Pad13)")
(net 22 "Net-(J0-Pad14)")
(net 23 "Net-(J0-Pad15)")
(net 24 "Net-(J0-Pad16)")
(net 25 "Net-(J0-Pad17)")
(net 26 "Net-(J0-Pad18)")
(net 27 "Net-(J0-Pad19)")
(net 28 "Net-(J0-Pad20)")
(net 29 "Net-(J0-Pad21)")
(net 30 "Net-(J0-Pad22)")
(net 31 "Net-(J0-Pad23)")
(net 32 "Net-(J0-Pad24)")
(net 33 "Net-(J0-Pad29)")
(net 34 "Net-(J0-Pad30)")
(net 35 "Net-(J0-Pad31)")
(net 36 "Net-(J0-Pad32)")
(net 37 "Net-(J0-Pad33)")
(net 38 "Net-(J0-Pad34)")
(net 39 "Net-(J0-Pad35)")
(net 40 "Net-(J0-Pad36)")
(net 41 "Net-(J0-Pad37)")
(net 42 "Net-(J0-Pad38)")
(net 43 "Net-(J0-Pad39)")
(net 44 "Net-(J0-Pad40)")
(net 45 "Net-(J0-Pad43)")
(net 46 "Net-(J0-Pad44)")
(net 47 "Net-(J0-Pad45)")
(net 48 "Net-(J0-Pad46)")
(net 49 "Net-(J0-Pad47)")
(net 50 "Net-(J0-Pad48)")
(net 51 "Net-(J0-Pad49)")
(net 52 "Net-(J0-Pad50)")
(net 53 "Net-(J1-Pad3)")
(net 54 "Net-(J1-Pad5)")
(net 55 "Net-(J1-Pad7)")
(net 56 "Net-(J1-Pad8)")
(net 57 "Net-(J1-Pad10)")
(net 58 "Net-(J1-Pad11)")
(net 59 "Net-(J1-Pad12)")
(net 60 "Net-(J1-Pad13)")
(net 61 "Net-(J1-Pad15)")
(net 62 "Net-(J1-Pad16)")
(net 63 "Net-(J1-Pad18)")
(net 64 "Net-(J1-Pad19)")
(net 65 "Net-(J1-Pad21)")
(net 66 "Net-(J1-Pad22)")
(net 67 "Net-(J1-Pad23)")
(net 68 "Net-(J1-Pad24)")
(net 69 "Net-(J1-Pad26)")
(net 70 "Net-(J1-Pad27)")
(net 71 "Net-(J1-Pad28)")
(net 72 "Net-(J1-Pad29)")
(net 73 "Net-(J1-Pad31)")
(net 74 "Net-(J1-Pad32)")
(net 75 "Net-(J1-Pad33)")
(net 76 "Net-(J1-Pad35)")
(net 77 "Net-(J1-Pad36)")
(net 78 "Net-(J1-Pad37)")
(net 79 "Net-(J1-Pad38)")
(net 80 "Net-(J1-Pad40)")
(net 81 "Net-(U0-Pad1)")
(net 82 "Net-(J0-Pad42)")
(net 83 "Net-(U0-Pad19)")
(net 84 "Net-(U2-Pad3)")
(net 85 "Net-(U2-Pad8)")
(net 86 "Net-(J0-Pad41)")
(net 87 "Net-(U3-Pad1)")
(net 88 "Net-(U3-Pad10)")
(net 89 "Net-(C1-Pad2)")
(net 90 "Net-(C1-Pad1)")
(net 91 "Net-(C5-Pad1)")
(net 92 "Net-(U3-Pad3)")
(net 93 "Net-(U3-Pad8)")
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(net 94 "Net-(U1-Pad2)")
(net 95 "Net-(U1-Pad23)")
(net 96 "Net-(U1-Pad26)")
(net 97 "Net-(U1-Pad27)")
(net 98 "Net-(U7-Pad11)")
(net 99 "Net-(U6-Pad19)")
(net 100 "Net-(U8-Pad2)")
(net 101 "Net-(U8-Pad11)")
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(net_class Default "This is the default net class."
(clearance 0.1778)
(trace_width 0.1778)
(via_dia 0.762)
(via_drill 0.50038)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "Net-(J0-Pad1)")
(add_net "Net-(J0-Pad10)")
(add_net "Net-(J0-Pad11)")
(add_net "Net-(J0-Pad12)")
(add_net "Net-(J0-Pad13)")
(add_net "Net-(J0-Pad14)")
(add_net "Net-(J0-Pad15)")
(add_net "Net-(J0-Pad16)")
(add_net "Net-(J0-Pad17)")
(add_net "Net-(J0-Pad18)")
(add_net "Net-(J0-Pad19)")
(add_net "Net-(J0-Pad2)")
(add_net "Net-(J0-Pad20)")
(add_net "Net-(J0-Pad21)")
(add_net "Net-(J0-Pad22)")
(add_net "Net-(J0-Pad23)")
(add_net "Net-(J0-Pad24)")
(add_net "Net-(J0-Pad29)")
(add_net "Net-(J0-Pad3)")
(add_net "Net-(J0-Pad30)")
(add_net "Net-(J0-Pad31)")
(add_net "Net-(J0-Pad32)")
(add_net "Net-(J0-Pad33)")
(add_net "Net-(J0-Pad34)")
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(add_net "Net-(J0-Pad36)")
(add_net "Net-(J0-Pad37)")
(add_net "Net-(J0-Pad38)")
(add_net "Net-(J0-Pad39)")
(add_net "Net-(J0-Pad4)")
(add_net "Net-(J0-Pad40)")
(add_net "Net-(J0-Pad41)")
(add_net "Net-(J0-Pad42)")
(add_net "Net-(J0-Pad43)")
(add_net "Net-(J0-Pad44)")
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(add_net "Net-(J0-Pad46)")
(add_net "Net-(J0-Pad47)")
(add_net "Net-(J0-Pad48)")
(add_net "Net-(J0-Pad49)")
(add_net "Net-(J0-Pad5)")
(add_net "Net-(J0-Pad50)")
(add_net "Net-(J0-Pad6)")
(add_net "Net-(J0-Pad7)")
(add_net "Net-(J0-Pad8)")
(add_net "Net-(J0-Pad9)")
(add_net "Net-(J1-Pad10)")
(add_net "Net-(J1-Pad11)")
(add_net "Net-(J1-Pad12)")
(add_net "Net-(J1-Pad13)")
(add_net "Net-(J1-Pad15)")
(add_net "Net-(J1-Pad16)")
(add_net "Net-(J1-Pad18)")
(add_net "Net-(J1-Pad19)")
(add_net "Net-(J1-Pad21)")
(add_net "Net-(J1-Pad22)")
(add_net "Net-(J1-Pad23)")
(add_net "Net-(J1-Pad24)")
(add_net "Net-(J1-Pad26)")
(add_net "Net-(J1-Pad27)")
(add_net "Net-(J1-Pad28)")
(add_net "Net-(J1-Pad29)")
(add_net "Net-(J1-Pad3)")
(add_net "Net-(J1-Pad31)")
(add_net "Net-(J1-Pad32)")
(add_net "Net-(J1-Pad33)")
(add_net "Net-(J1-Pad35)")
(add_net "Net-(J1-Pad36)")
(add_net "Net-(J1-Pad37)")
(add_net "Net-(J1-Pad38)")
(add_net "Net-(J1-Pad40)")
(add_net "Net-(J1-Pad5)")
(add_net "Net-(J1-Pad7)")
(add_net "Net-(J1-Pad8)")
(add_net "Net-(U0-Pad1)")
(add_net "Net-(U0-Pad11)")
(add_net "Net-(U0-Pad12)")
(add_net "Net-(U0-Pad13)")
(add_net "Net-(U0-Pad14)")
(add_net "Net-(U0-Pad15)")
(add_net "Net-(U0-Pad16)")
(add_net "Net-(U0-Pad17)")
(add_net "Net-(U0-Pad18)")
(add_net "Net-(U0-Pad19)")
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(add_net "Net-(U1-Pad2)")
(add_net "Net-(U1-Pad23)")
(add_net "Net-(U1-Pad26)")
(add_net "Net-(U1-Pad27)")
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(add_net "Net-(U2-Pad3)")
(add_net "Net-(U2-Pad8)")
(add_net "Net-(U3-Pad1)")
(add_net "Net-(U3-Pad10)")
(add_net "Net-(U3-Pad3)")
(add_net "Net-(U3-Pad8)")
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(add_net "Net-(U6-Pad19)")
(add_net "Net-(U7-Pad11)")
(add_net "Net-(U8-Pad11)")
(add_net "Net-(U8-Pad2)")
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
(net_class 3V3 ""
(clearance 0.1778)
(trace_width 0.3556)
(via_dia 0.762)
(via_drill 0.50038)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "Net-(C5-Pad1)")
)
(net_class 5V ""
(clearance 0.254)
(trace_width 0.8128)
(via_dia 0.762)
(via_drill 0.7112)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "Net-(C1-Pad1)")
)
(net_class Ground ""
(clearance 0.254)
(trace_width 0.8128)
(via_dia 0.762)
(via_drill 0.7112)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net "Net-(C1-Pad2)")
)
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB688E8)
(at 123.825 78.105 90)
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FA1EB22)
(fp_text reference U5 (at 3.81 -2.33 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
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(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
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(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(net 93 "Net-(U3-Pad8)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 73 "Net-(J1-Pad31)"))
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 80 "Net-(J1-Pad40)"))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(U0-Pad18)"))
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 75 "Net-(J1-Pad33)"))
(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 79 "Net-(J1-Pad38)"))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 76 "Net-(J1-Pad35)"))
(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 77 "Net-(J1-Pad36)"))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(U0-Pad16)"))
(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(U0-Pad12)"))
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 "Net-(U0-Pad11)"))
(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 78 "Net-(J1-Pad37)"))
(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 74 "Net-(J1-Pad32)"))
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(C5-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(module Connector_PinSocket_2.54mm:PinSocket_2x20_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A433) (tstamp 5FB687FC)
(at 110.49 100.584 180)
(descr "Through hole straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 2x20 2.54mm double row")
(path /5FA19C2C)
(fp_text reference J1 (at -1.27 -2.77) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Raspberry_Pi_2_3 (at -1.27 51.03) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.81 -1.27) (end 0.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.27 -1.27) (end 1.27 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.27) (end 1.27 49.53) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 49.53) (end -3.81 49.53) (layer F.Fab) (width 0.1))
(fp_line (start -3.81 49.53) (end -3.81 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -3.87 -1.33) (end -1.27 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -3.87 -1.33) (end -3.87 49.59) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.33 1.27) (end 1.33 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -1.33) (end -1.27 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
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(fp_line (start -4.34 50) (end -4.34 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at -1.27 24.13 90) (layer F.Fab)
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)
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(pad 2 thru_hole oval (at -2.54 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 90 "Net-(C1-Pad1)"))
(pad 3 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 53 "Net-(J1-Pad3)"))
(pad 4 thru_hole oval (at -2.54 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 90 "Net-(C1-Pad1)"))
(pad 5 thru_hole oval (at 0 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 54 "Net-(J1-Pad5)"))
(pad 6 thru_hole oval (at -2.54 5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 7 thru_hole oval (at 0 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 55 "Net-(J1-Pad7)"))
(pad 8 thru_hole oval (at -2.54 7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 56 "Net-(J1-Pad8)"))
(pad 9 thru_hole oval (at 0 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 10 thru_hole oval (at -2.54 10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 57 "Net-(J1-Pad10)"))
(pad 11 thru_hole oval (at 0 12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 58 "Net-(J1-Pad11)"))
(pad 12 thru_hole oval (at -2.54 12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 59 "Net-(J1-Pad12)"))
(pad 13 thru_hole oval (at 0 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 60 "Net-(J1-Pad13)"))
(pad 14 thru_hole oval (at -2.54 15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 15 thru_hole oval (at 0 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 61 "Net-(J1-Pad15)"))
(pad 16 thru_hole oval (at -2.54 17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 62 "Net-(J1-Pad16)"))
(pad 17 thru_hole oval (at 0 20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 91 "Net-(C5-Pad1)"))
(pad 18 thru_hole oval (at -2.54 20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 63 "Net-(J1-Pad18)"))
(pad 19 thru_hole oval (at 0 22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 64 "Net-(J1-Pad19)"))
(pad 20 thru_hole oval (at -2.54 22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 21 thru_hole oval (at 0 25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 65 "Net-(J1-Pad21)"))
(pad 22 thru_hole oval (at -2.54 25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 66 "Net-(J1-Pad22)"))
(pad 23 thru_hole oval (at 0 27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 67 "Net-(J1-Pad23)"))
(pad 24 thru_hole oval (at -2.54 27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 68 "Net-(J1-Pad24)"))
(pad 25 thru_hole oval (at 0 30.48 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 26 thru_hole oval (at -2.54 30.48 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 69 "Net-(J1-Pad26)"))
(pad 27 thru_hole oval (at 0 33.02 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 70 "Net-(J1-Pad27)"))
(pad 28 thru_hole oval (at -2.54 33.02 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 71 "Net-(J1-Pad28)"))
(pad 29 thru_hole oval (at 0 35.56 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 72 "Net-(J1-Pad29)"))
(pad 30 thru_hole oval (at -2.54 35.56 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 31 thru_hole oval (at 0 38.1 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 73 "Net-(J1-Pad31)"))
(pad 32 thru_hole oval (at -2.54 38.1 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 74 "Net-(J1-Pad32)"))
(pad 33 thru_hole oval (at 0 40.64 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 75 "Net-(J1-Pad33)"))
(pad 34 thru_hole oval (at -2.54 40.64 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 35 thru_hole oval (at 0 43.18 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 76 "Net-(J1-Pad35)"))
(pad 36 thru_hole oval (at -2.54 43.18 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 77 "Net-(J1-Pad36)"))
(pad 37 thru_hole oval (at 0 45.72 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 78 "Net-(J1-Pad37)"))
(pad 38 thru_hole oval (at -2.54 45.72 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 79 "Net-(J1-Pad38)"))
(pad 39 thru_hole oval (at 0 48.26 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 40 thru_hole oval (at -2.54 48.26 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 80 "Net-(J1-Pad40)"))
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_2x20_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Apple2:Capacitor (layer F.Cu) (tedit 5FEB5F4F) (tstamp 5FB68750)
(at 121.285 73.065 270)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /5FB87862)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text reference C6 (at 1.25 2.54 270) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value C (at 1.25 2.55 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(fp_text user %R (at 1.25 0 270) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
)
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 91 "Net-(C5-Pad1)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(module Apple2:Capacitor (layer F.Cu) (tedit 5FEB5F56) (tstamp 5FB6873B)
(at 121.285 85.765 270)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /5FB8694D)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text reference C5 (at 1.25 2.54 270) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value C (at 1.25 2.55 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 270) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
)
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 91 "Net-(C5-Pad1)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 89 "Net-(C1-Pad2)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(module Apple2:Capacitor (layer F.Cu) (tedit 5FEB5F7F) (tstamp 5FB686E7)
(at 121.285 97.83 270)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /5FB85911)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text reference C1 (at 1.25 2.54 270) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value C (at 1.25 2.55 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(fp_text user %R (at 1.25 0 270) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
)
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 90 "Net-(C1-Pad1)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(module Apple2:Capacitor (layer F.Cu) (tedit 5FEB5F9C) (tstamp 5FB68726)
(at 161.29 52.705 180)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /5FB82906)
(fp_text reference C4 (at 1.25 2.54 180) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value C (at 1.25 2.55 180) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 180) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(C1-Pad1)"))
(pad 2 thru_hole circle (at 2.5 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
)
(module Apple2:Capacitor (layer F.Cu) (tedit 5FEB5FA8) (tstamp 5FB68711)
(at 185.8518 52.705 180)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /5FB81404)
(fp_text reference C3 (at 1.25 2.54 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value C (at 1.25 2.55 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 180) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(C1-Pad1)"))
(pad 2 thru_hole circle (at 2.5 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
)
(module Apple2:Capacitor (layer F.Cu) (tedit 5FEB5FB7) (tstamp 5FB686FC)
(at 190.5 90.17 90)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /5FB849D8)
(fp_text reference C2 (at 1.25 2.54 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value C (at 1.25 2.55 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 90) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 1 thru_hole circle (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(C1-Pad1)"))
(pad 2 thru_hole circle (at 2.5 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
)
(module Apple2:Capacitor (layer F.Cu) (tedit 5FEB5F72) (tstamp 5FF7C959)
(at 121.285 47.625 270)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /60A87587)
(fp_text reference C7 (at 1.25 2.54 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value C (at 1.25 2.55 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 270) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(C5-Pad1)"))
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
)
(module Apple2:Capacitor (layer F.Cu) (tedit 5FEB5F5D) (tstamp 5FF7C96E)
(at 121.285 60.325 270)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /60A58951)
(fp_text reference C8 (at 1.25 2.54 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value C (at 1.25 2.55 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 270) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(C5-Pad1)"))
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
)
(module Apple2:Capacitor (layer F.Cu) (tedit 5FEB5FA2) (tstamp 5FF7C983)
(at 173.99 52.705 180)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(path /60C3A67B)
(fp_text reference C9 (at 1.25 2.54 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value C (at 1.25 2.55 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start -0.65 -1.3) (end -0.65 1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.65 1.3) (end 3.15 1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 1.3) (end 3.15 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start 3.15 -1.3) (end -0.65 -1.3) (layer F.Fab) (width 0.1))
(fp_line (start -0.77 -1.42) (end 3.27 -1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 1.42) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 -1.42) (end -0.77 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start -0.77 0.795) (end -0.77 1.42) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 -1.42) (end 3.27 -0.795) (layer F.Fab) (width 0.12))
(fp_line (start 3.27 0.795) (end 3.27 1.42) (layer F.Fab) (width 0.12))
(fp_line (start -1.05 -1.55) (end -1.05 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.55) (end 3.55 1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.55) (end 3.55 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.55) (end -1.05 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.25 0 180) (layer F.Fab)
(effects (font (size 0.76 0.76) (thickness 0.114)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(C1-Pad1)"))
(pad 2 thru_hole circle (at 2.5 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/C_Disc_D3.8mm_W2.6mm_P2.50mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
)
(module Apple2:74LS32 (layer F.Cu) (tedit 5FB6A63A) (tstamp 5FF7D7EC)
(at 168.7068 55.1688)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /60BA60C0)
(fp_text reference U8 (at 3.81 -2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value 74LS32 (at 3.875 7.55 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_arc (start 6.025 13.795) (end 4.925 13.795) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_line (start 5.25 10.17) (end 5.25 13.32) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 14.77) (end 5.475 15.295) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 15.295) (end 6.425 15.295) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 12.72) (end 5.725 12.72) (layer F.SilkS) (width 0.12))
(fp_line (start 5.725 12.72) (end 5.725 13.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 10.17) (end 5.25 10.17) (layer F.SilkS) (width 0.12))
(fp_arc (start 4.923537 13.765952) (end 6.023537 13.765952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_line (start 6.025 13.795) (end 6.025 13.245) (layer F.SilkS) (width 0.12))
(fp_line (start 4.925 13.22) (end 4.925 13.795) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.475 12.445) (end 4.925001 13.219999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_arc (start 2 9.747) (end 1.450001 10.521999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 10.522) (end 1.45 11.097) (layer F.SilkS) (width 0.12))
(fp_line (start 2.55 11.097) (end 2.55 10.547) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.55 11.097) (end 1.45 11.097) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.448537 11.067952) (end 2.548537 11.067952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_line (start 1.175 10.122) (end 1.75 10.122) (layer F.SilkS) (width 0.12))
(fp_line (start 1.75 10.122) (end 1.75 10.672) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 10.622) (end 2.225 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 7.747) (end 1.175 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 12.022) (end 1.95 12.772) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 12.772) (end 1.175 12.772) (layer F.SilkS) (width 0.12))
(fp_line (start 5.25 2.55) (end 5.25 5.7) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 2.55) (end 5.25 2.55) (layer F.SilkS) (width 0.12))
(fp_line (start 5.725 5.1) (end 5.725 5.75) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 5.1) (end 5.725 5.1) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 7.675) (end 6.425 7.675) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 7.15) (end 5.475 7.675) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 5.025) (end 1.175 5.025) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 4.275) (end 1.95 5.025) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 0) (end 1.175 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 2.875) (end 2.225 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.75 2.375) (end 1.75 2.925) (layer F.SilkS) (width 0.12))
(fp_line (start 1.175 2.375) (end 1.75 2.375) (layer F.SilkS) (width 0.12))
(fp_line (start 4.925 5.6) (end 4.925 6.175) (layer F.SilkS) (width 0.12))
(fp_line (start 6.025 6.175) (end 6.025 5.625) (layer F.SilkS) (width 0.12))
(fp_arc (start 4.923537 6.145952) (end 6.023537 6.145952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_arc (start 6.025 6.175) (end 4.925 6.175) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.475 4.825) (end 4.925001 5.599999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.448537 3.320952) (end 2.548537 3.320952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.55 3.35) (end 1.45 3.35) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_line (start 2.55 3.35) (end 2.55 2.8) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 2.775) (end 1.45 3.35) (layer F.SilkS) (width 0.12))
(fp_arc (start 2 2) (end 1.450001 2.774999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 90 "Net-(C1-Pad1)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(net 11 "Net-(J0-Pad5)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 98 "Net-(U7-Pad11)"))
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 85 "Net-(U2-Pad8)"))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 101 "Net-(U8-Pad11)"))
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 101 "Net-(U8-Pad11)"))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(J0-Pad41)"))
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(net 13 "Net-(J0-Pad4)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 99 "Net-(U6-Pad19)"))
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 81 "Net-(U0-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 100 "Net-(U8-Pad2)"))
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 100 "Net-(U8-Pad2)"))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(J0-Pad41)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5FEB5F8A) (tstamp 5FF7D6E0)
(at 123.825 52.705 90)
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FED6949)
(fp_text reference U6 (at 3.81 -2.33 90) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value 74LVC245 (at 3.81 25.19 90) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(C5-Pad1)"))
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 89 "Net-(C1-Pad2)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(U0-Pad12)"))
(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 68 "Net-(J1-Pad24)"))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(U0-Pad13)"))
(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 66 "Net-(J1-Pad22)"))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 "Net-(U0-Pad14)"))
(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 63 "Net-(J1-Pad18)"))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 69 "Net-(J1-Pad26)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(U0-Pad16)"))
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 68 "Net-(J1-Pad24)"))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U0-Pad17)"))
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 66 "Net-(J1-Pad22)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(U0-Pad18)"))
(pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 63 "Net-(J1-Pad18)"))
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5FEB5F90) (tstamp 5FF7D6B8)
(at 123.825 65.405 90)
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(path /5FED6A94)
(fp_text reference U7 (at 3.81 -2.33 90) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value 74LVC374 (at 3.81 25.19 90) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 89 "Net-(C1-Pad2)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 98 "Net-(U7-Pad11)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 62 "Net-(J1-Pad16)"))
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 95 "Net-(U1-Pad23)"))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(U0-Pad18)"))
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 "Net-(U0-Pad14)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U0-Pad17)"))
(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(U0-Pad13)"))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(U0-Pad12)"))
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(C1-Pad2)"))
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(C5-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(module Package_DIP:DIP-28_W15.24mm_Socket (layer F.Cu) (tedit 5FEB5FB0) (tstamp 5FF7D65A)
(at 187.101925 81.586962 270)
(descr "28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket")
(tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket")
(path /5FD87325)
(fp_text reference U1 (at 7.62 -2.33 270) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value 27C256 (at 7.62 35.35 270) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 -1.27) (end 14.985 34.29) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 34.29) (end 0.255 34.29) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 34.29) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 34.35) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 34.35) (end 16.51 34.35) (layer F.Fab) (width 0.1))
(fp_line (start 16.51 34.35) (end 16.51 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 16.51 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 6.62 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 34.35) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 34.35) (end 14.08 34.35) (layer F.SilkS) (width 0.12))
(fp_line (start 14.08 34.35) (end 14.08 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 14.08 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.39) (end -1.33 34.41) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 34.41) (end 16.57 34.41) (layer F.SilkS) (width 0.12))
(fp_line (start 16.57 34.41) (end 16.57 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 16.57 -1.39) (end -1.33 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.55 -1.6) (end -1.55 34.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 34.65) (end 16.8 34.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.8 34.65) (end 16.8 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.8 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 7.62 16.51 270) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 90 "Net-(C1-Pad1)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 15 thru_hole oval (at 15.24 33.02 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 16 thru_hole oval (at 15.24 30.48 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 3 thru_hole oval (at 0 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 17 thru_hole oval (at 15.24 27.94 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 4 thru_hole oval (at 0 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 18 thru_hole oval (at 15.24 25.4 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 5 thru_hole oval (at 0 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 19 thru_hole oval (at 15.24 22.86 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 6 thru_hole oval (at 0 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 "Net-(J0-Pad6)"))
(pad 20 thru_hole oval (at 15.24 20.32 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(net 10 "Net-(J0-Pad1)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 7 thru_hole oval (at 0 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 21 thru_hole oval (at 15.24 17.78 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 8 thru_hole oval (at 0 17.78 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 22 thru_hole oval (at 15.24 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 9 thru_hole oval (at 0 20.32 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 23 thru_hole oval (at 15.24 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 10 thru_hole oval (at 0 22.86 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 24 thru_hole oval (at 15.24 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 11 thru_hole oval (at 0 25.4 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 25 thru_hole oval (at 15.24 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 12 thru_hole oval (at 0 27.94 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 26 thru_hole oval (at 15.24 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 13 thru_hole oval (at 0 30.48 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 27 thru_hole oval (at 15.24 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(pad 14 thru_hole oval (at 0 33.02 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-28_W15.24mm_Socket.wrl
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(module "Apple2:Apple II Expansion Edge Connector" (layer F.Cu) (tedit 5FB6E0FA) (tstamp 5FB687BE)
(at 138.505001 110.49)
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(fp_text reference J0 (at 0 0.5) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value "Apple II Expansion Bus" (at 9.652 -5.08) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text user "26 GND" (at 45.974 10.922 45) (layer F.Fab)
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Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text user "27 DMA IN" (at 42.799 11.43 45) (layer F.Fab)
(effects (font (size 0.762 0.762) (thickness 0.127)))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text user "28 INT IN" (at 40.386 11.303 45) (layer F.Fab)
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Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text user "29 _NMI" (at 38.1 10.922 45) (layer F.Fab)
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Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text user "30 _IRQ" (at 35.687 10.922 45) (layer F.Fab)
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Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_line (start -15.875 1.27) (end -16.51 1.27) (layer F.Fab) (width 0.15))
(fp_line (start -15.875 7.62) (end -15.875 1.27) (layer F.Fab) (width 0.15))
(fp_line (start 48.895 1.27) (end 49.53 1.27) (layer F.Fab) (width 0.15))
(fp_line (start 48.895 7.62) (end 48.895 1.27) (layer F.Fab) (width 0.15))
(pad 50 connect roundrect (at -13.97 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
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(pad 49 connect roundrect (at -11.43 5.08) (size 1.27 7.62) (layers B.Cu B.Mask) (roundrect_rratio 0.25)
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Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(module Package_DIP:DIP-14_W7.62mm (layer F.Cu) (tedit 5FB6A63A) (tstamp 5FB68898)
(at 156.21 55.245)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FB50A31)
(fp_text reference U3 (at 3.81 -2.33) (layer F.Fab)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_text value 74LS32 (at 3.875 7.55 90) (layer F.SilkS)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_arc (start 2 2) (end 1.450001 2.774999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 2.775) (end 1.45 3.35) (layer F.SilkS) (width 0.12))
(fp_line (start 2.55 3.35) (end 2.55 2.8) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.55 3.35) (end 1.45 3.35) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.448537 3.320952) (end 2.548537 3.320952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.475 4.825) (end 4.925001 5.599999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_arc (start 6.025 6.175) (end 4.925 6.175) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_arc (start 4.923537 6.145952) (end 6.023537 6.145952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_line (start 6.025 6.175) (end 6.025 5.625) (layer F.SilkS) (width 0.12))
(fp_line (start 4.925 5.6) (end 4.925 6.175) (layer F.SilkS) (width 0.12))
(fp_line (start 1.175 2.375) (end 1.75 2.375) (layer F.SilkS) (width 0.12))
(fp_line (start 1.75 2.375) (end 1.75 2.925) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 2.875) (end 2.225 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 0) (end 1.175 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 4.275) (end 1.95 5.025) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 5.025) (end 1.175 5.025) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 7.15) (end 5.475 7.675) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 7.675) (end 6.425 7.675) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 5.1) (end 5.725 5.1) (layer F.SilkS) (width 0.12))
(fp_line (start 5.725 5.1) (end 5.725 5.75) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 2.55) (end 5.25 2.55) (layer F.SilkS) (width 0.12))
(fp_line (start 5.25 2.55) (end 5.25 5.7) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 12.772) (end 1.175 12.772) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 12.022) (end 1.95 12.772) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 7.747) (end 1.175 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 10.622) (end 2.225 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 1.75 10.122) (end 1.75 10.672) (layer F.SilkS) (width 0.12))
(fp_line (start 1.175 10.122) (end 1.75 10.122) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.448537 11.067952) (end 2.548537 11.067952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.55 11.097) (end 1.45 11.097) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_line (start 2.55 11.097) (end 2.55 10.547) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 10.522) (end 1.45 11.097) (layer F.SilkS) (width 0.12))
(fp_arc (start 2 9.747) (end 1.450001 10.521999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.475 12.445) (end 4.925001 13.219999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_line (start 4.925 13.22) (end 4.925 13.795) (layer F.SilkS) (width 0.12))
(fp_line (start 6.025 13.795) (end 6.025 13.245) (layer F.SilkS) (width 0.12))
(fp_arc (start 4.923537 13.765952) (end 6.023537 13.765952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 10.17) (end 5.25 10.17) (layer F.SilkS) (width 0.12))
(fp_line (start 5.725 12.72) (end 5.725 13.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 12.72) (end 5.725 12.72) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 15.295) (end 6.425 15.295) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 14.77) (end 5.475 15.295) (layer F.SilkS) (width 0.12))
(fp_line (start 5.25 10.17) (end 5.25 13.32) (layer F.SilkS) (width 0.12))
(fp_arc (start 6.025 13.795) (end 4.925 13.795) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 87 "Net-(U3-Pad1)"))
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(U3-Pad8)"))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(J0-Pad41)"))
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(J0-Pad41)"))
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(U3-Pad3)"))
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 88 "Net-(U3-Pad10)"))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 81 "Net-(U0-Pad1)"))
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 88 "Net-(U3-Pad10)"))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(J0-Pad2)"))
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 85 "Net-(U2-Pad8)"))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 87 "Net-(U3-Pad1)"))
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(J0-Pad3)"))
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 89 "Net-(C1-Pad2)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(C1-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-14_W7.62mm (layer F.Cu) (tedit 5FB69AA2) (tstamp 5FB68876)
(at 180.7718 55.245)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FD4E618)
(fp_text reference U2 (at 3.81 -2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS00 (at 3.875 7.75 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 7.62) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.55194 3.06832) (end 2.50444 3.06832) (layer F.SilkS) (width 0.12))
(fp_line (start 1.5494 3.08102) (end 1.5494 3.66776) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.03454 3.683) (end 1.5494 3.683) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.04724 4.35864) (end 2.062479 4.221481) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 2.52476 3.67538) (end 2.52476 3.0734) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.99898 11.72718) (end 1.51384 11.72718) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.01168 12.40282) (end 2.026919 12.265661) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 1.51638 11.1125) (end 2.46888 11.1125) (layer F.SilkS) (width 0.12))
(fp_line (start 2.4892 11.71956) (end 2.4892 11.11758) (layer F.SilkS) (width 0.12))
(fp_line (start 1.51384 11.1252) (end 1.51384 11.71194) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6769 6.4897) (end 5.19176 6.4897) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6896 7.16534) (end 5.704839 7.028181) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 5.1943 5.87502) (end 6.1468 5.87502) (layer F.SilkS) (width 0.12))
(fp_line (start 6.16712 6.48208) (end 6.16712 5.8801) (layer F.SilkS) (width 0.12))
(fp_line (start 5.19176 5.88772) (end 5.19176 6.47446) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6769 13.79982) (end 5.19176 13.79982) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6896 14.47546) (end 5.704839 14.338301) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 5.1943 13.18514) (end 6.1468 13.18514) (layer F.SilkS) (width 0.12))
(fp_line (start 6.16712 13.7922) (end 6.16712 13.19022) (layer F.SilkS) (width 0.12))
(fp_line (start 5.19176 13.19784) (end 5.19176 13.78458) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 0) (end 2.286 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 0) (end 2.286 3.048) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 2.54) (end 1.905 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 1.905 2.54) (end 1.905 3.048) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 5.08) (end 2.032 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 5.08) (end 2.032 4.572) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 11.049) (end 2.286 7.62) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 7.62) (end 1.143 7.62) (layer F.SilkS) (width 0.12))
(fp_line (start 1.778 11.049) (end 1.778 10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 1.778 10.16) (end 1.143 10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 12.573) (end 2.032 12.954) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 12.954) (end 1.143 12.954) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 5.842) (end 5.461 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 2.54) (end 6.477 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 5.842) (end 5.842 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 5.08) (end 6.477 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 6.477 7.747) (end 5.715 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 5.715 7.747) (end 5.715 7.366) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 13.081) (end 5.461 10.287) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 10.287) (end 6.477 10.287) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 13.081) (end 5.842 12.7) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 12.7) (end 6.477 12.7) (layer F.SilkS) (width 0.12))
(fp_line (start 6.477 15.367) (end 5.715 15.367) (layer F.SilkS) (width 0.12))
(fp_line (start 5.715 15.367) (end 5.715 14.605) (layer F.SilkS) (width 0.12))
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(C1-Pad1)"))
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 89 "Net-(C1-Pad2)"))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 "Net-(J0-Pad18)"))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 83 "Net-(U0-Pad19)"))
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 "Net-(J0-Pad18)"))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(U2-Pad3)"))
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 81 "Net-(U0-Pad1)"))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(U2-Pad3)"))
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 81 "Net-(U0-Pad1)"))
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(U2-Pad3)"))
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 81 "Net-(U0-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(J0-Pad1)"))
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 85 "Net-(U2-Pad8)"))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(J0-Pad41)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB68824)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(at 123.952 102.87 90)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FA15F43)
(fp_text reference U0 (at 3.81 -2.33 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS245 (at 3.81 25.19 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 81 "Net-(U0-Pad1)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 "Net-(U0-Pad11)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 51 "Net-(J0-Pad49)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(U0-Pad12)"))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 50 "Net-(J0-Pad48)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(U0-Pad13)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 49 "Net-(J0-Pad47)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 "Net-(U0-Pad14)"))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 48 "Net-(J0-Pad46)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 47 "Net-(J0-Pad45)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 20 "Net-(U0-Pad16)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 46 "Net-(J0-Pad44)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U0-Pad17)"))
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 45 "Net-(J0-Pad43)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(U0-Pad18)"))
(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 82 "Net-(J0-Pad42)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 83 "Net-(U0-Pad19)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 89 "Net-(C1-Pad2)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 90 "Net-(C1-Pad1)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5FB688C0)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(at 123.825 90.805 90)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5FA19168)
(fp_text reference U4 (at 3.81 -2.33 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LVC245 (at 3.81 25.19 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 11.43 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 20 thru_hole oval (at 7.62 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 91 "Net-(C5-Pad1)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 10 thru_hole oval (at 0 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 89 "Net-(C1-Pad2)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 19 thru_hole oval (at 7.62 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 92 "Net-(U3-Pad3)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 9 thru_hole oval (at 0 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 "Net-(U0-Pad11)"))
(pad 18 thru_hole oval (at 7.62 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 55 "Net-(J1-Pad7)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(U0-Pad12)"))
(pad 17 thru_hole oval (at 7.62 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 58 "Net-(J1-Pad11)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 "Net-(U0-Pad13)"))
(pad 16 thru_hole oval (at 7.62 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 60 "Net-(J1-Pad13)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 "Net-(U0-Pad14)"))
(pad 15 thru_hole oval (at 7.62 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 61 "Net-(J1-Pad15)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(U0-Pad15)"))
(pad 14 thru_hole oval (at 7.62 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 64 "Net-(J1-Pad19)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 20 "Net-(U0-Pad16)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 13 thru_hole oval (at 7.62 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 65 "Net-(J1-Pad21)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 19 "Net-(U0-Pad17)"))
(pad 12 thru_hole oval (at 7.62 20.32 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 67 "Net-(J1-Pad23)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(U0-Pad18)"))
(pad 11 thru_hole oval (at 7.62 22.86 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 72 "Net-(J1-Pad29)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(net 89 "Net-(C1-Pad2)"))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(gr_line (start 193.675 42.545) (end 193.04 41.91) (layer Edge.Cuts) (width 0.05))
(gr_line (start 193.675 111.125) (end 193.675 42.545) (layer Edge.Cuts) (width 0.05))
(gr_line (start 104.775 41.91) (end 193.04 41.91) (layer Edge.Cuts) (width 0.05))
(gr_line (start 104.14 42.545) (end 104.775 41.91) (layer Edge.Cuts) (width 0.05))
(gr_line (start 104.14 111.125) (end 104.14 42.545) (layer Edge.Cuts) (width 0.05))
(gr_line (start 104.775 111.76) (end 104.14 111.125) (layer Edge.Cuts) (width 0.05))
(gr_line (start 108.585 111.76) (end 104.775 111.76) (layer Edge.Cuts) (width 0.05))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(gr_text "74LVC245 Input Level Shifter\n(Control bits)" (at 135.89 61.595) (layer F.SilkS) (tstamp 5FF7F125)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_text "74LVC374 Output Level Shifter \n+ EPROM high address" (at 135.89 48.895) (layer F.SilkS) (tstamp 5FF7F11D)
(effects (font (size 1 1) (thickness 0.15)))
)
(gr_line (start 123.19 119.38) (end 186.69 119.38) (layer Edge.Cuts) (width 0.05))
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(gr_line (start 122.555 111.76) (end 122.555 118.745) (layer Edge.Cuts) (width 0.05))
(gr_line (start 108.585 111.76) (end 122.555 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 193.04 111.76) (end 193.675 111.125) (layer Edge.Cuts) (width 0.05))
(gr_line (start 187.325 111.76) (end 193.04 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 187.325 118.745) (end 187.325 111.76) (layer Edge.Cuts) (width 0.05))
(gr_line (start 186.69 119.38) (end 187.325 118.745) (layer Edge.Cuts) (width 0.05))
(gr_text "https://github.com/tjboldt/Apple2-IO-RPi\nThird Protoype 2020-Dec-29\n(c)2020 Terence J. Boldt" (at 160.02 107.95) (layer B.SilkS)
Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
(effects (font (size 1 1) (thickness 0.15)) (justify left mirror))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(gr_text "74LVC374 Output Level Shifter\n(Primary Data)" (at 135.255 74.295) (layer F.SilkS)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(gr_text "74LVC245 Input Level Shifter\n(Primary Data)" (at 135.89 86.995) (layer F.SilkS)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(gr_text "74LS245 Data Bus Buffer" (at 135.255 99.06) (layer F.SilkS)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(gr_text "Attach Raspberry Pi Zero W facing outward from card" (at 115.951 76.708 90) (layer F.SilkS)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)))
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(gr_line (start 169.2555 70.461) (end 169.2555 71.385) (layer Dwgs.User) (width 0.14))
(gr_line (start 165.108 78.105) (end 165.108 76.845) (layer Dwgs.User) (width 0.14))
(gr_line (start 170.3475 73.758) (end 168.258 73.758) (layer Dwgs.User) (width 0.14))
(gr_line (start 166.158 65.757) (end 166.158 68.004) (layer Dwgs.User) (width 0.14))
(gr_line (start 168.783 80.772) (end 168.783 79.512) (layer Dwgs.User) (width 0.14))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(gr_text "27256 EPROM\nFirmware at $Cn00 - $CnFF\nWhere n = slot number" (at 158.806325 89.283162) (layer F.SilkS)
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
(effects (font (size 1 1) (thickness 0.15)) (justify left))
)
(gr_line (start 191.77 57.785) (end 191.77 111.76) (layer Dwgs.User) (width 0.15))
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(gr_line (start 188.595 111.76) (end 189.865 111.76) (layer Dwgs.User) (width 0.15))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 180.415001 111.409815) (end 180.415001 115.57) (width 0.1778) (layer F.Cu) (net 31))
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Update schematic/PCB to work with more EPROM types
2020-12-14 03:19:04 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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(segment (start 135.458299 75.4126) (end 135.458299 77.089) (width 0.1778) (layer B.Cu) (net 57))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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(segment (start 134.9756 84.347985) (end 134.9756 84.8868) (width 0.1778) (layer B.Cu) (net 59))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 133.985 65.405) (end 133.985 66.9544) (width 0.1778) (layer B.Cu) (net 59))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 132.867311 68.072089) (end 132.867311 72.99961) (width 0.1778) (layer B.Cu) (net 59))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 133.985 66.9544) (end 132.867311 68.072089) (width 0.1778) (layer B.Cu) (net 59))
(segment (start 132.867311 72.99961) (end 135.051701 75.184) (width 0.1778) (layer B.Cu) (net 59))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 135.051701 75.184) (end 135.051701 84.271884) (width 0.1778) (layer B.Cu) (net 59))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 135.051701 84.271884) (end 134.9756 84.347985) (width 0.1778) (layer B.Cu) (net 59))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 120.964573 84.506709) (end 122.606709 84.506709) (width 0.1778) (layer F.Cu) (net 60))
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(segment (start 122.606709 84.506709) (end 122.910609 84.810609) (width 0.1778) (layer F.Cu) (net 60))
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(segment (start 136.525 83.185) (end 135.4582 82.1182) (width 0.1778) (layer F.Cu) (net 61))
(segment (start 135.4582 82.1182) (end 135.1534 81.8134) (width 0.1778) (layer F.Cu) (net 61))
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(segment (start 113.03 82.804) (end 114.6048 84.3788) (width 0.1778) (layer F.Cu) (net 62))
(segment (start 114.6048 84.3788) (end 117.7798 84.3788) (width 0.1778) (layer F.Cu) (net 62))
(segment (start 117.7798 81.895698) (end 117.7798 82.5246) (width 0.1778) (layer B.Cu) (net 62))
(segment (start 118.999 80.676498) (end 117.7798 81.895698) (width 0.1778) (layer B.Cu) (net 62))
(segment (start 117.7798 84.3788) (end 117.7798 82.5246) (width 0.1778) (layer B.Cu) (net 62))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(via (at 118.4275 67.4878) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 62))
(segment (start 118.745001 67.805301) (end 118.4275 67.4878) (width 0.1778) (layer F.Cu) (net 62))
(segment (start 126.828297 67.805301) (end 118.745001 67.805301) (width 0.1778) (layer F.Cu) (net 62))
(segment (start 127.165101 67.468497) (end 126.828297 67.805301) (width 0.1778) (layer F.Cu) (net 62))
(segment (start 126.365 65.405) (end 127.165101 66.205101) (width 0.1778) (layer F.Cu) (net 62))
(segment (start 127.165101 66.205101) (end 127.165101 67.468497) (width 0.1778) (layer F.Cu) (net 62))
(segment (start 119.075289 76.479311) (end 118.999 76.5556) (width 0.1778) (layer B.Cu) (net 62))
(segment (start 119.075289 73.310488) (end 119.075289 76.479311) (width 0.1778) (layer B.Cu) (net 62))
(segment (start 118.135498 71.748903) (end 118.135498 72.370697) (width 0.1778) (layer B.Cu) (net 62))
(segment (start 118.4275 71.456901) (end 118.135498 71.748903) (width 0.1778) (layer B.Cu) (net 62))
(segment (start 118.4275 67.4878) (end 118.4275 68.6054) (width 0.1778) (layer B.Cu) (net 62))
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(segment (start 118.4275 68.6054) (end 118.4275 69.348098) (width 0.1778) (layer B.Cu) (net 62))
(segment (start 118.135498 72.370697) (end 119.075289 73.310488) (width 0.1778) (layer B.Cu) (net 62))
(segment (start 118.999 76.5556) (end 118.999 80.676498) (width 0.1778) (layer B.Cu) (net 62))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 137.324999 44.285001) (end 136.525 45.085) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 137.591701 44.018299) (end 137.324999 44.285001) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 145.618299 44.018299) (end 137.591701 44.018299) (width 0.1778) (layer F.Cu) (net 63))
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(segment (start 113.03 80.264) (end 115.8113 80.264) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 115.8113 80.264) (end 117.1321 81.5848) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 117.1321 81.5848) (end 117.1321 75.596498) (width 0.1778) (layer B.Cu) (net 63))
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(segment (start 132.918299 53.217017) (end 136.419581 56.718299) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 136.525 45.085) (end 132.918299 48.691701) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 132.918299 48.691701) (end 132.918299 53.217017) (width 0.1778) (layer B.Cu) (net 63))
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(segment (start 137.591701 58.648699) (end 136.3726 59.8678) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 137.337899 56.718299) (end 137.591701 56.972101) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 137.591701 56.972101) (end 137.591701 58.648699) (width 0.1778) (layer B.Cu) (net 63))
(via (at 116.6114 60.2996) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 63))
(segment (start 119.680882 60.2996) (end 116.6114 60.2996) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 120.772983 61.391701) (end 119.680882 60.2996) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 121.797017 61.391701) (end 120.772983 61.391701) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 136.3726 59.8678) (end 123.320918 59.8678) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 123.320918 59.8678) (end 121.797017 61.391701) (width 0.1778) (layer F.Cu) (net 63))
(segment (start 116.230401 60.680599) (end 116.230401 62.611001) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 116.6114 60.2996) (end 116.230401 60.680599) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 116.928901 65.620899) (end 116.10342 66.44638) (width 0.1778) (layer B.Cu) (net 63))
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(segment (start 116.928901 63.309501) (end 116.928901 65.620899) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 118.249701 74.478897) (end 118.249701 74.326497) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 117.1321 75.596498) (end 118.249701 74.478897) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 117.957609 73.329486) (end 117.627723 72.9996) (width 0.1778) (layer B.Cu) (net 63))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 118.249701 74.326497) (end 118.249701 74.1426) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 118.249701 74.1426) (end 118.249701 73.704703) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 116.10342 66.44638) (end 116.10342 69.2404) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 116.10342 69.2404) (end 116.10342 70.5358) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 118.249701 73.621578) (end 118.249701 74.1426) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 116.10342 71.475297) (end 118.249701 73.621578) (width 0.1778) (layer B.Cu) (net 63))
(segment (start 116.10342 69.2404) (end 116.10342 71.475297) (width 0.1778) (layer B.Cu) (net 63))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 110.49 77.724) (end 111.339999 78.573999) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 111.339999 78.573999) (end 111.720999 78.573999) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 111.720999 78.573999) (end 112.294299 79.147299) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 112.294299 79.147299) (end 116.218793 79.147299) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 116.218793 79.147299) (end 118.072094 81.0006) (width 0.1778) (layer F.Cu) (net 64))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 118.072094 81.0006) (end 118.8974 81.0006) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 118.8974 81.0006) (end 119.1768 81.28) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 137.159992 81.279992) (end 137.3632 81.4832) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 119.176808 81.279992) (end 137.159992 81.279992) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 119.1768 81.28) (end 119.176808 81.279992) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 137.3632 81.4832) (end 139.065 83.185) (width 0.1778) (layer F.Cu) (net 64))
(segment (start 139.319 80.899) (end 141.605 83.185) (width 0.1778) (layer F.Cu) (net 65))
(segment (start 119.5578 80.6196) (end 119.8372 80.899) (width 0.1778) (layer F.Cu) (net 65))
(segment (start 111.837099 76.531099) (end 114.605699 76.531099) (width 0.1778) (layer F.Cu) (net 65))
(segment (start 110.49 75.184) (end 111.837099 76.531099) (width 0.1778) (layer F.Cu) (net 65))
(segment (start 114.605699 76.531099) (end 115.3922 77.3176) (width 0.1778) (layer F.Cu) (net 65))
(segment (start 115.3922 77.3176) (end 115.3922 77.3684) (width 0.1778) (layer F.Cu) (net 65))
(segment (start 119.8372 80.899) (end 139.319 80.899) (width 0.1778) (layer F.Cu) (net 65))
(segment (start 115.3922 77.3684) (end 118.6434 80.6196) (width 0.1778) (layer F.Cu) (net 65))
(segment (start 118.6434 80.6196) (end 119.5578 80.6196) (width 0.1778) (layer F.Cu) (net 65))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 135.89 46.99) (end 133.985 45.085) (width 0.1778) (layer F.Cu) (net 66))
(segment (start 144.145 45.085) (end 142.24 46.99) (width 0.1778) (layer F.Cu) (net 66))
(segment (start 142.24 46.99) (end 135.89 46.99) (width 0.1778) (layer F.Cu) (net 66))
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(via (at 117.475 53.975) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 66))
(segment (start 131.025999 54.636293) (end 118.136293 54.636293) (width 0.1778) (layer F.Cu) (net 66))
(segment (start 118.136293 54.636293) (end 117.475 53.975) (width 0.1778) (layer F.Cu) (net 66))
(segment (start 113.284 74.93) (end 113.03 75.184) (width 0.1778) (layer F.Cu) (net 66))
(segment (start 131.025999 53.835399) (end 131.025999 54.636293) (width 0.1778) (layer B.Cu) (net 66))
(segment (start 130.962301 53.771701) (end 131.025999 53.835399) (width 0.1778) (layer B.Cu) (net 66))
(segment (start 130.784501 53.771701) (end 130.962301 53.771701) (width 0.1778) (layer B.Cu) (net 66))
(segment (start 130.378299 53.365499) (end 130.784501 53.771701) (width 0.1778) (layer B.Cu) (net 66))
(segment (start 133.985 45.085) (end 130.378299 48.691701) (width 0.1778) (layer B.Cu) (net 66))
(segment (start 130.378299 48.691701) (end 130.378299 53.365499) (width 0.1778) (layer B.Cu) (net 66))
(segment (start 117.475 53.975) (end 115.3922 56.0578) (width 0.1778) (layer B.Cu) (net 66))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(via (at 116.4082 75.4126) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 66))
(segment (start 113.03 75.184) (end 116.1796 75.184) (width 0.1778) (layer F.Cu) (net 66))
(segment (start 116.1796 75.184) (end 116.4082 75.4126) (width 0.1778) (layer F.Cu) (net 66))
(segment (start 115.3922 73.857785) (end 115.3922 70.9168) (width 0.1778) (layer B.Cu) (net 66))
(segment (start 116.4082 74.873785) (end 115.3922 73.857785) (width 0.1778) (layer B.Cu) (net 66))
(segment (start 116.4082 75.4126) (end 116.4082 74.873785) (width 0.1778) (layer B.Cu) (net 66))
(segment (start 115.3922 56.0578) (end 115.3922 70.9168) (width 0.1778) (layer B.Cu) (net 66))
(segment (start 115.3922 70.9168) (end 115.3922 71.5772) (width 0.1778) (layer B.Cu) (net 66))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 111.339999 73.493999) (end 110.49 72.644) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 111.606701 73.760701) (end 111.339999 73.493999) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 114.224699 73.760701) (end 111.606701 73.760701) (width 0.1778) (layer F.Cu) (net 67))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 141.503391 80.543391) (end 144.145 83.185) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 120.141991 80.543391) (end 141.503391 80.543391) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 119.86259 80.26399) (end 120.141991 80.543391) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 110.49 72.644) (end 111.633 73.787) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 111.633 73.787) (end 115.9002 73.787) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 115.9002 73.787) (end 117.1448 75.0316) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 117.1448 75.0316) (end 117.1448 78.3336) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 117.1448 78.3336) (end 119.07519 80.26399) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 119.07519 80.26399) (end 119.86259 80.26399) (width 0.1778) (layer F.Cu) (net 67))
(segment (start 139.577017 46.151701) (end 140.643718 45.085) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 131.445 45.085) (end 132.511701 44.018299) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 140.643718 45.085) (end 141.605 45.085) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 132.511701 44.018299) (end 134.497017 44.018299) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 134.497017 44.018299) (end 135.051701 44.572983) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 135.051701 44.572983) (end 135.051701 45.190419) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 135.051701 45.190419) (end 136.012983 46.151701) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 136.012983 46.151701) (end 139.577017 46.151701) (width 0.1778) (layer F.Cu) (net 68))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 130.645001 44.285001) (end 131.445 45.085) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 130.378299 44.018299) (end 130.645001 44.285001) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 111.658301 44.018299) (end 130.378299 44.018299) (width 0.1778) (layer F.Cu) (net 68))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 108.4072 69.786694) (end 108.4072 47.2694) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 109.917407 71.296901) (end 108.4072 69.786694) (width 0.1778) (layer F.Cu) (net 68))
(segment (start 111.682901 71.296901) (end 109.917407 71.296901) (width 0.1778) (layer F.Cu) (net 68))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 108.4072 47.2694) (end 111.658301 44.018299) (width 0.1778) (layer F.Cu) (net 68))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 113.03 72.644) (end 111.682901 71.296901) (width 0.1778) (layer F.Cu) (net 68))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(via (at 137.795 48.2727) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 69))
(segment (start 139.065 45.085) (end 139.065 47.0027) (width 0.1778) (layer B.Cu) (net 69))
(segment (start 139.065 47.0027) (end 137.795 48.2727) (width 0.1778) (layer B.Cu) (net 69))
(via (at 128.905 48.2727) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 69))
(segment (start 137.795 48.2727) (end 128.905 48.2727) (width 0.1778) (layer F.Cu) (net 69))
(segment (start 128.905 48.2727) (end 128.905 45.085) (width 0.1778) (layer B.Cu) (net 69))
(segment (start 109.953983 68.680701) (end 109.0422 67.768918) (width 0.1778) (layer F.Cu) (net 69))
(segment (start 113.03 70.104) (end 111.606701 68.680701) (width 0.1778) (layer F.Cu) (net 69))
(segment (start 111.606701 68.680701) (end 109.953983 68.680701) (width 0.1778) (layer F.Cu) (net 69))
(segment (start 128.524001 48.653699) (end 128.905 48.2727) (width 0.1778) (layer F.Cu) (net 69))
(segment (start 128.485999 48.691701) (end 128.524001 48.653699) (width 0.1778) (layer F.Cu) (net 69))
(segment (start 112.356805 48.691701) (end 128.485999 48.691701) (width 0.1778) (layer F.Cu) (net 69))
(segment (start 109.0422 52.006306) (end 112.356805 48.691701) (width 0.1778) (layer F.Cu) (net 69))
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(segment (start 111.339999 65.873999) (end 110.49 65.024) (width 0.1778) (layer F.Cu) (net 72))
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(segment (start 116.478985 66.4972) (end 116.198686 66.216901) (width 0.1778) (layer F.Cu) (net 72))
(segment (start 117.0178 66.4972) (end 116.478985 66.4972) (width 0.1778) (layer F.Cu) (net 72))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 143.6624 80.1624) (end 146.685 83.185) (width 0.1778) (layer F.Cu) (net 72))
(segment (start 118.3513 75.980431) (end 118.745 76.374131) (width 0.1778) (layer F.Cu) (net 72))
(segment (start 118.745 76.374131) (end 118.745 78.9432) (width 0.1778) (layer F.Cu) (net 72))
(segment (start 118.745 78.9432) (end 119.4816 79.6798) (width 0.1778) (layer F.Cu) (net 72))
(segment (start 119.4816 79.6798) (end 120.2182 79.6798) (width 0.1778) (layer F.Cu) (net 72))
(segment (start 120.2182 79.6798) (end 120.7008 80.1624) (width 0.1778) (layer F.Cu) (net 72))
(segment (start 120.7008 80.1624) (end 143.6624 80.1624) (width 0.1778) (layer F.Cu) (net 72))
(segment (start 118.3513 75.441616) (end 118.3513 75.980431) (width 0.1778) (layer B.Cu) (net 72))
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(segment (start 116.59869 71.336797) (end 118.719679 73.457786) (width 0.1778) (layer B.Cu) (net 72))
(segment (start 116.59869 66.91631) (end 116.59869 71.336797) (width 0.1778) (layer B.Cu) (net 72))
(segment (start 117.0178 66.4972) (end 116.59869 66.91631) (width 0.1778) (layer B.Cu) (net 72))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(via (at 117.602 74.0156) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 73))
(segment (start 117.718101 74.131701) (end 117.602 74.0156) (width 0.1778) (layer F.Cu) (net 73))
(segment (start 111.339999 63.333999) (end 110.49 62.484) (width 0.1778) (layer F.Cu) (net 73))
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(segment (start 116.2812 63.600701) (end 111.606701 63.600701) (width 0.1778) (layer F.Cu) (net 73))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 117.982999 74.396599) (end 117.602 74.0156) (width 0.1778) (layer F.Cu) (net 73))
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(segment (start 115.74781 64.134091) (end 116.2812 63.600701) (width 0.1778) (layer B.Cu) (net 73))
(segment (start 115.74781 71.622595) (end 115.74781 64.134091) (width 0.1778) (layer B.Cu) (net 73))
(segment (start 117.221001 73.095786) (end 115.74781 71.622595) (width 0.1778) (layer B.Cu) (net 73))
(segment (start 117.221001 73.634601) (end 117.221001 73.095786) (width 0.1778) (layer B.Cu) (net 73))
(segment (start 117.602 74.0156) (end 117.221001 73.634601) (width 0.1778) (layer B.Cu) (net 73))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 113.03 62.484) (end 118.2116 62.484) (width 0.1778) (layer F.Cu) (net 74))
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(segment (start 133.985 78.105) (end 133.985 76.339799) (width 0.1778) (layer B.Cu) (net 75))
(segment (start 133.985 76.339799) (end 133.2484 75.603199) (width 0.1778) (layer B.Cu) (net 75))
(segment (start 122.938017 73.139299) (end 122.351701 72.552983) (width 0.1778) (layer F.Cu) (net 75))
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(segment (start 118.8447 71.998299) (end 118.783199 72.0598) (width 0.1778) (layer F.Cu) (net 75))
(segment (start 122.351701 72.552983) (end 121.797017 71.998299) (width 0.1778) (layer F.Cu) (net 75))
(segment (start 121.797017 71.998299) (end 118.8447 71.998299) (width 0.1778) (layer F.Cu) (net 75))
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(segment (start 111.339999 60.793999) (end 110.49 59.944) (width 0.1778) (layer F.Cu) (net 75))
(segment (start 111.682901 61.136901) (end 111.339999 60.793999) (width 0.1778) (layer F.Cu) (net 75))
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(segment (start 118.244384 61.1632) (end 118.218085 61.136901) (width 0.1778) (layer F.Cu) (net 75))
(segment (start 118.783199 61.1632) (end 118.244384 61.1632) (width 0.1778) (layer F.Cu) (net 75))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 118.783199 71.2216) (end 118.783199 72.0598) (width 0.1778) (layer B.Cu) (net 75))
(segment (start 119.0752 70.929599) (end 118.783199 71.2216) (width 0.1778) (layer B.Cu) (net 75))
(segment (start 119.0752 64.7446) (end 119.0752 70.929599) (width 0.1778) (layer B.Cu) (net 75))
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(segment (start 118.783199 61.1632) (end 118.783199 64.452599) (width 0.1778) (layer B.Cu) (net 75))
(segment (start 123.558299 73.139299) (end 123.1646 73.139299) (width 0.1778) (layer F.Cu) (net 75))
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(segment (start 133.2484 75.603199) (end 126.022199 75.603199) (width 0.1778) (layer F.Cu) (net 75))
(segment (start 123.1646 73.139299) (end 122.938017 73.139299) (width 0.1778) (layer F.Cu) (net 75))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(via (at 117.5004 69.3166) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 76))
(segment (start 117.7798 69.0372) (end 117.5004 69.3166) (width 0.1778) (layer F.Cu) (net 76))
(via (at 117.0432 56.7182) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 76))
(segment (start 111.339999 56.554001) (end 110.49 57.404) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 111.606701 56.287299) (end 111.339999 56.554001) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 113.950391 56.287299) (end 111.606701 56.287299) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 114.381292 56.7182) (end 113.950391 56.287299) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 117.0432 56.7182) (end 114.381292 56.7182) (width 0.1778) (layer F.Cu) (net 76))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 117.7544 57.4294) (end 117.0432 56.7182) (width 0.1778) (layer B.Cu) (net 76))
(segment (start 117.7544 66.719198) (end 117.7544 57.4294) (width 0.1778) (layer B.Cu) (net 76))
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(segment (start 116.954299 68.770499) (end 116.954299 67.519299) (width 0.1778) (layer B.Cu) (net 76))
(segment (start 117.5004 69.3166) (end 116.954299 68.770499) (width 0.1778) (layer B.Cu) (net 76))
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(segment (start 135.051701 71.869201) (end 136.271 73.0885) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 135.051701 69.976901) (end 135.051701 71.869201) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 134.112 69.0372) (end 135.051701 69.976901) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 134.112 69.0372) (end 117.7798 69.0372) (width 0.1778) (layer F.Cu) (net 76))
(segment (start 136.271 76.9112) (end 136.525 77.1652) (width 0.1778) (layer B.Cu) (net 76))
(segment (start 136.271 73.0885) (end 136.271 76.9112) (width 0.1778) (layer B.Cu) (net 76))
(segment (start 136.525 78.105) (end 136.525 77.1652) (width 0.1778) (layer B.Cu) (net 76))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 114.232081 57.404) (end 116.035481 59.2074) (width 0.1778) (layer F.Cu) (net 77))
(segment (start 113.03 57.404) (end 114.232081 57.404) (width 0.1778) (layer F.Cu) (net 77))
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(segment (start 133.985 70.485) (end 135.051701 69.418299) (width 0.1778) (layer B.Cu) (net 77))
(segment (start 116.035481 59.2074) (end 134.6454 59.2074) (width 0.1778) (layer F.Cu) (net 77))
(segment (start 134.6454 59.2074) (end 134.7724 59.2074) (width 0.1778) (layer F.Cu) (net 77))
(segment (start 117.533305 54.991903) (end 117.988995 54.991903) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 116.288701 53.747299) (end 117.533305 54.991903) (width 0.1778) (layer F.Cu) (net 78))
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(segment (start 111.606701 53.747299) (end 116.288701 53.747299) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 125.971291 55.283994) (end 125.6792 54.991903) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 131.336896 55.283994) (end 125.971291 55.283994) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 117.988995 54.991903) (end 125.6792 54.991903) (width 0.1778) (layer F.Cu) (net 78))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 132.137889 54.483001) (end 131.78229 54.8386) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 132.112489 54.508401) (end 131.78229 54.8386) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 131.78229 54.8386) (end 131.336896 55.283994) (width 0.1778) (layer F.Cu) (net 78))
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(segment (start 142.671701 58.775501) (end 143.1544 59.2582) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 142.671701 55.092502) (end 142.671701 58.775501) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 142.0622 54.483001) (end 142.671701 55.092502) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 142.0622 54.483001) (end 132.137889 54.483001) (width 0.1778) (layer F.Cu) (net 78))
(segment (start 145.211701 77.038299) (end 145.0086 77.2414) (width 0.1778) (layer B.Cu) (net 78))
(segment (start 145.211701 64.892983) (end 145.211701 77.038299) (width 0.1778) (layer B.Cu) (net 78))
(segment (start 143.1544 62.835682) (end 145.211701 64.892983) (width 0.1778) (layer B.Cu) (net 78))
(segment (start 143.1544 59.2582) (end 143.1544 62.835682) (width 0.1778) (layer B.Cu) (net 78))
(segment (start 144.145 78.105) (end 145.0086 77.2414) (width 0.1778) (layer B.Cu) (net 78))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 113.03 54.864) (end 113.879999 55.713999) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 133.159401 55.26991) (end 133.096 55.372) (width 0.1778) (layer B.Cu) (net 79))
(via (at 133.159401 55.26991) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 79))
(segment (start 132.176497 55.713999) (end 125.9586 55.713999) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 132.620586 55.26991) (end 132.176497 55.713999) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 133.159401 55.26991) (end 132.620586 55.26991) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 113.879999 55.713999) (end 125.9586 55.713999) (width 0.1778) (layer F.Cu) (net 79))
(segment (start 125.9586 55.713999) (end 126.300599 55.713999) (width 0.1778) (layer F.Cu) (net 79))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 136.525 67.4116) (end 136.525 70.485) (width 0.1778) (layer B.Cu) (net 79))
(segment (start 135.458299 66.344899) (end 136.525 67.4116) (width 0.1778) (layer B.Cu) (net 79))
(segment (start 135.458299 57.568808) (end 135.458299 66.344899) (width 0.1778) (layer B.Cu) (net 79))
(segment (start 133.159401 55.26991) (end 135.458299 57.568808) (width 0.1778) (layer B.Cu) (net 79))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 144.145 70.485) (end 141.8336 68.1736) (width 0.1778) (layer F.Cu) (net 80))
(via (at 117.602 68.2244) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 80))
(segment (start 141.8336 68.1736) (end 117.6528 68.1736) (width 0.1778) (layer F.Cu) (net 80))
(segment (start 117.6528 68.1736) (end 117.602 68.2244) (width 0.1778) (layer F.Cu) (net 80))
(via (at 117.2718 52.451) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 80))
(segment (start 113.157 52.451) (end 113.03 52.324) (width 0.1778) (layer F.Cu) (net 80))
(segment (start 117.2718 52.451) (end 113.157 52.451) (width 0.1778) (layer F.Cu) (net 80))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 117.4242 52.451) (end 117.2718 52.451) (width 0.1778) (layer B.Cu) (net 80))
(segment (start 117.602 68.2244) (end 117.602 67.374506) (width 0.1778) (layer B.Cu) (net 80))
(segment (start 117.602 67.374506) (end 118.110009 66.866497) (width 0.1778) (layer B.Cu) (net 80))
(segment (start 118.110009 66.866497) (end 118.11001 66.49719) (width 0.1778) (layer B.Cu) (net 80))
(segment (start 118.11001 66.49719) (end 118.122701 66.484499) (width 0.1778) (layer B.Cu) (net 80))
(segment (start 118.122701 66.484499) (end 118.122701 53.149501) (width 0.1778) (layer B.Cu) (net 80))
(segment (start 118.122701 53.149501) (end 117.4242 52.451) (width 0.1778) (layer B.Cu) (net 80))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 187.591801 67.145001) (end 188.3918 67.945) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 187.325099 66.878299) (end 187.591801 67.145001) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 177.317301 66.878299) (end 187.325099 66.878299) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 176.3268 67.8688) (end 177.317301 66.878299) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 188.3918 66.81363) (end 188.3918 65.405) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 188.3918 67.945) (end 188.3918 66.81363) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 188.3918 64.27363) (end 188.3918 62.865) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 188.3918 65.405) (end 188.3918 64.27363) (width 0.1778) (layer B.Cu) (net 81))
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(segment (start 169.091718 66.675) (end 157.48 66.675) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 176.3268 67.8688) (end 175.133 66.675) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 175.133 66.675) (end 169.091718 66.675) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 157.48 64.135) (end 156.21 62.865) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 157.48 66.675) (end 157.48 64.135) (width 0.1778) (layer B.Cu) (net 81))
(via (at 146.05 97.601573) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 81))
(segment (start 130.198227 97.601573) (end 146.05 97.601573) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 123.952 102.87) (end 124.9298 102.87) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 124.9298 102.87) (end 130.198227 97.601573) (width 0.1778) (layer B.Cu) (net 81))
(via (at 149.86 97.601573) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 81))
(segment (start 146.05 97.601573) (end 149.86 97.601573) (width 0.1778) (layer F.Cu) (net 81))
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(segment (start 149.86 97.601573) (end 152.4 95.061573) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 152.4 95.061573) (end 152.4 64.135) (width 0.1778) (layer B.Cu) (net 81))
(segment (start 155.410001 63.664999) (end 156.21 62.865) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 155.410001 64.013998) (end 155.410001 63.664999) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 154.641298 64.782701) (end 155.410001 64.013998) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 154.008983 64.782701) (end 154.641298 64.782701) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 153.361282 64.135) (end 154.008983 64.782701) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 152.4 64.135) (end 153.361282 64.135) (width 0.1778) (layer F.Cu) (net 81))
(segment (start 144.855001 104.584371) (end 144.855001 115.57) (width 0.1778) (layer B.Cu) (net 82))
(segment (start 144.272 102.87) (end 144.272 104.00137) (width 0.1778) (layer B.Cu) (net 82))
(segment (start 144.272 104.00137) (end 144.855001 104.584371) (width 0.1778) (layer B.Cu) (net 82))
(segment (start 125.692001 94.450001) (end 126.492 95.25) (width 0.1778) (layer B.Cu) (net 83))
(segment (start 124.967901 93.725901) (end 125.692001 94.450001) (width 0.1778) (layer B.Cu) (net 83))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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(segment (start 109.640001 81.113999) (end 110.49 80.264) (width 0.3556) (layer F.Cu) (net 91))
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(segment (start 110.49 100.584) (end 109.2844 100.584) (width 0.3556) (layer F.Cu) (net 91))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 115.19529 83.185) (end 117.475 83.185) (width 0.3556) (layer F.Cu) (net 91))
(segment (start 113.479891 81.469601) (end 115.19529 83.185) (width 0.3556) (layer F.Cu) (net 91))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(segment (start 117.475 83.185) (end 123.825 83.185) (width 0.3556) (layer F.Cu) (net 91))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 111.695601 81.469601) (end 113.479891 81.469601) (width 0.3556) (layer F.Cu) (net 91))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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(segment (start 133.858 63.1698) (end 136.207499 63.1698) (width 0.1778) (layer F.Cu) (net 92))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 125.5522 73.787) (end 126.111 73.787) (width 0.1778) (layer B.Cu) (net 92))
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(segment (start 127.431701 75.7174) (end 127.431701 82.118299) (width 0.1778) (layer B.Cu) (net 92))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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(segment (start 144.145 57.785) (end 145.211701 56.718299) (width 0.1778) (layer B.Cu) (net 95))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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(segment (start 163.055301 92.087701) (end 177.282664 92.087701) (width 0.1778) (layer F.Cu) (net 96))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
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(segment (start 132.918299 79.1718) (end 132.511701 78.765202) (width 0.1778) (layer B.Cu) (net 96))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
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(segment (start 167.660209 61.798299) (end 161.721701 61.798299) (width 0.1778) (layer F.Cu) (net 97))
(segment (start 167.736409 61.722099) (end 167.660209 61.798299) (width 0.1778) (layer F.Cu) (net 97))
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(segment (start 126.365 61.595) (end 126.365 57.785) (width 0.1778) (layer B.Cu) (net 97))
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(segment (start 146.685 63.5) (end 146.685 57.785) (width 0.1778) (layer B.Cu) (net 98))
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(segment (start 155.371701 61.391701) (end 153.035 59.055) (width 0.1778) (layer F.Cu) (net 99))
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(segment (start 153.035 59.055) (end 150.495 56.515) (width 0.1778) (layer B.Cu) (net 99))
(segment (start 128.905 47.625) (end 126.365 45.085) (width 0.1778) (layer F.Cu) (net 99))
Optimize vias and tracks
2020-12-30 02:07:01 +00:00
(segment (start 140.1064 47.625) (end 140.716 47.625) (width 0.1778) (layer F.Cu) (net 99))
(segment (start 140.1064 47.625) (end 128.905 47.625) (width 0.1778) (layer F.Cu) (net 99))
(via (at 146.2278 49.6316) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 99))
(segment (start 140.716 47.625) (end 142.7226 49.6316) (width 0.1778) (layer F.Cu) (net 99))
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(segment (start 150.495 53.8988) (end 150.495 56.0578) (width 0.1778) (layer B.Cu) (net 99))
(segment (start 146.2278 49.6316) (end 150.495 53.8988) (width 0.1778) (layer B.Cu) (net 99))
(segment (start 150.495 56.515) (end 150.495 56.0578) (width 0.1778) (layer B.Cu) (net 99))
Update board to support 8 bit data and 16x firmware
2020-12-30 00:54:22 +00:00
(via (at 172.72 58.42) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 100))
(segment (start 168.7068 57.7088) (end 172.0088 57.7088) (width 0.1778) (layer F.Cu) (net 100))
(segment (start 172.0088 57.7088) (end 172.72 58.42) (width 0.1778) (layer F.Cu) (net 100))
(via (at 173.355 70.485) (size 0.762) (drill 0.50038) (layers F.Cu B.Cu) (net 100))
(segment (start 172.72 58.42) (end 173.355 59.055) (width 0.1778) (layer B.Cu) (net 100))
(segment (start 173.355 59.055) (end 173.355 70.485) (width 0.1778) (layer B.Cu) (net 100))
(segment (start 176.2506 70.485) (end 176.3268 70.4088) (width 0.1778) (layer F.Cu) (net 100))
(segment (start 173.355 70.485) (end 176.2506 70.485) (width 0.1778) (layer F.Cu) (net 100))
(segment (start 171.2468 62.7888) (end 168.7068 65.3288) (width 0.1778) (layer F.Cu) (net 101))
(segment (start 176.3268 62.7888) (end 171.2468 62.7888) (width 0.1778) (layer F.Cu) (net 101))
Add ground wires to EPROM address lines
2020-12-13 05:43:19 +00:00
)
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