Apple-2-HW
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Apple2-IO-RPi
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Merge pull request #2 from tjboldt/fullbyte 

Fullbyte
This commit is contained in:
Terence Boldt 2021-01-16 22:50:20 -05:00 committed by GitHub
parent bd41c31f06 7602dae70a
commit fde4bb712e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
26 changed files with 39088 additions and 27758 deletions
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74
Apple2/Firmware.asm
View File

@ -11,9 +11,10 @@ IOError = $27
NoDevice = $28
WriteProtect = $2B
SlotDrive = $50
InputByte = $c08e
OutputByte = $c08d
InputFlags = $c08b
OutputFlags = $c087
ReadBlockCommand = $01
WriteBlockCommand = $02
GetTimeCommand = $03
@ -50,15 +51,6 @@ Boot:
sta BufferHi
jsr Driver ;get the block
; lda #$00 ;block 1
; sta BlockLo
; sta BlockHi
; sta BufferLo ;buffer at $A00
; lda #$0A
; sta BufferHi
; jsr Driver ;get the block
; ldx #sdrive ;set up for slot n
jmp $801 ;execute the block
;;
@ -142,58 +134,40 @@ write256:
rts
SendByte:
pha
lsr
lsr
lsr
lsr
jsr SendNibble
pla
jsr SendNibble
rts
SendNibble:
and #$0F
ora #$70 ;Write bit low
pha
waitWrite:
lda InputByte,x
asl ;Second highest bit goes low when ready
bmi waitWrite
lda InputFlags,x
rol
rol
bcs waitWrite
pla
sta OutputByte,x
lda #$0e ; set bit 0 low to indicate write started
sta OutputFlags,x
finishWrite:
lda InputByte,x
asl
bpl finishWrite
lda #$FF
sta OutputByte,x
lda InputFlags,x
rol
rol
bcc finishWrite
lda #$0f
sta OutputFlags,x
rts
GetByte:
jsr GetNibble
asl
asl
asl
asl
sta NibbleStorage
jsr GetNibble
and #$0f
ora NibbleStorage
rts
GetNibble:
lda #$b0 ;set read flag low
sta OutputByte,x
lda #$0d ;set read flag low
sta OutputFlags,x
waitRead:
lda InputFlags,x
rol
bcs waitRead
lda InputByte,x
bmi waitRead
ora #$f0 ;set all flags high
sta OutputByte,x
pha
lda #$0f ;set all flags high
sta OutputFlags,x
finishRead:
lda InputByte,x
bpl finishRead
lda InputFlags,x
rol
bcc finishRead
pla
end:
rts

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Apple2/Firmware.bin
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Apple2/Firmware_27256_EPROM.bin Normal file
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6
Apple2/driver_assemble.sh
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@ -10,3 +10,9 @@ ca65 Firmware.asm -D STARTSLOT=\$c500 -o Slot5.o --listing Firmware5.lst
ca65 Firmware.asm -D STARTSLOT=\$c600 -o Slot6.o --listing Firmware6.lst
ca65 Firmware.asm -D STARTSLOT=\$c700 -o Slot7.o --listing Firmware7.lst
ld65 Slot0.o Slot1.o Slot2.o Slot3.o Slot4.o Slot5.o Slot6.o Slot7.o -o Firmware.bin -t none
cat \
Firmware.bin Firmware.bin Firmware.bin Firmware.bin \
Firmware.bin Firmware.bin Firmware.bin Firmware.bin \
Firmware.bin Firmware.bin Firmware.bin Firmware.bin \
Firmware.bin Firmware.bin Firmware.bin Firmware.bin \
> Firmware_27256_EPROM.bin

91
Hardware/Apple2.pretty/74LS00.kicad_mod Normal file
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@ -0,0 +1,91 @@
(module 74LS00 (layer F.Cu) (tedit 5FB69AA2)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(fp_text reference U2 (at 3.81 -2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS00 (at 3.875 7.75 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 7.62) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.55194 3.06832) (end 2.50444 3.06832) (layer F.SilkS) (width 0.12))
(fp_line (start 1.5494 3.08102) (end 1.5494 3.66776) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.03454 3.683) (end 1.5494 3.683) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.04724 4.35864) (end 2.062479 4.221481) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 2.52476 3.67538) (end 2.52476 3.0734) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.99898 11.72718) (end 1.51384 11.72718) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.01168 12.40282) (end 2.026919 12.265661) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 1.51638 11.1125) (end 2.46888 11.1125) (layer F.SilkS) (width 0.12))
(fp_line (start 2.4892 11.71956) (end 2.4892 11.11758) (layer F.SilkS) (width 0.12))
(fp_line (start 1.51384 11.1252) (end 1.51384 11.71194) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6769 6.4897) (end 5.19176 6.4897) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6896 7.16534) (end 5.704839 7.028181) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 5.1943 5.87502) (end 6.1468 5.87502) (layer F.SilkS) (width 0.12))
(fp_line (start 6.16712 6.48208) (end 6.16712 5.8801) (layer F.SilkS) (width 0.12))
(fp_line (start 5.19176 5.88772) (end 5.19176 6.47446) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6769 13.79982) (end 5.19176 13.79982) (angle -182.7927024) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.6896 14.47546) (end 5.704839 14.338301) (angle -338.1228359) (layer F.SilkS) (width 0.12))
(fp_line (start 5.1943 13.18514) (end 6.1468 13.18514) (layer F.SilkS) (width 0.12))
(fp_line (start 6.16712 13.7922) (end 6.16712 13.19022) (layer F.SilkS) (width 0.12))
(fp_line (start 5.19176 13.19784) (end 5.19176 13.78458) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 0) (end 2.286 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 0) (end 2.286 3.048) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 2.54) (end 1.905 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 1.905 2.54) (end 1.905 3.048) (layer F.SilkS) (width 0.12))
(fp_line (start 1.143 5.08) (end 2.032 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 5.08) (end 2.032 4.572) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 11.049) (end 2.286 7.62) (layer F.SilkS) (width 0.12))
(fp_line (start 2.286 7.62) (end 1.143 7.62) (layer F.SilkS) (width 0.12))
(fp_line (start 1.778 11.049) (end 1.778 10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 1.778 10.16) (end 1.143 10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 12.573) (end 2.032 12.954) (layer F.SilkS) (width 0.12))
(fp_line (start 2.032 12.954) (end 1.143 12.954) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 5.842) (end 5.461 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 2.54) (end 6.477 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 5.842) (end 5.842 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 5.08) (end 6.477 5.08) (layer F.SilkS) (width 0.12))
(fp_line (start 6.477 7.747) (end 5.715 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 5.715 7.747) (end 5.715 7.366) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 13.081) (end 5.461 10.287) (layer F.SilkS) (width 0.12))
(fp_line (start 5.461 10.287) (end 6.477 10.287) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 13.081) (end 5.842 12.7) (layer F.SilkS) (width 0.12))
(fp_line (start 5.842 12.7) (end 6.477 12.7) (layer F.SilkS) (width 0.12))
(fp_line (start 6.477 15.367) (end 5.715 15.367) (layer F.SilkS) (width 0.12))
(fp_line (start 5.715 15.367) (end 5.715 14.605) (layer F.SilkS) (width 0.12))
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

88
Hardware/Apple2.pretty/74LS32.kicad_mod Normal file
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@ -0,0 +1,88 @@
(module 74LS32 (layer F.Cu) (tedit 5FB6A63A)
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(fp_text reference U3 (at 3.81 -2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS32 (at 3.875 7.55 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_arc (start 2 2) (end 1.450001 2.774999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 2.775) (end 1.45 3.35) (layer F.SilkS) (width 0.12))
(fp_line (start 2.55 3.35) (end 2.55 2.8) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.55 3.35) (end 1.45 3.35) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.448537 3.320952) (end 2.548537 3.320952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.475 4.825) (end 4.925001 5.599999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_arc (start 6.025 6.175) (end 4.925 6.175) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_arc (start 4.923537 6.145952) (end 6.023537 6.145952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_line (start 6.025 6.175) (end 6.025 5.625) (layer F.SilkS) (width 0.12))
(fp_line (start 4.925 5.6) (end 4.925 6.175) (layer F.SilkS) (width 0.12))
(fp_line (start 1.175 2.375) (end 1.75 2.375) (layer F.SilkS) (width 0.12))
(fp_line (start 1.75 2.375) (end 1.75 2.925) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 2.875) (end 2.225 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 0) (end 1.175 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 4.275) (end 1.95 5.025) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 5.025) (end 1.175 5.025) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 7.15) (end 5.475 7.675) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 7.675) (end 6.425 7.675) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 5.1) (end 5.725 5.1) (layer F.SilkS) (width 0.12))
(fp_line (start 5.725 5.1) (end 5.725 5.75) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 2.55) (end 5.25 2.55) (layer F.SilkS) (width 0.12))
(fp_line (start 5.25 2.55) (end 5.25 5.7) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 12.772) (end 1.175 12.772) (layer F.SilkS) (width 0.12))
(fp_line (start 1.95 12.022) (end 1.95 12.772) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 7.747) (end 1.175 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 2.225 10.622) (end 2.225 7.747) (layer F.SilkS) (width 0.12))
(fp_line (start 1.75 10.122) (end 1.75 10.672) (layer F.SilkS) (width 0.12))
(fp_line (start 1.175 10.122) (end 1.75 10.122) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.448537 11.067952) (end 2.548537 11.067952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.55 11.097) (end 1.45 11.097) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(fp_line (start 2.55 11.097) (end 2.55 10.547) (layer F.SilkS) (width 0.12))
(fp_line (start 1.45 10.522) (end 1.45 11.097) (layer F.SilkS) (width 0.12))
(fp_arc (start 2 9.747) (end 1.450001 10.521999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_arc (start 5.475 12.445) (end 4.925001 13.219999) (angle -69.47693483) (layer F.SilkS) (width 0.12))
(fp_line (start 4.925 13.22) (end 4.925 13.795) (layer F.SilkS) (width 0.12))
(fp_line (start 6.025 13.795) (end 6.025 13.245) (layer F.SilkS) (width 0.12))
(fp_arc (start 4.923537 13.765952) (end 6.023537 13.765952) (angle 62.8786966) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 10.17) (end 5.25 10.17) (layer F.SilkS) (width 0.12))
(fp_line (start 5.725 12.72) (end 5.725 13.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.45 12.72) (end 5.725 12.72) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 15.295) (end 6.425 15.295) (layer F.SilkS) (width 0.12))
(fp_line (start 5.475 14.77) (end 5.475 15.295) (layer F.SilkS) (width 0.12))
(fp_line (start 5.25 10.17) (end 5.25 13.32) (layer F.SilkS) (width 0.12))
(fp_arc (start 6.025 13.795) (end 4.925 13.795) (angle -58.13402231) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

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Hardware/Apple2.pretty/Apple2IORPi_PCB.jpg
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34
Hardware/Apple2.pretty/Capacitor.kicad_mod Normal file
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@ -0,0 +1,34 @@
(module Capacitor (layer F.Cu) (tedit 5FEB5EFB)
(descr "C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor")
(fp_text reference C1 (at 1.25 2.54) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value C (at 1.25 2.55) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 1.25 0) (layer F.Fab)
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40
Hardware/Apple2IORPi-Edge.Cuts.gbr
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T4
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X4.45Y-3.86
X4.45Y-3.96
T0
M30

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(export (version D)
(design
(source C:\Users\teren\Apple2-IO-RPi\Hardware\Apple2IORPi.sch)
(date "2020-12-13 22:02:29")
(date "2020-12-29 08:57:49")
(tool "Eeschema (5.0.2)-1")
(sheet (number 1) (name /) (tstamps /)
(title_block
(title "Apple II I/O RPi")
(company "Terence J. Boldt")
(rev 0.6)
(date 2020-12-13)
(rev 0.9)
(date 2020-12-29)
(source Apple2IORPi.sch)
(comment (number 1) (value "Initial draft desgn"))
(comment (number 1) (value "Third Prototype"))
(comment (number 2) (value "Provides storage and network for the Apple ]["))
(comment (number 3) (value "Raspberry Pi Zero W as a daughter board"))
(comment (number 4) (value "Expansion card for Apple ][ computers")))))
@ -112,7 +112,46 @@
(datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/doc0014.pdf)
(libsource (lib Memory_EPROM) (part 27C256) (description "OTP EPROM 256 KiBit"))
(sheetpath (names /) (tstamps /))
(tstamp 5FD87325)))
(tstamp 5FD87325))
(comp (ref U6)
(value 74LVC245)
(datasheet http://www.ti.com/lit/gpn/sn74LS245)
(libsource (lib 74xx) (part 74LS245) (description "Octal BUS Transceivers, 3-State outputs"))
(sheetpath (names /) (tstamps /))
(tstamp 5FED6949))
(comp (ref U7)
(value 74LVC374)
(datasheet http://www.ti.com/lit/gpn/sn74LS374)
(libsource (lib 74xx) (part 74LS374) (description "8-bit Register, 3-state outputs"))
(sheetpath (names /) (tstamps /))
(tstamp 5FED6A94))
(comp (ref C8)
(value C)
(footprint Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm)
(datasheet ~)
(libsource (lib Device) (part C) (description "Unpolarized capacitor"))
(sheetpath (names /) (tstamps /))
(tstamp 60A58951))
(comp (ref C7)
(value C)
(footprint Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm)
(datasheet ~)
(libsource (lib Device) (part C) (description "Unpolarized capacitor"))
(sheetpath (names /) (tstamps /))
(tstamp 60A87587))
(comp (ref U8)
(value 74LS32)
(datasheet http://www.ti.com/lit/gpn/sn74LS32)
(libsource (lib 74xx) (part 74LS32) (description "Quad 2-input OR"))
(sheetpath (names /) (tstamps /))
(tstamp 60BA60C0))
(comp (ref C9)
(value C)
(footprint Capacitor_THT:C_Disc_D3.8mm_W2.6mm_P2.50mm)
(datasheet ~)
(libsource (lib Device) (part C) (description "Unpolarized capacitor"))
(sheetpath (names /) (tstamps /))
(tstamp 60C3A67B)))
(libparts
(libpart (lib 74xx) (part 74LS00)
(aliases
@ -398,314 +437,382 @@
(library (logical Memory_EPROM)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library/Memory_EPROM.lib")))
(nets
(net (code 1) (name "Net-(U2-Pad8)")
(node (ref U2) (pin 8))
(node (ref U3) (pin 12)))
(net (code 2) (name "Net-(U3-Pad10)")
(node (ref U3) (pin 11))
(node (ref U3) (pin 10)))
(net (code 3) (name "Net-(U3-Pad1)")
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(net (code 69) (name "Net-(J0-Pad9)")
(node (ref U1) (pin 3))
(node (ref J0) (pin 9)))
(net (code 70) (name "Net-(U0-Pad1)")
(node (ref U8) (pin 9))
(node (ref U3) (pin 4))
(node (ref U2) (pin 9))
(node (ref U0) (pin 1))
(node (ref U2) (pin 10))
(node (ref U2) (pin 11)))
(net (code 71) (name "Net-(J0-Pad21)")
(node (ref J0) (pin 21)))
(net (code 72) (name "Net-(J0-Pad10)")
(node (ref U1) (pin 25))
(node (ref J0) (pin 10)))
(net (code 73) (name "Net-(J0-Pad11)")
(node (ref J0) (pin 11))
(node (ref U1) (pin 24)))
(net (code 74) (name "Net-(J0-Pad12)")
(node (ref U1) (pin 21))
(node (ref J0) (pin 12)))
(net (code 75) (name "Net-(J0-Pad13)")
(node (ref J0) (pin 13)))
(net (code 76) (name "Net-(J0-Pad14)")
(node (ref J0) (pin 14)))
(net (code 77) (name "Net-(J0-Pad15)")
(node (ref J0) (pin 15)))
(net (code 78) (name "Net-(J0-Pad16)")
(node (ref J0) (pin 16)))
(net (code 79) (name "Net-(J0-Pad17)")
(node (ref J0) (pin 17)))
(net (code 80) (name "Net-(J0-Pad19)")
(node (ref J0) (pin 19)))
(net (code 81) (name "Net-(J0-Pad20)")
(node (ref J0) (pin 20)))
(net (code 82) (name "Net-(J0-Pad22)")
(node (ref J0) (pin 22)))
(net (code 83) (name "Net-(J0-Pad24)")
(node (ref J0) (pin 24))
(node (ref J0) (pin 27)))
(net (code 84) (name "Net-(J0-Pad23)")
(node (ref J0) (pin 23))
(node (ref J0) (pin 28)))
(net (code 85) (name "Net-(J0-Pad29)")
(node (ref J0) (pin 29)))
(net (code 86) (name "Net-(J0-Pad30)")
(node (ref J0) (pin 30)))
(net (code 87) (name "Net-(J0-Pad31)")
(node (ref J0) (pin 31)))
(net (code 88) (name "Net-(J0-Pad32)")
(node (ref J0) (pin 32)))
(net (code 89) (name "Net-(U3-Pad3)")
(node (ref U3) (pin 3))
(node (ref U4) (pin 19)))
(net (code 90) (name "Net-(J1-Pad13)")
(node (ref J1) (pin 13))
(node (ref U4) (pin 16)))
(net (code 91) (name "Net-(J1-Pad15)")
(node (ref J1) (pin 15))
(node (ref U4) (pin 15)))
(net (code 92) (name "Net-(J1-Pad19)")
(node (ref J1) (pin 19))
(node (ref U4) (pin 14)))
(net (code 93) (name "Net-(C1-Pad2)")
(node (ref C6) (pin 2))
(node (ref U5) (pin 10))
(node (ref U6) (pin 1))
(node (ref U6) (pin 10))
(node (ref J1) (pin 30))
(node (ref U2) (pin 7))
(node (ref U3) (pin 7))
(node (ref U7) (pin 10))
(node (ref U5) (pin 1))
(node (ref U7) (pin 1))
(node (ref J1) (pin 9))
(node (ref C8) (pin 2))
(node (ref J1) (pin 25))
(node (ref J1) (pin 14))
(node (ref J1) (pin 20))
(node (ref U4) (pin 1))
(node (ref U4) (pin 10))
(node (ref U8) (pin 7))
(node (ref C9) (pin 2))
(node (ref C7) (pin 2))
(node (ref U0) (pin 10))
(node (ref J0) (pin 26))
(node (ref J1) (pin 6))
(node (ref C3) (pin 2))
(node (ref J1) (pin 39))
(node (ref C4) (pin 2))
(node (ref U1) (pin 14))
(node (ref C2) (pin 2))
(node (ref J1) (pin 34))
(node (ref C1) (pin 2))
(node (ref C5) (pin 2)))
(net (code 94) (name "Net-(J0-Pad3)")
(node (ref U1) (pin 9))
(node (ref J0) (pin 3))
(node (ref U3) (pin 13)))
(net (code 95) (name "Net-(U3-Pad10)")
(node (ref U3) (pin 10))
(node (ref U3) (pin 11)))
(net (code 96) (name "Net-(U2-Pad3)")
(node (ref U2) (pin 5))
(node (ref U2) (pin 4))
(node (ref U2) (pin 3)))
(net (code 97) (name "Net-(U0-Pad19)")
(node (ref U2) (pin 6))
(node (ref U0) (pin 19)))
(net (code 99) (name "Net-(U3-Pad1)")
(node (ref U3) (pin 6))
(node (ref U3) (pin 1)))
(net (code 100) (name "Net-(J0-Pad41)")
(node (ref U8) (pin 1))
(node (ref U8) (pin 4))
(node (ref J0) (pin 41))
(node (ref U3) (pin 2))
(node (ref U3) (pin 9))
(node (ref U2) (pin 1)))
(net (code 101) (name "Net-(J0-Pad18)")
(node (ref U2) (pin 12))
(node (ref J0) (pin 18))
(node (ref U2) (pin 13)))
(net (code 102) (name "Net-(J0-Pad1)")
(node (ref U2) (pin 2))
(node (ref J0) (pin 1))
(node (ref U1) (pin 22))
(node (ref U1) (pin 20)))))

BIN
Hardware/Apple2IORPi.pdf
View File

Binary file not shown.

2
Hardware/Apple2IORPi.pro
View File

@ -1,4 +1,4 @@
update=2021-01-08 14:20:49
update=2021-01-08 22:14:24
version=1
last_client=kicad
[general]

1590
Hardware/Apple2IORPi.sch
View File

File diff suppressed because it is too large Load Diff

6
Hardware/fp-lib-table
View File

@ -1,3 +1,3 @@
(fp_lib_table
(lib (name Apple2)(type KiCad)(uri /home/terence/source/Apple2-IO-RPi/Hardware/Apple2.pretty)(options "")(descr ""))
)
(fp_lib_table
(lib (name Apple2)(type KiCad)(uri C:/Users/teren/Apple2-IO-RPi/Hardware/Apple2.pretty)(options "")(descr ""))
)

22
README.md
View File

@ -7,17 +7,21 @@ Apple II expansion card using a Raspberry Pi for I/O
The purpose of this project is to provide I/O for an Apple II series 8 bit computer via a Raspberry Pi Zero W which is powered by the Apple II expansion bus. Initially this is storage via virtual ProDOS compatible drive. Next might be adding virtual serial card support over wifi. Future enhancements could use the RPi for more complex processing as per request from the Apple II. For example, the Apple II could request a web page or application and the RPi could calculate this in Apple II hi-res graphics mode and send the image data back to the II for display purposes.
## Project Status
This is an early stage project. Currently one board has been assembled and tested. It is now possible for the Apple II to boot from and write to a virutal hard drive image stored on the RPi in any slot. The code has no error handling or tests yet and is incomplete.
This is an early stage project. Currently three prototype revisions been assembled and tested. It is now possible for the Apple II to boot from and write to a virutal hard drive image stored on the RPi in any slot and execute simple commands on the RPi via an Apple II application. The code has no error handling or tests yet and is incomplete.
## Roadmap
1. DONE - Build initial prototype that reads/writes virtual hard drive
2. DONE - Create firmware to make the card a bootable device
3. DONE - Fix board with updated second prototype PCB
4. WORKING - Add ProDOS clock driver (real driver later, for now just directly sets values)
5. WORKING - Add RPi terminal access (does not keep context between commands yet)
6. Add web service call support
7. Proxy VNC connection, rendering as Apple II compatible graphics
8. Create new schematic/PCB with faster data transfer
4. DONE - Add ProDOS clock support
5. WORKING - Add simple RPi command execution (does not keep context between commands yet)
6. DONE - Create new schematic/PCB with faster data transfer
7. Add proper ProDOS clock driver (currently just directly sets values on block reads)
8. Add directory context to RPi command execution
9. Add full terminal emulation
10. Add support for direct file read/write without drive image
11. Add web service call support
12. Proxy VNC connection, rendering as Apple II compatible graphics
## Setup
1. Have PCBs made from the gerber and drill files in the Hardware folder
@ -29,12 +33,12 @@ This is an early stage project. Currently one board has been assembled and teste
7. Put microSD card in the RPi
8. Install the expansion card into the Apple II
9. Power on the Apple II
10. Install Go on the RPi over ssh
10. Install Git and Go on the RPi over ssh
11. go build Driver.go
12. Copy a ProDOS hard drive image onto the RPi
13. ./Driver HARDDRIVE.hdv
14. Setup the Driver as a service or to autostart via cronjob
## Similar Project
If you're looking for complete hardware design or prefer having Apple II peripherals control a control a Raspberry Pi rather than simply using the Raspberry Pi to provide storage and network access to the Apple II, have a look at David Schmenk's excellent [Apple2Pi](https://github.com/dschmenk/apple2pi) project.
If you prefer having Apple II peripherals control a Raspberry Pi rather than simply using the Raspberry Pi to provide storage, network access and processing to the Apple II, have a look at David Schmenk's excellent [Apple2Pi](https://github.com/dschmenk/apple2pi) project.

167
RaspberryPi/Driver.go
View File

@ -17,16 +17,24 @@ var edgeTimeout time.Duration
var out_write gpio.PinIO
var out_read gpio.PinIO
var out_commandWrite gpio.PinIO
var out_commandRead gpio.PinIO
var out_reserved2 gpio.PinIO
var out_reserved1 gpio.PinIO
var out_bit7 gpio.PinIO
var out_bit6 gpio.PinIO
var out_bit5 gpio.PinIO
var out_bit4 gpio.PinIO
var out_bit3 gpio.PinIO
var out_bit2 gpio.PinIO
var out_bit1 gpio.PinIO
var out_bit0 gpio.PinIO
var in_write gpio.PinIO
var in_read gpio.PinIO
var in_commandWrite gpio.PinIO
var in_commandRead gpio.PinIO
var in_reserved2 gpio.PinIO
var in_reserved1 gpio.PinIO
var in_bit7 gpio.PinIO
var in_bit6 gpio.PinIO
var in_bit5 gpio.PinIO
var in_bit4 gpio.PinIO
var in_bit3 gpio.PinIO
var in_bit2 gpio.PinIO
var in_bit1 gpio.PinIO
@ -95,7 +103,12 @@ func handleReadBlockCommand(file *os.File) {
file.ReadAt(buffer, int64(block)*512)
//dumpBlock(buffer)
readBlock(buffer)
err := readBlock(buffer)
if err == nil {
fmt.Printf("Read block completed\n")
} else {
fmt.Printf("Failed to read block\n")
}
}
func handleWriteBlockCommand(file *os.File) {
@ -111,6 +124,7 @@ func handleWriteBlockCommand(file *os.File) {
writeBlock(buffer)
file.WriteAt(buffer, int64(block)*512)
file.Sync()
fmt.Printf("Write block completed\n")
}
func handleExecCommand() {
@ -134,6 +148,7 @@ func handleExecCommand() {
}
func handleGetTimeCommand() {
fmt.Printf("Sending date/time...\n")
/* 49041 ($BF91) 49040 ($BF90)
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
@ -165,6 +180,7 @@ func handleGetTimeCommand() {
writeByte(bf91)
writeByte(bf92)
writeByte(bf93)
fmt.Printf("Send time complete\n")
}
func readBlock(buffer []byte) error {
@ -191,18 +207,26 @@ func writeBlock(buffer []byte) error {
}
func initGpio() {
out_write = gpioreg.ByName("GPIO5")
out_read = gpioreg.ByName("GPIO11")
out_commandWrite = gpioreg.ByName("GPIO9")
out_commandRead = gpioreg.ByName("GPIO10")
out_write = gpioreg.ByName("GPIO24")
out_read = gpioreg.ByName("GPIO25")
out_reserved2 = gpioreg.ByName("GPIO7") //note GPIO7 and CPIO8 require extra effort to use
out_reserved1 = gpioreg.ByName("GPIO8")
out_bit7 = gpioreg.ByName("GPIO5")
out_bit6 = gpioreg.ByName("GPIO11")
out_bit5 = gpioreg.ByName("GPIO9")
out_bit4 = gpioreg.ByName("GPIO10")
out_bit3 = gpioreg.ByName("GPIO22")
out_bit2 = gpioreg.ByName("GPIO27")
out_bit1 = gpioreg.ByName("GPIO17")
out_bit0 = gpioreg.ByName("GPIO4")
in_write = gpioreg.ByName("GPIO12")
in_read = gpioreg.ByName("GPIO16")
in_commandWrite = gpioreg.ByName("GPIO20")
in_commandRead = gpioreg.ByName("GPIO21")
in_write = gpioreg.ByName("GPIO23")
in_read = gpioreg.ByName("GPIO18")
in_reserved2 = gpioreg.ByName("GPIO14")
in_reserved1 = gpioreg.ByName("GPIO15")
in_bit7 = gpioreg.ByName("GPIO12")
in_bit6 = gpioreg.ByName("GPIO16")
in_bit5 = gpioreg.ByName("GPIO20")
in_bit4 = gpioreg.ByName("GPIO21")
in_bit3 = gpioreg.ByName("GPIO26")
in_bit2 = gpioreg.ByName("GPIO19")
in_bit1 = gpioreg.ByName("GPIO13")
@ -210,6 +234,18 @@ func initGpio() {
in_write.In(gpio.PullDown, gpio.BothEdges)
in_read.In(gpio.PullDown, gpio.BothEdges)
out_reserved1.Out(gpio.High)
out_reserved2.Out(gpio.High)
out_read.Out(gpio.High)
out_write.Out(gpio.High)
out_bit7.Out(gpio.Low)
out_bit6.Out(gpio.Low)
out_bit5.Out(gpio.Low)
out_bit4.Out(gpio.Low)
out_bit3.Out(gpio.Low)
out_bit2.Out(gpio.Low)
out_bit1.Out(gpio.Low)
out_bit0.Out(gpio.Low)
edgeTimeout = time.Second * 5
}
@ -247,36 +283,8 @@ func writeString(outString string) error {
return nil
}
func readByte() (byte, error) {
data, err := readNibble()
data = data << byte(4)
if err != nil {
return 0, err
}
highNibble, err := readNibble()
if err != nil {
return 0, err
}
data += highNibble
//fmt.Printf("R%02X ", data)
return data, nil
}
func writeByte(data byte) error {
//fmt.Printf("W%02X ", data)
err := writeNibble(data >> 4)
if err != nil {
return err
}
err = writeNibble(data & 15)
if err != nil {
return err
}
return nil
}
func readNibble() (byte, error) {
// let the Apple II know we are ready to read
if debug {
fmt.Printf("let the Apple II know we are ready to read\n")
@ -290,34 +298,50 @@ func readNibble() (byte, error) {
for in_write.Read() == gpio.High {
if !in_write.WaitForEdge(edgeTimeout) {
if debug {
fmt.Printf("Timed out reading nibble -- write stuck high\n")
fmt.Printf("Timed out reading byte -- write stuck high\n")
}
return 0, errors.New("Timed out reading nibble -- write stuck high\n")
return 0, errors.New("Timed out reading byte -- write stuck high\n")
}
}
// get a nibble of data
if debug {
fmt.Printf("get a nibble of data\n")
fmt.Printf("get a byte of data\n")
}
var nibble byte
nibble = 0
var data byte
data = 0
bit7 := in_bit7.Read()
bit6 := in_bit6.Read()
bit5 := in_bit5.Read()
bit4 := in_bit4.Read()
bit3 := in_bit3.Read()
bit2 := in_bit2.Read()
bit1 := in_bit1.Read()
bit0 := in_bit0.Read()
if bit7 == gpio.High {
data += 128
}
if bit6 == gpio.High {
data += 64
}
if bit5 == gpio.High {
data += 32
}
if bit4 == gpio.High {
data += 16
}
if bit3 == gpio.High {
nibble += 8
data += 8
}
if bit2 == gpio.High {
nibble += 4
data += 4
}
if bit1 == gpio.High {
nibble += 2
data += 2
}
if bit0 == gpio.High {
nibble += 1
data += 1
}
// let the Apple II know we are done reading
@ -329,16 +353,16 @@ func readNibble() (byte, error) {
for in_write.Read() == gpio.Low {
if !in_write.WaitForEdge(edgeTimeout) {
if debug {
fmt.Printf("Timed out reading nibble -- write stuck low\n")
fmt.Printf("Timed out reading byte -- write stuck low\n")
}
return 0, errors.New("Timed out reading nibble -- write stuck low")
return 0, errors.New("Timed out reading byte -- write stuck low")
}
}
return nibble, nil
return data, nil
}
func writeNibble(data byte) error {
func writeByte(data byte) error {
// wait for the Apple II to be ready to read
if debug {
fmt.Printf("wait for the Apple II to be ready to read\n")
@ -346,16 +370,41 @@ func writeNibble(data byte) error {
for in_read.Read() == gpio.High {
if !in_read.WaitForEdge(edgeTimeout) {
if debug {
fmt.Printf("Timed out writing nibble -- read stuck high\n")
fmt.Printf("Timed out writing byte -- read stuck high\n")
}
return errors.New("Timed out writing nibble -- read stuck high")
return errors.New("Timed out writing byte -- read stuck high")
}
}
bit7 := gpio.Low
bit6 := gpio.Low
bit5 := gpio.Low
bit4 := gpio.Low
bit3 := gpio.Low
bit2 := gpio.Low
bit1 := gpio.Low
bit0 := gpio.Low
if ((data & 128) >> 7) == 1 {
bit7 = gpio.High
}
out_bit7.Out(bit7)
if ((data & 64) >> 6) == 1 {
bit6 = gpio.High
}
out_bit6.Out(bit6)
if ((data & 32) >> 5) == 1 {
bit5 = gpio.High
}
out_bit5.Out(bit5)
if ((data & 16) >> 4) == 1 {
bit4 = gpio.High
}
out_bit4.Out(bit4)
if ((data & 8) >> 3) == 1 {
bit3 = gpio.High
}
@ -387,9 +436,9 @@ func writeNibble(data byte) error {
for in_read.Read() == gpio.Low {
if !in_read.WaitForEdge(edgeTimeout) {
if debug {
fmt.Printf("Timed out writing nibble -- read stuck low\n")
fmt.Printf("Timed out writing byte -- read stuck low\n")
}
return errors.New("Timed out writing nibble -- read stuck low")
return errors.New("Timed out writing byte -- read stuck low")
}
}