mirror of
https://github.com/tjboldt/Apple2-IO-RPi.git
synced 2024-06-11 23:29:33 +00:00
55c1cb180d
The implemenation is based on a Raspberry Pi Pico - see https://github.com/a2retrosystems/A2retroNET The new hardware type has a simple UART-type interface. Beside the two data registers, there are only the two bits to indicate readability and writability of the data registers.
207 lines
6.0 KiB
Plaintext
207 lines
6.0 KiB
Plaintext
///////////////////////////////////////////////////////////////////////////////
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/*
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MIT License
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Copyright (c) 2022 Oliver Schmidt (https://a2retro.de/)
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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*/
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///////////////////////////////////////////////////////////////////////////////
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.define public gpio_addr 2 // 12 pins
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.define public gpio_rw 14
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.define public gpio_data 15 // 8 pins
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.define public gpio_led 25
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.define public gpio_enbl 26 // DEVSEL | IOSEL | IOSTRB
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.define public gpio_irq 27
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.define public gpio_rdy 28
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.define public size_addr 13 // incl. R/W
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.define public size_data 8
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.define public sm_enbl 0
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.define public sm_read 1 // from Apple II perspective
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.define public sm_write 2 // from Apple II perspective
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.define irq_write 4
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/*
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Implementation of the Apple II peripheral bus protocol:
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- /DEVSEL, /IOSEL and /IOSTRB are supposed to combined to ENBL via an AND gate.
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- On the falling edge of ENBL, the lines A0-A11 and R/W are sampled and pushed
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into the 'enable' state machine RX FIFO.
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- In case of an Apple II write cycle, the lines D0-D7 are sampled ~300ns later
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and pushed into the 'write' state machine RX FIFO.
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- If a byte is pushed into the 'read' state machine TX FIFO, it is driven out
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to the lines D0-D7 until the rising edge of ENBL.
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*/
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///////////////////////////////////////////////////////////////////////////////
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.program enbl
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.wrap_target
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idle:
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wait 1 gpio gpio_enbl // wait for ENBL to rise
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wait 0 gpio gpio_enbl // wait for ENBL to fall
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in pins, size_addr // shift A0-A11 + R/W into ISR
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jmp pin idle // jump to idle if R/W is high
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irq irq_write // Set 'write' IRQ
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.wrap
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% c-sdk {
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static inline void enbl_program_init(uint offset) {
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pio_sm_config c = enbl_program_get_default_config(offset);
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// in_base: gpio_addr
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sm_config_set_in_pins(&c, gpio_addr);
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// shift_right: false
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// autopush: true
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// push_threshold: size_addr
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sm_config_set_in_shift(&c, false, true, size_addr);
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// pin: gpio_rw
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sm_config_set_jmp_pin(&c, gpio_rw);
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// state_machine: sm_enbl
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// initial_pc: offset
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pio_sm_init(pio0, sm_enbl, offset, &c);
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// state_machine: sm_enbl
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pio_sm_set_enabled(pio0, sm_enbl, true);
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}
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%}
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///////////////////////////////////////////////////////////////////////////////
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.program write
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.wrap_target
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wait 1 irq irq_write [31] // wait for 'write' IRQ to be set and clear it
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// [31 cycles to allow 6502 to set up D0-D7]
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in pins, size_data // shift D0-D7 into ISR
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.wrap
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% c-sdk {
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static inline void write_program_init(uint offset) {
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pio_sm_config c = write_program_get_default_config(offset);
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// in_base: gpio_data
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sm_config_set_in_pins(&c, gpio_data);
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// shift_right: false
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// autopush: true
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// push_threshold: size_data
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sm_config_set_in_shift(&c, false, true, size_data);
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// state_machine: sm_write
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// initial_pc: offset
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pio_sm_init(pio0, sm_write, offset, &c);
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// state_machine: sm_write
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pio_sm_set_enabled(pio0, sm_write, true);
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}
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%}
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///////////////////////////////////////////////////////////////////////////////
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.program read
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/*
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Both set and set-side are limited to 5 pins each. So both set and side-set are
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configured to set (the direction of) 4 pins. This approach allows to set the
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direction of D0-D7 in one operation.
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Note: The naive approach would have been
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mov osr, ~x // move 0xFFFFFFFF to OSR
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out pindirs, size_data // enable output of D0-D7
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[...]
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mov osr, x // move 0x00000000 to OSR
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out pindirs, size_data // disable output of D0-D7
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but this would have required two operations and destroyed OSR.
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*/
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.side_set (size_data / 2) opt pindirs
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.wrap_target
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pull block // pull data into OSR, block on empty FIFO
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out pins, size_data // shift OSR out to D0-D7
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set pindirs, 15 side 15 // enable output of D0-D7
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wait 1 gpio gpio_enbl // wait for ENBL to rise
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set pindirs, 0 side 0 // disable output of D0-D7
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.wrap
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% c-sdk {
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static inline void read_program_init(uint offset) {
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pio_sm_config c = read_program_get_default_config(offset);
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// out_base: gpio_data
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// out_count: size_data
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sm_config_set_out_pins(&c, gpio_data, size_data);
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// shift_right: true
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// autopull: false
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// pull_threshold: size_data
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sm_config_set_out_shift(&c, true, false, size_data);
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// set_base: gpio_data
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// set_count: size_data / 2
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sm_config_set_set_pins(&c, gpio_data, size_data / 2);
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// sideset_base: gpio_data + size_data / 2
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sm_config_set_sideset_pins(&c, gpio_data + size_data / 2);
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// state_machine: sm_read
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// initial_pc: offset
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pio_sm_init(pio0, sm_read, offset, &c);
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// state_machine: sm_read
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pio_sm_set_enabled(pio0, sm_read, true);
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}
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%}
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///////////////////////////////////////////////////////////////////////////////
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