50 lines
1.1 KiB
VHDL
50 lines
1.1 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use work.ps2_components.all;
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entity mouseTop is
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port(
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mclk : in STD_LOGIC;
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PS2C : inout STD_LOGIC;
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PS2D : inout STD_LOGIC;
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btn : in STD_LOGIC_VECTOR(3 downto 0);
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ld : out STD_LOGIC_VECTOR(3 downto 0);
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aToG : out STD_LOGIC_VECTOR(6 downto 0);
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dp : out STD_LOGIC;
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an : out STD_LOGIC_VECTOR(3 downto 0)
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);
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end mouseTop;
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architecture mouseTop of mouseTop is
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signal clk7m, clk190, clr: STD_LOGIC;
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signal byte3: STD_LOGIC_VECTOR(7 downto 0);
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signal xData, yData: STD_LOGIC_VECTOR(8 downto 0);
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signal xMouse: STD_LOGIC_VECTOR(15 downto 0);
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begin
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clr <= btn(3);
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dp <= '1'; -- decimal points off
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xMouse <= xData(7 downto 0) & yData(7 downto 0);
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ld(0) <= yData(8);
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ld(1) <= xData(8);
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ld(2) <= byte3(1); -- right button
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ld(3) <= byte3(0); -- left button
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U1 : clkdiv2
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port map(mclk => mclk, clr => clr, clk7m => clk7m, clk190 => clk190);
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U2 : mouseCtrl
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port map(clk7m => clk7m, clr => clr, sel => btn(0),
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PS2C => PS2C, PS2D => PS2D, byte3 => byte3,
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xData => xData, yData => yData);
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U3 : x7segb
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port map(x => xMouse, cclk => clk190, clr => clr,
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aToG => aToG, an => an);
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end mouseTop;
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