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AppleIISd
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Program enable added and verified

This commit is contained in:
Florian Reitz 2019-02-14 23:58:48 +01:00
parent 91d54ddd9c
commit 02d9e608e1
5 changed files with 474 additions and 447 deletions
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6
VHDL/AddressDecoder.vhd
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@ -39,7 +39,8 @@ entity AddressDecoder is
NIO_SEL : in std_logic; -- $Cs00 - $CsFF, EEPROM bank 0
NIO_STB : in std_logic; -- $C800 - $CFFF, EEPROM banks 1 to 7
NRESET : in std_logic;
DATA_EN : out std_logic; -- to CPLD
DATA_EN : out std_logic; -- to CPLD
PGM_EN : in std_logic; -- from CPLD;
NG : out std_logic; -- to bus transceiver
NOE : out std_logic; -- to EEPROM
NWE : out std_logic); -- to EEPROM
@ -84,7 +85,8 @@ begin
NWE <= RNW
or (not NIO_SEL and not NIO_STB)
or (NIO_SEL and NIO_STB)
or (NIO_SEL and ncs);
or (NIO_SEL and ncs)
or not PGM_EN;
cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;

25
VHDL/AddressDecoder_Test.vhd
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@ -50,7 +50,8 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
NIO_SEL : IN std_logic;
NIO_STB : IN std_logic;
NRESET : IN std_logic;
DATA_EN : OUT std_logic;
DATA_EN : OUT std_logic;
PGM_EN : IN std_logic;
NG : OUT std_logic;
NOE : OUT std_logic;
NWE : OUT std_logic
@ -66,7 +67,8 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
signal NIO_STB : std_logic := '1';
signal NRESET : std_logic := '1';
signal CLK : std_logic := '0';
signal PHI0 : std_logic := '1';
signal PHI0 : std_logic := '1';
signal PGM_EN : std_logic := '1';
--Outputs
signal B : std_logic_vector(10 downto 8);
@ -91,7 +93,8 @@ BEGIN
NIO_SEL => NIO_SEL,
NIO_STB => NIO_STB,
NRESET => NRESET,
DATA_EN => DATA_EN,
DATA_EN => DATA_EN,
PGM_EN => PGM_EN,
NG => NG,
NOE => NOE,
NWE => NWE
@ -173,13 +176,27 @@ BEGIN
NIO_SEL <= '0';
wait until falling_edge(PHI0);
NIO_SEL <= '1';
wait until rising_edge(PHI0);
-- CnXX access, write, select, no PGM_EN
-- NG must be '0'
-- NOE must be '1'
-- NWE must be '1'
RNW <= '0';
PGM_EN <= '0';
A <= "0100"; -- must become "000"
wait until rising_edge(PHI0);
NIO_SEL <= '0';
wait until falling_edge(PHI0);
NIO_SEL <= '1';
wait until rising_edge(PHI0);
-- C8xx access, selected
-- NG must be '0'
-- NOE must be '0'
-- NWE must be '1'
RNW <= '1';
RNW <= '1';
PGM_EN <= '1';
A <= "1000"; -- must become "001"
wait until rising_edge(PHI0);
NIO_STB <= '0';

860
VHDL/AppleIISd.jed
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File diff suppressed because it is too large Load Diff

9
VHDL/AppleIISd.vhd
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@ -70,6 +70,7 @@ architecture Behavioral of AppleIISd is
signal addr_low_int : std_logic_vector (1 downto 0);
signal data_en : std_logic;
signal pgm_en : std_logic;
component SpiController is
Port (
@ -87,7 +88,8 @@ Port (
nsel : out std_logic;
wp : in std_logic;
card : in std_logic;
led : out std_logic
led : out std_logic;
pgm_en : out std_logic
);
end component;
@ -103,6 +105,7 @@ Port (
NIO_STB : in std_logic;
NRESET : in std_logic;
DATA_EN : out std_logic;
PGM_EN : in std_logic;
NG : out std_logic;
NOE : out std_logic;
NWE : out std_logic
@ -126,7 +129,8 @@ begin
nsel => NSEL,
wp => WP,
card => CARD,
led => LED
led => LED,
pgm_en => pgm_en
);
addDec: AddressDecoder port map(
@ -140,6 +144,7 @@ begin
NIO_STB => NIO_STB,
NRESET => NRESET,
DATA_EN => data_en,
PGM_EN => pgm_en,
NOE => NOE,
NWE => NWE,
NG => NG

21
VHDL/SpiController.vhd
View File

@ -24,7 +24,8 @@ Port (
sclk : out STD_LOGIC;
nsel : out STD_LOGIC;
wp : in STD_LOGIC;
card : in STD_LOGIC;
card : in STD_LOGIC;
pgm_en : out STD_LOGIC;
led : out STD_LOGIC
);
@ -39,7 +40,8 @@ architecture Behavioral of SpiController is
signal spidatain: std_logic_vector (7 downto 0);
signal spidataout: std_logic_vector (7 downto 0);
signal sdhc: std_logic; -- is SDHC card
signal inited: std_logic; -- card initialized
signal inited: std_logic; -- card initialized
signal pgmen: std_logic; -- enable EEPROM programming
-- spi register flags
signal tc: std_logic; -- transmission complete; cleared on spi data read
@ -66,7 +68,6 @@ architecture Behavioral of SpiController is
signal shiftclk : std_logic;
begin
--led <= not (inited);
led <= not (bsy or not slavesel);
bsy <= start_shifting or shifting2;
@ -193,7 +194,8 @@ begin
int_miso <= (miso and not slavesel);
-- outputs
nsel <= slavesel;
nsel <= slavesel;
pgm_en <= pgmen;
tc_proc: process (ndev_sel, shiftdone)
begin
@ -207,14 +209,14 @@ begin
--------------------------
-- cpu register section
-- cpu read
cpu_read: process(addr, spidatain, tc, bsy, frx,
cpu_read: process(addr, spidatain, tc, bsy, frx, pgmen,
ece, divisor, slavesel, wp, card, sdhc, inited)
begin
case addr is
when "00" => -- read SPI data in
data_out <= spidatain;
when "01" => -- read status register
data_out(0) <= '0';
data_out(0) <= pgmen;
data_out(1) <= '0';
data_out(2) <= ece;
data_out(3) <= '0';
@ -247,7 +249,8 @@ begin
divisor <= (others => '0');
spidataout <= (others => '1');
sdhc <= '0';
inited <= '0';
inited <= '0';
pgmen <= '0';
elsif (card = '1') then
sdhc <= '0';
inited <= '0';
@ -255,7 +258,8 @@ begin
case addr is
when "00" => -- write SPI data out (see other process above)
spidataout <= data_in;
when "01" => -- write status register
when "01" => -- write status register
pgmen <= data_in(0);
ece <= data_in(2);
frx <= data_in(4);
-- no bit 5 - 7
@ -273,4 +277,3 @@ begin
end process;
end Behavioral;