Apple-2-HW
/
AppleIISd
mirror of https://github.com/freitz85/AppleIISd.git
1
0
Fork 1
Code Issues Projects Releases Wiki Activity

Update to ISE 14.7

This commit is contained in:
freitz85 2017-09-10 13:41:13 +02:00
parent 2a06e1ba5d
commit 04e26f32da
9 changed files with 1079 additions and 1694 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
VHDL/AddressDecoder.jhd Normal file
View File

@ -0,0 +1 @@
MODULE AddressDecoder

42
VHDL/AddressDecoder.sym Normal file
View File

@ -0,0 +1,42 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="AddressDecoder">
<symboltype>BLOCK</symboltype>
<timestamp>2017-9-3T12:42:25</timestamp>
<pin polarity="Input" x="0" y="-416" name="A10" />
<pin polarity="Input" x="0" y="-352" name="A9" />
<pin polarity="Input" x="0" y="-288" name="A8" />
<pin polarity="Input" x="0" y="-224" name="CLK" />
<pin polarity="Input" x="0" y="-160" name="NIO_SEL" />
<pin polarity="Input" x="0" y="-96" name="NIO_STB" />
<pin polarity="Input" x="0" y="-32" name="NDEV_SEL" />
<pin polarity="Output" x="384" y="-416" name="B10" />
<pin polarity="Output" x="384" y="-288" name="B9" />
<pin polarity="Output" x="384" y="-160" name="B8" />
<pin polarity="Output" x="384" y="-32" name="NOE" />
<graph>
<rect width="256" x="64" y="-448" height="448" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-456" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin A10" />
<line x2="0" y1="-416" y2="-416" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin A9" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin A8" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin CLK" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin NIO_SEL" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin NIO_STB" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin NDEV_SEL" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin B10" />
<line x2="384" y1="-416" y2="-416" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin B9" />
<line x2="384" y1="-288" y2="-288" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin B8" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin NOE" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</graph>
</symbol>

BIN
VHDL/AppleIISd.ipf Normal file
View File

Binary file not shown.

27
VHDL/AppleIISd.npl
View File

@ -1,27 +0,0 @@
JDF G
// Created by Project Navigator ver 1.0
PROJECT AppleIISd
DESIGN appleiisd
DEVFAM xc9500xl
DEVFAMTIME 0
DEVICE xc9572xl
DEVICETIME 1468568184
DEVPKG PC44
DEVPKGTIME 1475334247
DEVSPEED -10
DEVSPEEDTIME 1469967516
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE AppleIISd.vhd
SOURCE AddressDecoder.sch
DEPASSOC appleiisd AppleIISd.ucf
[Normal]
p_CPLDFitterminate=xstvhd, 9500xl, VHDL.t_vm6File, 1504132429, Float
[STRATEGY-LIST]
Normal=True

0
VHDL/AppleIISd.tim Normal file
View File

829
VHDL/AppleIISd.tspec Normal file
View File

@ -0,0 +1,829 @@
AUTO_TS_P2P:FROM:ndev_sel:TO:data<0>:1
AUTO_TS_P2P:FROM:addr<1>:TO:data<0>:1
AUTO_TS_P2P:FROM:addr<0>:TO:data<0>:1
AUTO_TS_P2P:FROM:nrw:TO:data<0>:1
AUTO_TS_P2P:FROM:nphi2:TO:data<0>:1
AUTO_TS_P2P:FROM:extclk:TO:data<0>:1
AUTO_TS_F2P:FROM:slavesel.Q:TO:data<0>:1
AUTO_TS_F2P:FROM:divisor<0>.Q:TO:data<0>:1
AUTO_TS_F2P:FROM:cpha.Q:TO:data<0>:1
AUTO_TS_F2P:FROM:spidatain<0>.Q:TO:data<0>:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:data<0>:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:data<0>:1
AUTO_TS_F2P:FROM:ece.Q:TO:data<0>:1
AUTO_TS_P2P:FROM:ndev_sel:TO:data<1>:1
AUTO_TS_P2P:FROM:addr<1>:TO:data<1>:1
AUTO_TS_P2P:FROM:addr<0>:TO:data<1>:1
AUTO_TS_P2P:FROM:nrw:TO:data<1>:1
AUTO_TS_P2P:FROM:nphi2:TO:data<1>:1
AUTO_TS_P2P:FROM:extclk:TO:data<1>:1
AUTO_TS_F2P:FROM:divisor<1>.Q:TO:data<1>:1
AUTO_TS_F2P:FROM:cpol.Q:TO:data<1>:1
AUTO_TS_F2P:FROM:spidatain<1>.Q:TO:data<1>:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:data<1>:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:data<1>:1
AUTO_TS_F2P:FROM:ece.Q:TO:data<1>:1
AUTO_TS_P2P:FROM:ndev_sel:TO:data<2>:1
AUTO_TS_P2P:FROM:addr<1>:TO:data<2>:1
AUTO_TS_P2P:FROM:addr<0>:TO:data<2>:1
AUTO_TS_P2P:FROM:nrw:TO:data<2>:1
AUTO_TS_P2P:FROM:nphi2:TO:data<2>:1
AUTO_TS_P2P:FROM:extclk:TO:data<2>:1
AUTO_TS_F2P:FROM:divisor<2>.Q:TO:data<2>:1
AUTO_TS_F2P:FROM:ece.Q:TO:data<2>:1
AUTO_TS_F2P:FROM:spidatain<2>.Q:TO:data<2>:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:data<2>:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:data<2>:1
AUTO_TS_P2P:FROM:ndev_sel:TO:data<4>:1
AUTO_TS_P2P:FROM:addr<1>:TO:data<4>:1
AUTO_TS_P2P:FROM:addr<0>:TO:data<4>:1
AUTO_TS_P2P:FROM:nrw:TO:data<4>:1
AUTO_TS_P2P:FROM:nphi2:TO:data<4>:1
AUTO_TS_P2P:FROM:extclk:TO:data<4>:1
AUTO_TS_F2P:FROM:slaveinten.Q:TO:data<4>:1
AUTO_TS_F2P:FROM:frx.Q:TO:data<4>:1
AUTO_TS_F2P:FROM:spidatain<4>.Q:TO:data<4>:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:data<4>:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:data<4>:1
AUTO_TS_F2P:FROM:ece.Q:TO:data<4>:1
AUTO_TS_P2P:FROM:ndev_sel:TO:data<6>:1
AUTO_TS_P2P:FROM:addr<1>:TO:data<6>:1
AUTO_TS_P2P:FROM:addr<0>:TO:data<6>:1
AUTO_TS_P2P:FROM:nrw:TO:data<6>:1
AUTO_TS_P2P:FROM:nphi2:TO:data<6>:1
AUTO_TS_P2P:FROM:card:TO:data<6>:1
AUTO_TS_P2P:FROM:extclk:TO:data<6>:1
AUTO_TS_F2P:FROM:ier.Q:TO:data<6>:1
AUTO_TS_F2P:FROM:spidatain<6>.Q:TO:data<6>:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:data<6>:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:data<6>:1
AUTO_TS_F2P:FROM:ece.Q:TO:data<6>:1
AUTO_TS_P2P:FROM:ndev_sel:TO:data<3>:1
AUTO_TS_P2P:FROM:addr<1>:TO:data<3>:1
AUTO_TS_P2P:FROM:addr<0>:TO:data<3>:1
AUTO_TS_P2P:FROM:nrw:TO:data<3>:1
AUTO_TS_P2P:FROM:nphi2:TO:data<3>:1
AUTO_TS_P2P:FROM:extclk:TO:data<3>:1
AUTO_TS_F2P:FROM:tmo.Q:TO:data<3>:1
AUTO_TS_F2P:FROM:spidatain<3>.Q:TO:data<3>:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:data<3>:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:data<3>:1
AUTO_TS_F2P:FROM:ece.Q:TO:data<3>:1
AUTO_TS_P2P:FROM:ndev_sel:TO:data<7>:1
AUTO_TS_P2P:FROM:addr<1>:TO:data<7>:1
AUTO_TS_P2P:FROM:addr<0>:TO:data<7>:1
AUTO_TS_P2P:FROM:nrw:TO:data<7>:1
AUTO_TS_P2P:FROM:nphi2:TO:data<7>:1
AUTO_TS_P2P:FROM:extclk:TO:data<7>:1
AUTO_TS_P2P:FROM:card:TO:data<7>:1
AUTO_TS_F2P:FROM:tc.Q:TO:data<7>:1
AUTO_TS_F2P:FROM:spidatain<7>.Q:TO:data<7>:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:data<7>:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:data<7>:1
AUTO_TS_F2P:FROM:ece.Q:TO:data<7>:1
AUTO_TS_F2P:FROM:inited_int.Q:TO:data<7>:1
AUTO_TS_P2P:FROM:ndev_sel:TO:data<5>:1
AUTO_TS_P2P:FROM:extclk:TO:data<5>:1
AUTO_TS_P2P:FROM:nphi2:TO:data<5>:1
AUTO_TS_P2P:FROM:addr<1>:TO:data<5>:1
AUTO_TS_P2P:FROM:addr<0>:TO:data<5>:1
AUTO_TS_P2P:FROM:nrw:TO:data<5>:1
AUTO_TS_P2P:FROM:wp:TO:data<5>:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:data<5>:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:data<5>:1
AUTO_TS_F2P:FROM:ece.Q:TO:data<5>:1
AUTO_TS_F2P:FROM:spidatain<5>.Q:TO:data<5>:1
AUTO_TS_P2P:FROM:ndev_sel:TO:spi_mosi:1
AUTO_TS_P2P:FROM:extclk:TO:spi_mosi:1
AUTO_TS_P2P:FROM:nphi2:TO:spi_mosi:1
AUTO_TS_F2P:FROM:int_mosi.Q:TO:spi_mosi:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:spi_mosi:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:spi_mosi:1
AUTO_TS_F2P:FROM:ece.Q:TO:spi_mosi:1
AUTO_TS_F2P:FROM:tmo.Q:TO:spi_mosi:1
AUTO_TS_P2P:FROM:ndev_sel:TO:spi_Nsel:1
AUTO_TS_F2P:FROM:slavesel.Q:TO:spi_Nsel:1
AUTO_TS_P2P:FROM:ndev_sel:TO:spi_sclk:1
AUTO_TS_P2P:FROM:extclk:TO:spi_sclk:1
AUTO_TS_P2P:FROM:nphi2:TO:spi_sclk:1
AUTO_TS_F2P:FROM:int_sclk.Q:TO:spi_sclk:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:spi_sclk:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:spi_sclk:1
AUTO_TS_F2P:FROM:ece.Q:TO:spi_sclk:1
AUTO_TS_P2P:FROM:ndev_sel:TO:ng:1
AUTO_TS_P2P:FROM:nio_stb:TO:ng:1
AUTO_TS_P2P:FROM:nio_sel:TO:ng:1
AUTO_TS_P2P:FROM:a10:TO:b10:1
AUTO_TS_P2P:FROM:nio_stb:TO:b10:1
AUTO_TS_P2P:FROM:a8:TO:b8:1
AUTO_TS_P2P:FROM:nio_stb:TO:b8:1
AUTO_TS_P2P:FROM:a9:TO:b9:1
AUTO_TS_P2P:FROM:nio_stb:TO:b9:1
AUTO_TS_P2P:FROM:ndev_sel:TO:led:1
AUTO_TS_P2P:FROM:extclk:TO:led:1
AUTO_TS_P2P:FROM:nphi2:TO:led:1
AUTO_TS_F2P:FROM:shifting2.Q:TO:led:1
AUTO_TS_F2P:FROM:start_shifting.Q:TO:led:1
AUTO_TS_F2P:FROM:ece.Q:TO:led:1
AUTO_TS_F2P:FROM:slavesel.Q:TO:led:1
AUTO_TS_P2P:FROM:ndev_sel:TO:noe:1
AUTO_TS_P2P:FROM:extclk:TO:noe:1
AUTO_TS_F2P:FROM:add_dec/XLXN_47.Q:TO:noe:1
AUTO_TS_P2P:FROM:ndev_sel:TO:nirq:1
AUTO_TS_F2P:FROM:ier.Q:TO:nirq:1
AUTO_TS_F2P:FROM:slaveinten.Q:TO:nirq:1
AUTO_TS_F2P:FROM:tc.Q:TO:nirq:1
AUTO_TS_F2F:FROM:slavesel.Q:TO:slavesel.D:1
AUTO_TS_F2F:FROM:divisor<0>.Q:TO:slavesel.D:1
AUTO_TS_F2F:FROM:cpha.Q:TO:slavesel.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:slavesel.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:slavesel.D:1
AUTO_TS_F2F:FROM:spidatain<0>.Q:TO:slavesel.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:slavesel.D:1
AUTO_TS_P2F:FROM:data<0>:TO:slavesel.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:slavesel.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:slavesel.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:slavesel.D:1
AUTO_TS_P2F:FROM:nrw:TO:slavesel.D:1
AUTO_TS_P2F:FROM:nphi2:TO:slavesel.D:1
AUTO_TS_P2F:FROM:extclk:TO:slavesel.D:1
AUTO_TS_F2F:FROM:divisor<1>.Q:TO:cpol.D:1
AUTO_TS_F2F:FROM:cpol.Q:TO:cpol.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:cpol.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:cpol.D:1
AUTO_TS_F2F:FROM:spidatain<1>.Q:TO:cpol.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:cpol.D:1
AUTO_TS_P2F:FROM:data<1>:TO:cpol.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:cpol.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:cpol.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:cpol.D:1
AUTO_TS_P2F:FROM:nrw:TO:cpol.D:1
AUTO_TS_P2F:FROM:nphi2:TO:cpol.D:1
AUTO_TS_P2F:FROM:extclk:TO:cpol.D:1
AUTO_TS_F2F:FROM:divisor<2>.Q:TO:ece.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:ece.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:ece.D:1
AUTO_TS_F2F:FROM:spidatain<2>.Q:TO:ece.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:ece.D:1
AUTO_TS_P2F:FROM:data<2>:TO:ece.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:ece.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:ece.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:ece.D:1
AUTO_TS_P2F:FROM:nrw:TO:ece.D:1
AUTO_TS_P2F:FROM:nphi2:TO:ece.D:1
AUTO_TS_P2F:FROM:extclk:TO:ece.D:1
AUTO_TS_F2F:FROM:slavesel.Q:TO:cpha.D:1
AUTO_TS_F2F:FROM:divisor<0>.Q:TO:cpha.D:1
AUTO_TS_F2F:FROM:cpha.Q:TO:cpha.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:cpha.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:cpha.D:1
AUTO_TS_F2F:FROM:spidatain<0>.Q:TO:cpha.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:cpha.D:1
AUTO_TS_P2F:FROM:data<0>:TO:cpha.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:cpha.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:cpha.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:cpha.D:1
AUTO_TS_P2F:FROM:nrw:TO:cpha.D:1
AUTO_TS_P2F:FROM:nphi2:TO:cpha.D:1
AUTO_TS_P2F:FROM:extclk:TO:cpha.D:1
AUTO_TS_F2F:FROM:slaveinten.Q:TO:frx.D:1
AUTO_TS_F2F:FROM:frx.Q:TO:frx.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:frx.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:frx.D:1
AUTO_TS_F2F:FROM:spidatain<4>.Q:TO:frx.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:frx.D:1
AUTO_TS_P2F:FROM:data<4>:TO:frx.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:frx.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:frx.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:frx.D:1
AUTO_TS_P2F:FROM:nrw:TO:frx.D:1
AUTO_TS_P2F:FROM:nphi2:TO:frx.D:1
AUTO_TS_P2F:FROM:extclk:TO:frx.D:1
AUTO_TS_F2F:FROM:ier.Q:TO:ier.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:ier.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:ier.D:1
AUTO_TS_F2F:FROM:spidatain<6>.Q:TO:ier.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:ier.D:1
AUTO_TS_P2F:FROM:data<6>:TO:ier.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:ier.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:ier.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:ier.D:1
AUTO_TS_P2F:FROM:nrw:TO:ier.D:1
AUTO_TS_P2F:FROM:nphi2:TO:ier.D:1
AUTO_TS_P2F:FROM:card:TO:ier.D:1
AUTO_TS_P2F:FROM:extclk:TO:ier.D:1
AUTO_TS_F2F:FROM:slaveinten.Q:TO:slaveinten.D:1
AUTO_TS_F2F:FROM:frx.Q:TO:slaveinten.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:slaveinten.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:slaveinten.D:1
AUTO_TS_F2F:FROM:spidatain<4>.Q:TO:slaveinten.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:slaveinten.D:1
AUTO_TS_P2F:FROM:data<4>:TO:slaveinten.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:slaveinten.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:slaveinten.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:slaveinten.D:1
AUTO_TS_P2F:FROM:nrw:TO:slaveinten.D:1
AUTO_TS_P2F:FROM:nphi2:TO:slaveinten.D:1
AUTO_TS_P2F:FROM:extclk:TO:slaveinten.D:1
AUTO_TS_F2F:FROM:tmo.Q:TO:tmo.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:tmo.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:tmo.D:1
AUTO_TS_F2F:FROM:spidatain<3>.Q:TO:tmo.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:tmo.D:1
AUTO_TS_P2F:FROM:data<3>:TO:tmo.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:tmo.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:tmo.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:tmo.D:1
AUTO_TS_P2F:FROM:nrw:TO:tmo.D:1
AUTO_TS_P2F:FROM:nphi2:TO:tmo.D:1
AUTO_TS_P2F:FROM:extclk:TO:tmo.D:1
AUTO_TS_F2F:FROM:slavesel.Q:TO:divisor<0>.D:1
AUTO_TS_F2F:FROM:divisor<0>.Q:TO:divisor<0>.D:1
AUTO_TS_F2F:FROM:cpha.Q:TO:divisor<0>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:divisor<0>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:divisor<0>.D:1
AUTO_TS_F2F:FROM:spidatain<0>.Q:TO:divisor<0>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:divisor<0>.D:1
AUTO_TS_P2F:FROM:data<0>:TO:divisor<0>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:divisor<0>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:divisor<0>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:divisor<0>.D:1
AUTO_TS_P2F:FROM:nrw:TO:divisor<0>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:divisor<0>.D:1
AUTO_TS_P2F:FROM:extclk:TO:divisor<0>.D:1
AUTO_TS_F2F:FROM:divisor<1>.Q:TO:divisor<1>.D:1
AUTO_TS_F2F:FROM:cpol.Q:TO:divisor<1>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:divisor<1>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:divisor<1>.D:1
AUTO_TS_F2F:FROM:spidatain<1>.Q:TO:divisor<1>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:divisor<1>.D:1
AUTO_TS_P2F:FROM:data<1>:TO:divisor<1>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:divisor<1>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:divisor<1>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:divisor<1>.D:1
AUTO_TS_P2F:FROM:nrw:TO:divisor<1>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:divisor<1>.D:1
AUTO_TS_P2F:FROM:extclk:TO:divisor<1>.D:1
AUTO_TS_F2F:FROM:divisor<2>.Q:TO:divisor<2>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:divisor<2>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:divisor<2>.D:1
AUTO_TS_F2F:FROM:spidatain<2>.Q:TO:divisor<2>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:divisor<2>.D:1
AUTO_TS_P2F:FROM:data<2>:TO:divisor<2>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:divisor<2>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:divisor<2>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:divisor<2>.D:1
AUTO_TS_P2F:FROM:nrw:TO:divisor<2>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:divisor<2>.D:1
AUTO_TS_P2F:FROM:extclk:TO:divisor<2>.D:1
AUTO_TS_F2F:FROM:tc.Q:TO:inited_int.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:inited_int.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:inited_int.D:1
AUTO_TS_F2F:FROM:inited_int.Q:TO:inited_int.D:1
AUTO_TS_F2F:FROM:spidatain<7>.Q:TO:inited_int.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:inited_int.D:1
AUTO_TS_P2F:FROM:data<7>:TO:inited_int.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:inited_int.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:inited_int.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:inited_int.D:1
AUTO_TS_P2F:FROM:nrw:TO:inited_int.D:1
AUTO_TS_P2F:FROM:nphi2:TO:inited_int.D:1
AUTO_TS_P2F:FROM:extclk:TO:inited_int.D:1
AUTO_TS_P2F:FROM:card:TO:inited_int.D:1
AUTO_TS_F2F:FROM:slavesel.Q:TO:spidataout<0>.D:1
AUTO_TS_F2F:FROM:divisor<0>.Q:TO:spidataout<0>.D:1
AUTO_TS_F2F:FROM:cpha.Q:TO:spidataout<0>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidataout<0>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidataout<0>.D:1
AUTO_TS_F2F:FROM:spidatain<0>.Q:TO:spidataout<0>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidataout<0>.D:1
AUTO_TS_P2F:FROM:data<0>:TO:spidataout<0>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<0>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<0>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<0>.D:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<0>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidataout<0>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidataout<0>.D:1
AUTO_TS_F2F:FROM:divisor<1>.Q:TO:spidataout<1>.D:1
AUTO_TS_F2F:FROM:cpol.Q:TO:spidataout<1>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidataout<1>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidataout<1>.D:1
AUTO_TS_F2F:FROM:spidatain<1>.Q:TO:spidataout<1>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidataout<1>.D:1
AUTO_TS_P2F:FROM:data<1>:TO:spidataout<1>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<1>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<1>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<1>.D:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<1>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidataout<1>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidataout<1>.D:1
AUTO_TS_F2F:FROM:divisor<2>.Q:TO:spidataout<2>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidataout<2>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidataout<2>.D:1
AUTO_TS_F2F:FROM:spidatain<2>.Q:TO:spidataout<2>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidataout<2>.D:1
AUTO_TS_P2F:FROM:data<2>:TO:spidataout<2>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<2>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<2>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<2>.D:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<2>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidataout<2>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidataout<2>.D:1
AUTO_TS_F2F:FROM:tmo.Q:TO:spidataout<3>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidataout<3>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidataout<3>.D:1
AUTO_TS_F2F:FROM:spidatain<3>.Q:TO:spidataout<3>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidataout<3>.D:1
AUTO_TS_P2F:FROM:data<3>:TO:spidataout<3>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<3>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<3>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<3>.D:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<3>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidataout<3>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidataout<3>.D:1
AUTO_TS_F2F:FROM:slaveinten.Q:TO:spidataout<4>.D:1
AUTO_TS_F2F:FROM:frx.Q:TO:spidataout<4>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidataout<4>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidataout<4>.D:1
AUTO_TS_F2F:FROM:spidatain<4>.Q:TO:spidataout<4>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidataout<4>.D:1
AUTO_TS_P2F:FROM:data<4>:TO:spidataout<4>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<4>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<4>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<4>.D:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<4>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidataout<4>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidataout<4>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidataout<5>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidataout<5>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidataout<5>.D:1
AUTO_TS_F2F:FROM:spidatain<5>.Q:TO:spidataout<5>.D:1
AUTO_TS_P2F:FROM:data<5>:TO:spidataout<5>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<5>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidataout<5>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidataout<5>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<5>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<5>.D:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<5>.D:1
AUTO_TS_P2F:FROM:wp:TO:spidataout<5>.D:1
AUTO_TS_F2F:FROM:ier.Q:TO:spidataout<6>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidataout<6>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidataout<6>.D:1
AUTO_TS_F2F:FROM:spidatain<6>.Q:TO:spidataout<6>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidataout<6>.D:1
AUTO_TS_P2F:FROM:data<6>:TO:spidataout<6>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<6>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<6>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<6>.D:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<6>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidataout<6>.D:1
AUTO_TS_P2F:FROM:card:TO:spidataout<6>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidataout<6>.D:1
AUTO_TS_F2F:FROM:tc.Q:TO:spidataout<7>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidataout<7>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidataout<7>.D:1
AUTO_TS_F2F:FROM:inited_int.Q:TO:spidataout<7>.D:1
AUTO_TS_F2F:FROM:spidatain<7>.Q:TO:spidataout<7>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidataout<7>.D:1
AUTO_TS_P2F:FROM:data<7>:TO:spidataout<7>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<7>.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<7>.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<7>.D:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<7>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidataout<7>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidataout<7>.D:1
AUTO_TS_P2F:FROM:card:TO:spidataout<7>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:start_shifting.D:1
AUTO_TS_F2F:FROM:frx.Q:TO:start_shifting.D:1
AUTO_TS_P2F:FROM:addr<1>:TO:start_shifting.D:1
AUTO_TS_P2F:FROM:addr<0>:TO:start_shifting.D:1
AUTO_TS_P2F:FROM:nrw:TO:start_shifting.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:start_shifting.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:start_shifting.RSTF:1
AUTO_TS_F2F:FROM:ece.Q:TO:start_shifting.RSTF:1
AUTO_TS_F2F:FROM:shiftdone.Q:TO:start_shifting.RSTF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:start_shifting.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:start_shifting.RSTF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:start_shifting.RSTF:1
AUTO_TS_P2F:FROM:extclk:TO:start_shifting.RSTF:1
AUTO_TS_P2F:FROM:nphi2:TO:start_shifting.RSTF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:tc.SETF:1
AUTO_TS_F2F:FROM:ece.Q:TO:tc.SETF:1
AUTO_TS_F2F:FROM:shiftdone.Q:TO:tc.SETF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:tc.SETF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:tc.SETF:1
AUTO_TS_P2F:FROM:extclk:TO:tc.SETF:1
AUTO_TS_P2F:FROM:nphi2:TO:tc.SETF:1
AUTO_TS_F2F:FROM:shiftcnt<3>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:shiftcnt<2>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:shiftcnt<1>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:shiftdone.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:spidataout<1>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:spidataout<2>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:spidataout<4>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:spidataout<5>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:spidataout<6>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:spidataout<0>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:spidataout<3>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:spidataout<7>.Q:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:int_mosi.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:int_mosi.D:1
AUTO_TS_P2F:FROM:extclk:TO:int_mosi.D:1
AUTO_TS_P2F:FROM:nphi2:TO:int_mosi.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:int_mosi.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:int_mosi.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:int_mosi.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:int_mosi.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:int_mosi.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:int_mosi.CLKF:1
AUTO_TS_F2F:FROM:slavesel.Q:TO:spidatain<0>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<0>.D:1
AUTO_TS_P2F:FROM:spi_miso:TO:spidatain<0>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<0>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<0>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<0>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<0>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<0>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<0>.CLKF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<0>.CE:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<0>.CE:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:spidatain<0>.CE:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<0>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<0>.CE:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<0>.CE:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<0>.CE:1
AUTO_TS_F2F:FROM:spidatain<0>.Q:TO:spidatain<1>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<1>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<1>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<1>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<1>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<1>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<1>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<1>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<1>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<1>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<1>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<1>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<1>.CLKF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<1>.CE:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<1>.CE:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:spidatain<1>.CE:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<1>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<1>.CE:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<1>.CE:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<1>.CE:1
AUTO_TS_F2F:FROM:spidatain<1>.Q:TO:spidatain<2>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<2>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<2>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<2>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<2>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<2>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<2>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<2>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<2>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<2>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<2>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<2>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<2>.CLKF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<2>.CE:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<2>.CE:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:spidatain<2>.CE:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<2>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<2>.CE:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<2>.CE:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<2>.CE:1
AUTO_TS_F2F:FROM:spidatain<2>.Q:TO:spidatain<3>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<3>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<3>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<3>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<3>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<3>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<3>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<3>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<3>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<3>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<3>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<3>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<3>.CLKF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<3>.CE:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<3>.CE:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:spidatain<3>.CE:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<3>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<3>.CE:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<3>.CE:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<3>.CE:1
AUTO_TS_F2F:FROM:spidatain<3>.Q:TO:spidatain<4>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<4>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<4>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<4>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<4>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<4>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<4>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<4>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<4>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<4>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<4>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<4>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<4>.CLKF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<4>.CE:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<4>.CE:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:spidatain<4>.CE:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<4>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<4>.CE:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<4>.CE:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<4>.CE:1
AUTO_TS_F2F:FROM:spidatain<4>.Q:TO:spidatain<5>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<5>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<5>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<5>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<5>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<5>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<5>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<5>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<5>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<5>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<5>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<5>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<5>.CLKF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<5>.CE:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<5>.CE:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:spidatain<5>.CE:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<5>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<5>.CE:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<5>.CE:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<5>.CE:1
AUTO_TS_F2F:FROM:spidatain<5>.Q:TO:spidatain<6>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<6>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<6>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<6>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<6>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<6>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<6>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<6>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<6>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<6>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<6>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<6>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<6>.CLKF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<6>.CE:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<6>.CE:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:spidatain<6>.CE:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<6>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<6>.CE:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<6>.CE:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<6>.CE:1
AUTO_TS_F2F:FROM:spidatain<6>.Q:TO:spidatain<7>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<7>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<7>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<7>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<7>.D:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<7>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<7>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<7>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<7>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<7>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<7>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<7>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<7>.CLKF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<7>.CE:1
AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<7>.CE:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:spidatain<7>.CE:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<7>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<7>.CE:1
AUTO_TS_P2F:FROM:extclk:TO:spidatain<7>.CE:1
AUTO_TS_P2F:FROM:nphi2:TO:spidatain<7>.CE:1
AUTO_TS_F2F:FROM:cpol.Q:TO:int_sclk.D:1
AUTO_TS_F2F:FROM:shiftdone.Q:TO:int_sclk.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:int_sclk.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:int_sclk.D:1
AUTO_TS_F2F:FROM:cpha.Q:TO:int_sclk.D:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:int_sclk.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:int_sclk.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:int_sclk.D:1
AUTO_TS_P2F:FROM:nreset:TO:int_sclk.D:1
AUTO_TS_P2F:FROM:extclk:TO:int_sclk.D:1
AUTO_TS_P2F:FROM:nphi2:TO:int_sclk.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:int_sclk.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:int_sclk.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:int_sclk.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:int_sclk.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:int_sclk.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:int_sclk.CLKF:1
AUTO_TS_F2F:FROM:cpol.Q:TO:int_sclk.SETF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:int_sclk.SETF:1
AUTO_TS_P2F:FROM:nreset:TO:int_sclk.SETF:1
AUTO_TS_F2F:FROM:cpol.Q:TO:int_sclk.RSTF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:int_sclk.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:int_sclk.RSTF:1
AUTO_TS_F2F:FROM:shiftcnt<3>.Q:TO:shiftcnt<3>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<3>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<3>.D:1
AUTO_TS_F2F:FROM:shiftcnt<2>.Q:TO:shiftcnt<3>.D:1
AUTO_TS_F2F:FROM:shiftcnt<1>.Q:TO:shiftcnt<3>.D:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:shiftcnt<3>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<3>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<3>.D:1
AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<3>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<3>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<3>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<3>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<3>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<3>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<3>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<3>.CLKF:1
AUTO_TS_F2F:FROM:shiftcnt<2>.Q:TO:shiftcnt<2>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<2>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<2>.D:1
AUTO_TS_F2F:FROM:shiftcnt<1>.Q:TO:shiftcnt<2>.D:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:shiftcnt<2>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<2>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<2>.D:1
AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<2>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<2>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<2>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<2>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<2>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<2>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<2>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<2>.CLKF:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<0>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<0>.D:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:shiftcnt<0>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<0>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<0>.D:1
AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<0>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<0>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<0>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<0>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<0>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<0>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<0>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<0>.CLKF:1
AUTO_TS_F2F:FROM:shiftcnt<1>.Q:TO:shiftcnt<1>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<1>.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<1>.D:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:shiftcnt<1>.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<1>.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<1>.D:1
AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<1>.D:1
AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<1>.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<1>.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<1>.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<1>.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<1>.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<1>.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<1>.CLKF:1
AUTO_TS_F2F:FROM:shiftcnt<3>.Q:TO:shiftdone.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftdone.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:shiftdone.D:1
AUTO_TS_F2F:FROM:shiftcnt<2>.Q:TO:shiftdone.D:1
AUTO_TS_F2F:FROM:shiftcnt<1>.Q:TO:shiftdone.D:1
AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:shiftdone.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftdone.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shiftdone.D:1
AUTO_TS_P2F:FROM:extclk:TO:shiftdone.D:1
AUTO_TS_P2F:FROM:nphi2:TO:shiftdone.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftdone.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:shiftdone.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftdone.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shiftdone.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:shiftdone.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:shiftdone.CLKF:1
AUTO_TS_F2F:FROM:shiftdone.Q:TO:shifting2.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shifting2.D:1
AUTO_TS_F2F:FROM:ece.Q:TO:shifting2.D:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shifting2.D:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shifting2.D:1
AUTO_TS_P2F:FROM:extclk:TO:shifting2.D:1
AUTO_TS_P2F:FROM:nphi2:TO:shifting2.D:1
AUTO_TS_F2F:FROM:shifting2.Q:TO:shifting2.CLKF:1
AUTO_TS_F2F:FROM:ece.Q:TO:shifting2.CLKF:1
AUTO_TS_F2F:FROM:start_shifting.Q:TO:shifting2.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:shifting2.CLKF:1
AUTO_TS_P2F:FROM:extclk:TO:shifting2.CLKF:1
AUTO_TS_P2F:FROM:nphi2:TO:shifting2.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:int_mosi.SETF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:slavesel.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:slavesel.SETF:1
AUTO_TS_P2F:FROM:addr<1>:TO:slavesel.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:slavesel.CE:1
AUTO_TS_P2F:FROM:nrw:TO:slavesel.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:cpol.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:cpol.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:cpol.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:cpol.CE:1
AUTO_TS_P2F:FROM:nrw:TO:cpol.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:ece.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:ece.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:ece.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:ece.CE:1
AUTO_TS_P2F:FROM:nrw:TO:ece.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:cpha.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:cpha.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:cpha.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:cpha.CE:1
AUTO_TS_P2F:FROM:nrw:TO:cpha.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:frx.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:frx.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:frx.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:frx.CE:1
AUTO_TS_P2F:FROM:nrw:TO:frx.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:ier.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:ier.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:ier.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:ier.CE:1
AUTO_TS_P2F:FROM:nrw:TO:ier.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:slaveinten.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:slaveinten.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:slaveinten.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:slaveinten.CE:1
AUTO_TS_P2F:FROM:nrw:TO:slaveinten.CE:1
AUTO_TS_P2F:FROM:nreset:TO:spidatain<0>.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:spidatain<1>.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:spidatain<2>.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:spidatain<3>.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:spidatain<4>.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:spidatain<5>.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:spidatain<6>.RSTF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:tmo.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:tmo.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:tmo.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:tmo.CE:1
AUTO_TS_P2F:FROM:nrw:TO:tmo.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:divisor<0>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:divisor<0>.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:divisor<0>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:divisor<0>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:divisor<0>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:divisor<1>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:divisor<1>.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:divisor<1>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:divisor<1>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:divisor<1>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:divisor<2>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:divisor<2>.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:divisor<2>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:divisor<2>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:divisor<2>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:inited_int.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:inited_int.RSTF:1
AUTO_TS_P2F:FROM:addr<1>:TO:inited_int.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:inited_int.CE:1
AUTO_TS_P2F:FROM:nrw:TO:inited_int.CE:1
AUTO_TS_P2F:FROM:nreset:TO:spidatain<7>.RSTF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<0>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:spidataout<0>.SETF:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<0>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<0>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<0>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<1>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:spidataout<1>.SETF:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<1>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<1>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<1>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<2>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:spidataout<2>.SETF:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<2>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<2>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<2>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<3>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:spidataout<3>.SETF:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<3>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<3>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<3>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<4>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:spidataout<4>.SETF:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<4>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<4>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<4>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<5>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:spidataout<5>.SETF:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<5>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<5>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<5>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<6>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:spidataout<6>.SETF:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<6>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<6>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<6>.CE:1
AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<7>.CLKF:1
AUTO_TS_P2F:FROM:nreset:TO:spidataout<7>.SETF:1
AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<7>.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<7>.CE:1
AUTO_TS_P2F:FROM:nrw:TO:spidataout<7>.CE:1
AUTO_TS_P2F:FROM:nreset:TO:shiftcnt<3>.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:shiftcnt<2>.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:shiftcnt<0>.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:shiftcnt<1>.RSTF:1
AUTO_TS_P2F:FROM:nreset:TO:shiftdone.RSTF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:start_shifting.CLKF:1
AUTO_TS_P2F:FROM:ndev_sel:TO:tc.CLKF:1
AUTO_TS_P2F:FROM:addr<1>:TO:tc.CE:1
AUTO_TS_P2F:FROM:addr<0>:TO:tc.CE:1
AUTO_TS_P2F:FROM:a9:TO:add_dec/XLXN_47.D:1
AUTO_TS_P2F:FROM:a8:TO:add_dec/XLXN_47.D:1
AUTO_TS_P2F:FROM:a10:TO:add_dec/XLXN_47.D:1
AUTO_TS_P2F:FROM:nio_stb:TO:add_dec/XLXN_47.D:1
AUTO_TS_P2F:FROM:extclk:TO:add_dec/XLXN_47.CLKF:1

206
VHDL/AppleIISd.xise Normal file
View File

@ -0,0 +1,206 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="_" xil_pn:valueState="non-default"/>
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AppleIISd|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="AppleIISd.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AppleIISd_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="AppleIISd.ipf" xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-09-03T14:20:38" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="FD3A1F2B88484D658A65860211499755" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

1667
VHDL/appleiisd.jed
View File

File diff suppressed because it is too large Load Diff

1
VHDL/sch2HdlBatchFile Normal file
View File

@ -0,0 +1 @@
sch2hdl,-intstyle,ise,-family,xc9500xl,-verilog,U:/AppleIISd/VHDL/AddressDecoder.vf,-w,U:/AppleIISd/VHDL/AddressDecoder.sch