diff --git a/VHDL/AddressDecoder.sch b/VHDL/AddressDecoder.sch index 2d2da0a..8689c2c 100644 --- a/VHDL/AddressDecoder.sch +++ b/VHDL/AddressDecoder.sch @@ -6,31 +6,31 @@ BEGIN SCHEMATIC EDITTRAIT all:0 END ATTR BEGIN NETLIST - SIGNAL NIO_STB - SIGNAL XLXN_4 SIGNAL A10 SIGNAL A9 SIGNAL A8 SIGNAL XLXN_10 - SIGNAL XLXN_11 - SIGNAL NOE SIGNAL CLK SIGNAL XLXN_14 - SIGNAL A10_B - SIGNAL A9_B - SIGNAL A8_B + SIGNAL B10 + SIGNAL B9 + SIGNAL B8 + SIGNAL NOE + SIGNAL XLXN_29 SIGNAL NIO_SEL - SIGNAL XLXN_19 - PORT Input NIO_STB + SIGNAL NIO_STB + SIGNAL XLXN_38 + SIGNAL XLXN_46 PORT Input A10 PORT Input A9 PORT Input A8 - PORT Output NOE PORT Input CLK - PORT Output A10_B - PORT Output A9_B - PORT Output A8_B + PORT Output B10 + PORT Output B9 + PORT Output B8 + PORT Output NOE PORT Input NIO_SEL + PORT Input NIO_STB BEGIN BLOCKDEF fdrs TIMESTAMP 2001 3 9 11 23 0 LINE N 0 -128 64 -128 @@ -55,17 +55,6 @@ BEGIN SCHEMATIC LINE N 64 0 64 -64 CIRCLE N 128 -48 160 -16 END BLOCKDEF - BEGIN BLOCKDEF nand2 - TIMESTAMP 2001 3 9 11 23 50 - LINE N 0 -64 64 -64 - LINE N 0 -128 64 -128 - LINE N 256 -96 216 -96 - CIRCLE N 192 -108 216 -84 - LINE N 64 -48 64 -144 - LINE N 64 -144 144 -144 - LINE N 144 -48 64 -48 - ARC N 96 -144 192 -48 144 -48 144 -144 - END BLOCKDEF BEGIN BLOCKDEF vcc TIMESTAMP 2001 3 9 11 23 11 LINE N 96 -64 32 -64 @@ -82,159 +71,152 @@ BEGIN SCHEMATIC LINE N 64 -144 144 -144 LINE N 64 -48 64 -144 END BLOCKDEF - BEGIN BLOCKDEF and4b1 - TIMESTAMP 2001 5 11 10 43 32 - LINE N 0 -64 40 -64 - CIRCLE N 40 -76 64 -52 - LINE N 0 -128 64 -128 - LINE N 0 -192 64 -192 - LINE N 0 -256 64 -256 - LINE N 256 -160 192 -160 - LINE N 64 -64 64 -256 + BEGIN BLOCKDEF and4 + TIMESTAMP 2001 5 11 10 43 14 LINE N 144 -112 64 -112 ARC N 96 -208 192 -112 144 -112 144 -208 LINE N 64 -208 144 -208 + LINE N 64 -64 64 -256 + LINE N 256 -160 192 -160 + LINE N 0 -256 64 -256 + LINE N 0 -192 64 -192 + LINE N 0 -128 64 -128 + LINE N 0 -64 64 -64 END BLOCKDEF - BEGIN BLOCK XLXI_13 nand2 - PIN I0 NIO_SEL - PIN I1 NIO_STB - PIN O XLXN_4 - END BLOCK - BEGIN BLOCK XLXI_14 nand2 - PIN I0 XLXN_11 - PIN I1 XLXN_4 - PIN O NOE - END BLOCK BEGIN BLOCK XLXI_16 fdrs PIN C CLK PIN D XLXN_14 PIN R XLXN_10 - PIN S XLXN_19 - PIN Q XLXN_11 + PIN S XLXN_46 + PIN Q XLXN_29 END BLOCK BEGIN BLOCK XLXI_17 vcc PIN P XLXN_14 END BLOCK BEGIN BLOCK XLXI_18 and2 PIN I0 A10 - PIN I1 NIO_SEL - PIN O A10_B + PIN I1 XLXN_38 + PIN O B10 END BLOCK BEGIN BLOCK XLXI_19 and2 PIN I0 A9 - PIN I1 NIO_SEL - PIN O A9_B + PIN I1 XLXN_38 + PIN O B9 END BLOCK BEGIN BLOCK XLXI_20 and2 PIN I0 A8 - PIN I1 NIO_SEL - PIN O A8_B + PIN I1 XLXN_38 + PIN O B8 END BLOCK BEGIN BLOCK XLXI_22 inv PIN I NIO_SEL - PIN O XLXN_19 + PIN O XLXN_46 END BLOCK - BEGIN BLOCK XLXI_23 and4b1 - PIN I0 NIO_STB - PIN I1 A10 - PIN I2 A9 - PIN I3 A8 + BEGIN BLOCK XLXI_29 inv + PIN I XLXN_29 + PIN O NOE + END BLOCK + BEGIN BLOCK XLXI_30 and4 + PIN I0 A8 + PIN I1 A9 + PIN I2 A10 + PIN I3 XLXN_38 PIN O XLXN_10 END BLOCK + BEGIN BLOCK XLXI_31 inv + PIN I NIO_STB + PIN O XLXN_38 + END BLOCK END NETLIST BEGIN SHEET 1 3520 2720 - IOMARKER 320 496 NIO_STB R180 28 - IOMARKER 320 560 NIO_SEL R180 28 - BEGIN BRANCH NIO_STB - WIRE 320 496 368 496 - WIRE 368 496 368 640 - WIRE 368 640 608 640 - WIRE 368 496 1120 496 - END BRANCH - BEGIN BRANCH XLXN_4 - WIRE 1376 528 1744 528 - END BRANCH BEGIN BRANCH A10 WIRE 320 704 592 704 - WIRE 592 704 608 704 - WIRE 592 704 592 1168 - WIRE 592 1168 1088 1168 + WIRE 592 704 704 704 + WIRE 592 704 592 992 + WIRE 592 992 1088 992 END BRANCH BEGIN BRANCH A9 WIRE 320 768 528 768 - WIRE 528 768 608 768 - WIRE 528 768 528 1312 - WIRE 528 1312 1088 1312 + WIRE 528 768 704 768 + WIRE 528 768 528 1136 + WIRE 528 1136 1088 1136 END BRANCH BEGIN BRANCH A8 - WIRE 320 832 480 832 - WIRE 480 832 608 832 - WIRE 480 832 480 1456 - WIRE 480 1456 1088 1456 + WIRE 320 832 464 832 + WIRE 464 832 704 832 + WIRE 464 832 464 1280 + WIRE 464 1280 1088 1280 END BRANCH IOMARKER 320 704 A10 R180 28 IOMARKER 320 768 A9 R180 28 IOMARKER 320 832 A8 R180 28 - BEGIN BRANCH NOE - WIRE 2000 560 2032 560 - END BRANCH BEGIN BRANCH CLK - WIRE 320 928 1392 928 + WIRE 320 576 912 576 + WIRE 912 576 912 640 + WIRE 912 640 992 640 END BRANCH - IOMARKER 320 928 CLK R180 28 - INSTANCE XLXI_18 1088 1232 R0 - INSTANCE XLXI_19 1088 1376 R0 - INSTANCE XLXI_20 1088 1520 R0 - BEGIN BRANCH A10_B - WIRE 1344 1136 1744 1136 + BEGIN BRANCH B10 + WIRE 1344 960 1360 960 + WIRE 1360 960 1664 960 END BRANCH - BEGIN BRANCH A9_B - WIRE 1344 1280 1744 1280 + BEGIN BRANCH B9 + WIRE 1344 1104 1360 1104 + WIRE 1360 1104 1664 1104 END BRANCH - BEGIN BRANCH A8_B - WIRE 1344 1424 1744 1424 + BEGIN BRANCH B8 + WIRE 1344 1248 1360 1248 + WIRE 1360 1248 1664 1248 END BRANCH - INSTANCE XLXI_17 976 800 R0 - BEGIN BRANCH XLXN_14 - WIRE 1040 800 1392 800 + BEGIN BRANCH NOE + WIRE 1616 512 1664 512 END BRANCH - INSTANCE XLXI_13 1120 624 R0 - BEGIN BRANCH XLXN_11 - WIRE 1728 592 1744 592 - WIRE 1728 592 1728 656 - WIRE 1728 656 1840 656 - WIRE 1840 656 1840 800 - WIRE 1776 800 1840 800 - END BRANCH - IOMARKER 1744 1136 A10_B R0 28 - IOMARKER 1744 1280 A9_B R0 28 - IOMARKER 1744 1424 A8_B R0 28 - IOMARKER 2032 560 NOE R0 28 - INSTANCE XLXI_14 1744 656 R0 - INSTANCE XLXI_16 1392 1056 R0 - BEGIN BRANCH XLXN_10 - WIRE 864 736 880 736 - WIRE 880 736 880 1024 - WIRE 880 1024 1392 1024 + BEGIN BRANCH XLXN_29 + WIRE 1376 512 1392 512 END BRANCH BEGIN BRANCH NIO_SEL - WIRE 320 560 944 560 - WIRE 944 560 1088 560 - WIRE 1088 560 1120 560 - WIRE 1088 560 1088 704 - WIRE 1088 704 1120 704 - WIRE 944 560 944 1104 - WIRE 944 1104 1088 1104 - WIRE 944 1104 944 1248 - WIRE 944 1248 944 1392 - WIRE 944 1392 1088 1392 - WIRE 944 1248 1088 1248 + WIRE 320 368 352 368 END BRANCH - BEGIN BRANCH XLXN_19 - WIRE 1344 704 1360 704 - WIRE 1360 704 1392 704 + BEGIN BRANCH NIO_STB + WIRE 320 640 336 640 END BRANCH - INSTANCE XLXI_22 1120 736 R0 - INSTANCE XLXI_23 608 576 M180 + IOMARKER 320 368 NIO_SEL R180 28 + IOMARKER 320 640 NIO_STB R180 28 + INSTANCE XLXI_31 336 672 R0 + BEGIN BRANCH XLXN_38 + WIRE 560 640 672 640 + WIRE 672 640 704 640 + WIRE 672 640 672 928 + WIRE 672 928 1088 928 + WIRE 672 928 672 1072 + WIRE 672 1072 1088 1072 + WIRE 672 1072 672 1216 + WIRE 672 1216 1088 1216 + END BRANCH + INSTANCE XLXI_30 704 896 R0 + BEGIN BRANCH XLXN_10 + WIRE 960 736 976 736 + WIRE 976 736 992 736 + END BRANCH + BEGIN BRANCH XLXN_14 + WIRE 848 496 848 512 + WIRE 848 512 992 512 + END BRANCH + IOMARKER 320 576 CLK R180 28 + INSTANCE XLXI_17 784 496 R0 + INSTANCE XLXI_22 352 400 R0 + BEGIN BRANCH XLXN_46 + WIRE 576 368 592 368 + WIRE 592 368 992 368 + WIRE 992 368 992 416 + END BRANCH + INSTANCE XLXI_16 992 768 R0 + INSTANCE XLXI_29 1392 544 R0 + IOMARKER 1664 512 NOE R0 28 + INSTANCE XLXI_18 1088 1056 R0 + INSTANCE XLXI_19 1088 1200 R0 + INSTANCE XLXI_20 1088 1344 R0 + IOMARKER 1664 960 B10 R0 28 + IOMARKER 1664 1104 B9 R0 28 + IOMARKER 1664 1248 B8 R0 28 END SHEET END SCHEMATIC diff --git a/VHDL/AppleIISd.vhd b/VHDL/AppleIISd.vhd index b32854e..c105f1d 100644 --- a/VHDL/AppleIISd.vhd +++ b/VHDL/AppleIISd.vhd @@ -46,8 +46,6 @@ use AddressDecoder.ALL; --use UNISIM.VComponents.all; entity AppleIISd is - - Port ( cpu_d : inout STD_LOGIC_VECTOR (7 downto 0); cpu_rnw : in STD_LOGIC; cpu_Nirq : out STD_LOGIC; @@ -137,9 +135,9 @@ architecture Behavioral of AppleIISd is CLK : in std_logic; NIO_SEL : in std_logic; NIO_STB : in std_logic; - A8_B : out std_logic; - A9_B : out std_logic; - A10_B : out std_logic; + B8 : out std_logic; + B9 : out std_logic; + B10 : out std_logic; NOE : out std_logic); end component; @@ -151,9 +149,9 @@ begin CLK=>extclk, NIO_SEL=>nio_sel, NIO_STB=>nio_stb, - A8_B=>b8, - A9_B=>b9, - A10_B=>b10, + B8=>b8, + B9=>b9, + B10=>b10, NOE=>noe);