inited signal added to cpld

.gitignore

@@ -160,7 +160,6 @@ VHDL/appleiisd_html*
 VHDL/*.vhf
 VHDL/*.dhp
 VHDL/*.gyd
-VHDL/*.jed
 VHDL/*.mfd
 VHDL/*.pnx
 VHDL/*.rpt

VHDL/AppleIISd.vhd

@@ -97,6 +97,7 @@ architecture Behavioral of AppleIISd is
 	signal spidatain: std_logic_vector (7 downto 0);
 	signal spidataout: std_logic_vector (7 downto 0);
 	signal spiint: std_logic;	-- spi interrupt state
+    signal inited: std_logic;   -- card initialized
 	
 	-- spi register flags
 	signal tc: std_logic;		-- transmission complete; cleared on spi data read
@@ -324,7 +325,7 @@ begin
 	-- cpu read
 	cpu_read: process (is_read, addr, 
 			spidatain, tc, ier, bsy, frx, tmo, ece, cpol, cpha, divisor,
-			slavesel, slaveinten, wp, card)
+			slavesel, slaveinten, wp, card, inited)
 	begin
 		if (is_read = '1') then 
 			case addr is
@@ -348,7 +349,7 @@ begin
 					int_dout(4) <= slaveinten;
 					int_dout(5) <= wp;
 					int_dout(6) <= card;
-					int_dout(7) <= '0';
+					int_dout(7) <= inited;
 				when others => 
 					int_dout <= (others => '0');
 			end case;
@@ -358,7 +359,7 @@ begin
 	end process;
 
 	-- cpu write 
-	cpu_write: process(reset, selected, nrw, addr, int_din)
+	cpu_write: process(reset, selected, nrw, addr, int_din, inited)
 	begin
 		if (reset = '1') then
 			cpha <= '0';
@@ -369,6 +370,7 @@ begin
 			ier <= '0';
 			slavesel <= '1';
 			slaveinten <= '0';
+            inited <= '0';
 			divisor <= (others => '0');
 		elsif (falling_edge(selected) and nrw = '0') then
 		--elsif (falling_edge(cpu_phi2) and selected='1' and nrw='0') then
@@ -389,6 +391,7 @@ begin
 				when "11" =>		-- write slave select / slave interrupt enable
 					slavesel <= int_din(0);
 					slaveinten <= int_din(4);
+                    inited <= int_din(7);
 				when others =>
 			end case;
 		end if;