Apple-2-HW
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AppleIISd
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signal rename and pinning

This commit is contained in:
freitz85 2017-07-05 23:28:27 +02:00
parent f851a50f65
commit 21acf3ac24
4 changed files with 98 additions and 75 deletions
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1
.gitignore vendored
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@ -168,5 +168,6 @@ VHDL/*.untf
VHDL/*.vm6
VHDL/*.xml
VHDL/*.err
VHDL/*.lfp
Hardware/SD_A2\.b\$1

44
VHDL/AddressDecoder.sch
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@ -21,6 +21,8 @@ BEGIN SCHEMATIC
SIGNAL NIO_STB
SIGNAL XLXN_38
SIGNAL XLXN_46
SIGNAL XLXN_47
SIGNAL NDEV_SEL
PORT Input A10
PORT Input A9
PORT Input A8
@ -31,6 +33,7 @@ BEGIN SCHEMATIC
PORT Output NOE
PORT Input NIO_SEL
PORT Input NIO_STB
PORT Input NDEV_SEL
BEGIN BLOCKDEF fdrs
TIMESTAMP 2001 3 9 11 23 0
LINE N 0 -128 64 -128
@ -83,12 +86,23 @@ BEGIN SCHEMATIC
LINE N 0 -128 64 -128
LINE N 0 -64 64 -64
END BLOCKDEF
BEGIN BLOCKDEF nand2
TIMESTAMP 2001 3 9 11 23 50
LINE N 0 -64 64 -64
LINE N 0 -128 64 -128
LINE N 256 -96 216 -96
CIRCLE N 192 -108 216 -84
LINE N 64 -48 64 -144
LINE N 64 -144 144 -144
LINE N 144 -48 64 -48
ARC N 96 -144 192 -48 144 -48 144 -144
END BLOCKDEF
BEGIN BLOCK XLXI_16 fdrs
PIN C CLK
PIN D XLXN_14
PIN R XLXN_10
PIN S XLXN_46
PIN Q XLXN_29
PIN Q XLXN_47
END BLOCK
BEGIN BLOCK XLXI_17 vcc
PIN P XLXN_14
@ -112,10 +126,6 @@ BEGIN SCHEMATIC
PIN I NIO_SEL
PIN O XLXN_46
END BLOCK
BEGIN BLOCK XLXI_29 inv
PIN I XLXN_29
PIN O NOE
END BLOCK
BEGIN BLOCK XLXI_30 and4
PIN I0 A8
PIN I1 A9
@ -127,6 +137,11 @@ BEGIN SCHEMATIC
PIN I NIO_STB
PIN O XLXN_38
END BLOCK
BEGIN BLOCK XLXI_32 nand2
PIN I0 XLXN_47
PIN I1 NDEV_SEL
PIN O NOE
END BLOCK
END NETLIST
BEGIN SHEET 1 3520 2720
BEGIN BRANCH A10
@ -168,10 +183,7 @@ BEGIN SCHEMATIC
WIRE 1360 1248 1664 1248
END BRANCH
BEGIN BRANCH NOE
WIRE 1616 512 1664 512
END BRANCH
BEGIN BRANCH XLXN_29
WIRE 1376 512 1392 512
WIRE 1680 336 1696 336
END BRANCH
BEGIN BRANCH NIO_SEL
WIRE 320 368 352 368
@ -210,13 +222,23 @@ BEGIN SCHEMATIC
WIRE 992 368 992 416
END BRANCH
INSTANCE XLXI_16 992 768 R0
INSTANCE XLXI_29 1392 544 R0
IOMARKER 1664 512 NOE R0 28
INSTANCE XLXI_18 1088 1056 R0
INSTANCE XLXI_19 1088 1200 R0
INSTANCE XLXI_20 1088 1344 R0
IOMARKER 1664 960 B10 R0 28
IOMARKER 1664 1104 B9 R0 28
IOMARKER 1664 1248 B8 R0 28
INSTANCE XLXI_32 1424 432 R0
BEGIN BRANCH XLXN_47
WIRE 1376 512 1392 512
WIRE 1392 368 1424 368
WIRE 1392 368 1392 512
END BRANCH
IOMARKER 1696 336 NOE R0 28
BEGIN BRANCH NDEV_SEL
WIRE 320 304 1408 304
WIRE 1408 304 1424 304
END BRANCH
IOMARKER 320 304 NDEV_SEL R180 28
END SHEET
END SCHEMATIC

52
VHDL/AppleIISd.ucf
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@ -1,39 +1,39 @@
#net "diag" loc="P29";
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "a10" LOC = "P38" ;
NET "b10" LOC = "P27" ;
NET "a8" LOC = "P36" ;
NET "b8" LOC = "P25" ;
NET "a9" LOC = "P37" ;
NET "b9" LOC = "P26" ;
NET "cpu_a<0>" LOC = "P22" ;
NET "cpu_a<1>" LOC = "P24" ;
NET "cpu_d<0>" LOC = "P2" ;
NET "cpu_d<1>" LOC = "P3" ;
NET "cpu_d<2>" LOC = "P4" ;
NET "cpu_d<3>" LOC = "P8" ;
NET "cpu_d<4>" LOC = "P9" ;
NET "cpu_d<5>" LOC = "P11" ;
NET "cpu_d<6>" LOC = "P12" ;
NET "cpu_d<7>" LOC = "P13" ;
NET "cpu_Nphi2" LOC = "P5" ;
NET "cpu_Nres" LOC = "P19" ;
NET "cpu_rnw" LOC = "P7" ;
NET "extclk" LOC = "P6" ;
NET "nio_sel" LOC = "P40" ;
NET "nio_stb" LOC = "P43" ;
NET "addr<0>" LOC = "P19" ;
NET "addr<1>" LOC = "P18" ;
NET "b10" LOC = "P22" ;
NET "b8" LOC = "P26" ;
NET "b9" LOC = "P27" ;
NET "card" LOC = "P33" ;
NET "data<0>" LOC = "P3" ;
NET "data<1>" LOC = "P5" ;
NET "data<2>" LOC = "P4" ;
NET "data<3>" LOC = "P6" ;
NET "data<4>" LOC = "P7" ;
NET "data<5>" LOC = "P9" ;
NET "data<6>" LOC = "P11" ;
NET "data<7>" LOC = "P13" ;
NET "extclk" LOC = "P42" ;
NET "led" LOC = "P29" ;
NET "Ncs2" LOC = "P18" ;
NET "ng" LOC = "P20" ;
NET "noe" LOC = "P14" ;
NET "spi_int" LOC = "P42" ;
NET "spi_miso" LOC = "P44" ;
NET "ndev_sel" LOC = "P24" ;
NET "ng" LOC = "P12" ;
NET "nio_sel" LOC = "P14" ;
NET "nio_stb" LOC = "P40" ;
NET "nirq" LOC = "P2" ;
NET "noe" LOC = "P25" ;
NET "nphi2" LOC = "P44" ;
NET "nreset" LOC = "P20" ;
NET "nrw" LOC = "P1" ;
NET "spi_miso" LOC = "P43" ;
NET "spi_mosi" LOC = "P35" ;
NET "spi_Nsel" LOC = "P28" ;
NET "spi_sclk" LOC = "P34" ;
NET "wp" LOC = "P39" ;
#PACE: Start of PACE Area Constraints

76
VHDL/AppleIISd.vhd
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@ -46,20 +46,21 @@ use AddressDecoder.ALL;
--use UNISIM.VComponents.all;
entity AppleIISd is
Port ( cpu_d : inout STD_LOGIC_VECTOR (7 downto 0);
cpu_rnw : in STD_LOGIC;
cpu_Nirq : out STD_LOGIC;
cpu_Nres : in STD_LOGIC;
cpu_a : in STD_LOGIC_VECTOR (1 downto 0);
cpu_Nphi2 : in STD_LOGIC;
Ncs2 : in STD_LOGIC;
Port ( data : inout STD_LOGIC_VECTOR (7 downto 0);
nrw : in STD_LOGIC;
nirq : out STD_LOGIC;
nreset : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (1 downto 0);
nphi2 : in STD_LOGIC;
ndev_sel : in STD_LOGIC;
extclk : in STD_LOGIC;
spi_miso: in std_logic;
spi_mosi : out STD_LOGIC;
spi_sclk : out STD_LOGIC;
spi_Nsel : out STD_LOGIC;
spi_int : in STD_LOGIC;
led : out std_logic;
wp : in STD_LOGIC;
card : in STD_LOGIC;
led : out STD_LOGIC;
a8 : in std_logic;
a9 : in std_logic;
@ -111,7 +112,6 @@ architecture Behavioral of AppleIISd is
signal slavesel: std_logic; -- slave select output (0=selected)
signal slaveinten: std_logic; -- slave interrupt enable (1=enabled)
signal slaveint: std_logic; -- slave interrupt inputs
--------------------------
-- helper signals
@ -133,6 +133,7 @@ architecture Behavioral of AppleIISd is
A9 : in std_logic;
A10 : in std_logic;
CLK : in std_logic;
NDEV_SEL : in std_logic;
NIO_SEL : in std_logic;
NIO_STB : in std_logic;
B8 : out std_logic;
@ -147,6 +148,7 @@ begin
A9=>a9,
A10=>a10,
CLK=>extclk,
NDEV_SEL=>ndev_sel,
NIO_SEL=>nio_sel,
NIO_STB=>nio_stb,
B8=>b8,
@ -156,7 +158,7 @@ begin
led <= not (bsy or not slavesel); --'0'; --shifting2; --shiftdone; --shiftcnt(2);
ng <= Ncs2 and nio_sel and nio_stb;
ng <= ndev_sel and nio_sel and nio_stb;
--------------------------
bsy <= start_shifting or shifting2;
@ -246,13 +248,13 @@ begin
-- shift operation enable
shiften: process(reset, selected, cpu_rnw, cpu_a, frx, shiftdone)
shiften: process(reset, selected, nrw, addr, frx, shiftdone)
begin
-- start shifting
if (reset='1' or shiftdone='1') then
start_shifting <= '0';
elsif (falling_edge(selected) and cpu_a="00" and (frx='1' or cpu_rnw='0')) then
-- access to register 00, either write (cpu_rnw=0) or fast receive bit set (frx)
elsif (falling_edge(selected) and addr="00" and (frx='1' or nrw='0')) then
-- access to register 00, either write (nrw=0) or fast receive bit set (frx)
-- then both types of access (write but also read)
start_shifting <= '1';
end if;
@ -261,7 +263,7 @@ begin
--------------------------
-- spiclk - spi clock generation
-- spiclk is still 2 times the freq. than sclk
clksrc <= cpu_Nphi2 when (ece = '0') else extclk;
clksrc <= nphi2 when (ece = '0') else extclk;
-- is a pulse signal to allow for divisor==0
--shiftclk <= clksrc when divcnt = "000000" else '0';
@ -284,23 +286,21 @@ begin
--------------------------
-- interrupt generation
int_out <= spiint
or (slaveint and slaveinten);
int_out <= spiint and slaveinten;
--------------------------
-- interface section
-- inputs
reset <= not (cpu_Nres);
selected <= not(Ncs2); -- and cpu_phi2;
is_read <= selected and cpu_Nphi2 and cpu_rnw;
int_din <= cpu_d;
slaveint <= not(spi_int); -- active low interrupt inputs
reset <= not (nreset);
selected <= not(ndev_sel); -- and cpu_phi2;
is_read <= selected and nphi2 and nrw;
int_din <= data;
int_miso <= (spi_miso and not slavesel);
-- outputs
cpu_d <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
cpu_Nirq <= '0' when (int_out='1') else 'Z'; -- wired-or
data <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
nirq <= '0' when (int_out='1') else 'Z'; -- wired-or
spi_sclk <= int_sclk;
spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state
spi_Nsel <= slavesel;
@ -309,9 +309,9 @@ begin
begin
if (shiftdone = '1') then
tc <= '1';
elsif (falling_edge(selected) and cpu_a="00"
--elsif (falling_edge(cpu_phi2) and selected='1' and cpu_a="00"
--and cpu_rnw='1' -- both reads _and_ writes clear the interrupt
elsif (falling_edge(selected) and addr="00"
--elsif (falling_edge(cpu_phi2) and selected='1' and addr="00"
--and nrw='1' -- both reads _and_ writes clear the interrupt
) then
tc <= '0';
end if;
@ -322,12 +322,12 @@ begin
--------------------------
-- cpu register section
-- cpu read
cpu_read: process (is_read, cpu_a,
cpu_read: process (is_read, addr,
spidatain, tc, ier, bsy, frx, tmo, ece, cpol, cpha, divisor,
slavesel, slaveint, slaveinten)
slavesel, slaveinten, wp, card)
begin
if (is_read = '1') then
case cpu_a is
case addr is
when "00" => -- read SPI data in
int_dout <= spidatain;
when "01" => -- read status register
@ -341,14 +341,14 @@ begin
int_dout(7) <= tc;
when "10" => -- read sclk divisor
int_dout(DIV_WIDTH-1 downto 0) <= divisor;
int_dout(3) <= '0';
int_dout(4) <= slaveint;
int_dout(7 downto 5) <= (others => '0');
int_dout(7 downto 3) <= (others => '0');
when "11" => -- read slave select / slave interrupt state
int_dout(0) <= slavesel;
int_dout(3 downto 1) <= (others => '0');
int_dout(4) <= slaveinten;
int_dout(7 downto 5) <= (others => '0');
int_dout(5) <= wp;
int_dout(6) <= card;
int_dout(7) <= '0';
when others =>
int_dout <= (others => '0');
end case;
@ -358,7 +358,7 @@ begin
end process;
-- cpu write
cpu_write: process(reset, selected, cpu_rnw, cpu_a, int_din)
cpu_write: process(reset, selected, nrw, addr, int_din)
begin
if (reset = '1') then
cpha <= '0';
@ -370,9 +370,9 @@ begin
slavesel <= '1';
slaveinten <= '0';
divisor <= (others => '0');
elsif (falling_edge(selected) and cpu_rnw = '0') then
--elsif (falling_edge(cpu_phi2) and selected='1' and cpu_rnw='0') then
case cpu_a is
elsif (falling_edge(selected) and nrw = '0') then
--elsif (falling_edge(cpu_phi2) and selected='1' and nrw='0') then
case addr is
when "00" => -- write SPI data out (see other process above)
spidataout <= int_din;
when "01" => -- write status register