Apple-2-HW/AppleIISd
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Test bench worst and best case timings

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freitz85 2017-10-10 21:22:18 +02:00
parent 8a6e7e647e
commit 2e4ebd9ac0
5 changed files with 47 additions and 40 deletions
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0
VHDL/IO.tim → VHDL/AddressDecoder.schlog
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40
VHDL/AppleIISd.vhd
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@ -39,10 +39,10 @@ Port (
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0);
is_read : in STD_LOGIC;
reset : in STD_LOGIC;
nreset : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (1 downto 0);
phi0 : in STD_LOGIC;
selected : in STD_LOGIC;
ndev_sel : in STD_LOGIC;
clk : in STD_LOGIC;
miso: in std_logic;
mosi : out STD_LOGIC;
@ -105,9 +105,9 @@ begin
end if;
end process;
process(shiftcnt, reset, shiftclk)
process(shiftcnt, nreset, shiftclk)
begin
if (reset = '1') then
if (nreset = '0') then
shiftdone <= '0';
elsif (rising_edge(shiftclk)) then
if (shiftcnt = "1111") then
@ -118,9 +118,9 @@ begin
end if;
end process;
process(reset, shifting2, shiftcnt, shiftclk)
process(nreset, shifting2, shiftcnt, shiftclk)
begin
if (reset='1') then
if (nreset = '0') then
shiftcnt <= (others => '0');
elsif (rising_edge(shiftclk)) then
if (shifting2 = '1') then
@ -132,9 +132,9 @@ begin
end if;
end process;
inproc: process(reset, shifting2, shiftcnt, shiftclk, spidatain, miso)
inproc: process(nreset, shifting2, shiftcnt, shiftclk, spidatain, miso)
begin
if (reset='1') then
if (nreset = '0') then
spidatain <= (others => '0');
elsif (rising_edge(shiftclk)) then
if (shifting2 = '1' and shiftcnt(0) = '1') then
@ -145,9 +145,9 @@ begin
end if;
end process;
outproc: process(reset, shifting2, spidataout, shiftcnt, shiftclk)
outproc: process(nreset, shifting2, spidataout, shiftcnt, shiftclk)
begin
if (reset='1') then
if (nreset = '0') then
mosi <= '1';
sclk <= '0';
else
@ -177,12 +177,12 @@ begin
-- shift operation enable
shiften: process(reset, selected, is_read, addr, frx, shiftdone)
shiften: process(nreset, ndev_sel, is_read, addr, frx, shiftdone)
begin
-- start shifting
if (reset='1' or shiftdone='1') then
if (nreset = '0' or shiftdone = '1') then
start_shifting <= '0';
elsif (falling_edge(selected) and addr="00" and (frx='1' or is_read='0')) then
elsif (rising_edge(ndev_sel) and addr="00" and (frx='1' or is_read='0')) then
-- access to register 00, either write (is_read=0) or fast receive bit set (frx)
-- then both types of access (write but also read)
start_shifting <= '1';
@ -198,9 +198,9 @@ begin
--shiftclk <= clksrc when divcnt = "000000" else '0';
shiftclk <= clksrc when bsy = '1' else '0';
-- clkgen: process(reset, divisor, clksrc)
-- clkgen: process(nreset, divisor, clksrc)
-- begin
-- if (reset='1') then
-- if (nreset = '0') then
-- divcnt <= divisor;
-- elsif (falling_edge(clksrc)) then
-- if (shiftclk = '1') then
@ -219,11 +219,11 @@ begin
-- outputs
nsel <= slavesel;
tc_proc: process (selected, shiftdone)
tc_proc: process (ndev_sel, shiftdone)
begin
if (shiftdone = '1') then
tc <= '1';
elsif (falling_edge(selected) and addr="00") then
elsif (rising_edge(ndev_sel) and addr="00") then
tc <= '0';
end if;
end process;
@ -261,9 +261,9 @@ begin
end process;
-- cpu write
cpu_write: process(reset, selected, is_read, addr, data_in, card, inited)
cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card, inited)
begin
if (reset = '1') then
if (nreset = '0') then
ece <= '0';
frx <= '0';
slavesel <= '1';
@ -272,7 +272,7 @@ begin
inited <= '0';
elsif (card = '1') then
inited <= '0';
elsif (falling_edge(selected) and is_read = '0') then
elsif (rising_edge(ndev_sel) and is_read = '0') then
case addr is
when "00" => -- write SPI data out (see other process above)
spidataout <= data_in;

14
VHDL/AppleIISd.xise
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@ -21,18 +21,14 @@
</file>
<file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="IO.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="IO_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
@ -152,8 +148,8 @@
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/IO_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.IO_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/IO_Test/uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work." xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
@ -163,7 +159,7 @@
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.IO_Test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work." xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>

8
VHDL/IO.vhd
View File

@ -77,10 +77,10 @@ Port (
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
is_read : in std_logic;
reset : in std_logic;
nreset : in std_logic;
addr : in std_logic_vector (1 downto 0);
phi0 : in std_logic;
selected : in std_logic;
ndev_sel : in std_logic;
clk : in std_logic;
miso: in std_logic;
mosi : out std_logic;
@ -115,10 +115,10 @@ begin
data_in => data_in,
data_out => data_out,
is_read => rnw_int,
reset => not NRESET,
nreset => NRESET,
addr => addr_low_int,
phi0 => PHI0,
selected => not ndev_sel_int,
ndev_sel => ndev_sel_int,
clk => CLK,
miso => miso_int,
mosi => MOSI,

25
VHDL/IO_Test.vhd
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@ -103,6 +103,16 @@ ARCHITECTURE behavior OF IO_Test IS
-- Clock period definitions
constant CLK_period : time := 142 ns;
-- Bus timings
-- worst case
constant ADD_valid : time := 300 ns; -- II+
constant DATA_valid : time := 200 ns; -- II+
constant ADD_hold : time := 15 ns; -- IIgs
--best case
--constant ADD_valid : time := 100 ns; -- IIgs
--constant DATA_valid : time := 30 ns; -- IIgs
--constant ADD_hold : time := 15 ns; -- IIgs
BEGIN
@ -169,8 +179,9 @@ BEGIN
-- read reg 0
DATA <= (others => 'Z');
ADD_LOW <= (others => 'U');
wait until falling_edge(PHI0);
wait for 300 ns;
wait for ADD_valid;
ADD_LOW <= (others => '0');
RNW <= '1';
DATA <= (others => 'U');
@ -179,12 +190,12 @@ BEGIN
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for 15 ns;
wait for ADD_hold;
ADD_LOW <= (others => 'U');
-- read reg 3
wait until falling_edge(PHI0);
wait for 300 ns;
wait for ADD_valid;
ADD_LOW <= (others => '1');
RNW <= '1';
DATA <= (others => 'U');
@ -193,23 +204,23 @@ BEGIN
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for 15 ns;
wait for ADD_hold;
ADD_LOW <= (others => 'U');
-- send data
wait until falling_edge(PHI0);
wait for 300 ns;
wait for ADD_valid;
ADD_LOW <= (others => '0');
RNW <= '0';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait for 200 ns;
wait for DATA_valid;
DATA <= (others => '0');
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for 15 ns;
wait for ADD_hold;
--wait for CLK_period;
ADD_LOW <= (others => 'U');
RNW <= '1';