diff --git a/.gitignore b/.gitignore
index aa04e65..58e3919 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,97 @@
-#Gitignore for files generated by Xilinx ISE
+#ignore OS noise
+
+Thumbs.db
+.DS_Store
+
+# Ignore list for Eagle, a PCB layout tool
+
+# Backup files
+*.s#?
+*.b#?
+*.l#?
+
+# Eagle project file
+# It contains a serial number and references to the file structure
+# on your computer.
+# comment the following line if you want to have your project file included.
+eagle.epf
+
+# Autorouter files
+*.pro
+*.job
+
+# CAM files
+*.$$$
+*.cmp
+*.ly2
+*.l15
+*.sol
+*.plc
+*.stc
+*.sts
+*.crc
+*.crs
+
+*.dri
+*.drl
+*.gpi
+*.pls
+
+*.drd
+*.drd.*
+
+*.info
+
+*.eps
+
+# file locks introduced since 7.x
+*.lck
+
+# Xilinx ISE
+# intermediate build files
+*.bgn
+*.bit
+*.bld
+*.cmd_log
+*.drc
+*.ll
+*.lso
+*.msd
+*.msk
+*.ncd
+*.ngc
+*.ngd
+*.ngr
+*.pad
+*.par
+*.pcf
+*.prj
+*.ptwx
+*.rbb
+*.rbd
+*.stx
+*.syr
+*.twr
+*.twx
+*.unroutes
+*.ut
+*.xpi
+*.xst
+*_bitgen.xwbt
+*_envsettings.html
+*_map.map
+*_map.mrp
+*_map.ngm
+*_map.xrpt
+*_ngdbuild.xrpt
+*_pad.csv
+*_pad.txt
+*_par.xrpt
+*_summary.html
+*_summary.xml
+*_usage.xml
+*_xst.xrpt
+
 
 *.log
 *.svf
@@ -38,7 +131,26 @@ impact_impact.xwbt
 spi6502b_html*/
 __projnav*/
 
-#ignore OS noise
+# iMPACT generated files
+_impactbatch.log
+impact.xsl
+impact_impact.xwbt
+ise_impact.cmd
+webtalk_impact.xml
 
-Thumbs.db
-.DS_Store
+# Core Generator generated files
+xaw2verilog.log
+
+# project-wide generated files
+*.gise
+par_usage_statistics.html
+usage_statistics_webtalk.html
+webtalk.log
+webtalk_pn.xml
+
+# generated folders
+iseconfig/
+xlnx_auto_0_xdb/
+xst/
+_ngo/
+_xmsgs/
diff --git a/AppleIISd.lst.txt b/AppleIISd.lst.txt
new file mode 100644
index 0000000..15c8cda
--- /dev/null
+++ b/AppleIISd.lst.txt
@@ -0,0 +1,670 @@
+                1    ********************************
+                2    *
+                3    * Initialize SD card
+                4    *
+                5    ********************************
+                6    
+                7             XC               
+                8             ORG   $8000      
+                9    
+                10   SLOT     =     $04        ; slot 4
+                11   DATA     =     $C0C0      ; slot 4
+                12   CTRL     =     DATA+1     
+                13   DIV      =     DATA+2     
+                14   SS       =     DATA+3     
+                15   R30      =     $0478      
+                16   R31      =     $04F8      
+                17   R32      =     $0578      
+                18   R33      =     $05F8      
+                19   CMDLO    =     $FA        
+                20   CMDHI    =     $FB        
+                21   *
+                22   FROM     =     $FA        ; + $fb
+                23   TO       =     $FC        ; + $fd
+                24   SIZE     =     $FE        ; + $ff
+                25   *
+                26   SSNONE   =     $0F        
+                27   SS0      =     $0E        
+                28   TC       =     $80        
+                29   DUMMY    =     $FF        
+                30   
+                31   
+                32   ********************************
+                33   *
+                34   * Install SD card driver
+                35   *
+                36   ********************************
+                37   
+                38   * make room for the driver
+                39   
+8000: A9 04     40   GETBUF   LDA   #4         ; allocate 4 pages
+8002: 20 F5 BE  41            JSR   $BEF5      ; call GETBUFR
+8005: B0 59     42            BCS   ERROR      ; did an error occur?
+8007: 85 FD     43            STA   TO+1       ; store buffer addr msb
+8009: 8D 84 80  44            STA   BUFMSB     
+800C: 64 FC     45            STZ   TO         ; store buffer addr lsb
+800E: 9C 85 80  46            STZ   BUFLSB     
+8011: A9 80     47            LDA   #>DRIVER1  
+8013: 85 FB     48            STA   FROM+1     ; store from addr msb
+8015: A9 8C     49            LDA   #<DRIVER1  
+8017: 85 FA     50            STA   FROM       ; store from addr lsb
+8019: A9 02     51            LDA   #>DRIVEND-DRIVER 
+801B: 85 FF     52            STA   SIZE+1     ; store size msb
+801D: A9 E4     53            LDA   #<DRIVEND-DRIVER 
+801F: 85 FE     54            STA   SIZE       ; store size lsb
+                55   
+                56   * move driver to new address
+                57   
+8021: A6 FF     58   MOVEUP   LDX   SIZE+1     ; the last byte must be
+8023: 18        59            CLC              ; moved first, start at 
+                              ===== Page 2 =====
+ 
+8024: 8A        60            TXA              ; the final pages of FROM
+8025: 65 FB     61            ADC   FROM+1     ; and TO
+8027: 85 FB     62            STA   FROM+1     
+8029: 18        63            CLC              
+802A: 8A        64            TXA              
+802B: 65 FD     65            ADC   TO+1       
+802D: 85 FD     66            STA   TO+1       
+802F: E8        67            INX              ; allows the use of
+8030: A4 FE     68            LDY   SIZE       ; BNE after DEX below
+8032: F0 0E     69            BEQ   MU3        
+8034: 88        70            DEY              ; move bytes on the last
+8035: F0 07     71            BEQ   MU2        ; page first
+8037: B1 FA     72   MU1      LDA   (FROM),Y   
+8039: 91 FC     73            STA   (TO),Y     
+803B: 88        74            DEY              
+803C: D0 F9     75            BNE   MU1        
+803E: B1 FA     76   MU2      LDA   (FROM),Y   ; handle Y=0 separately
+8040: 91 FC     77            STA   (TO),Y     
+8042: 88        78   MU3      DEY              
+8043: C6 FB     79            DEC   FROM+1     ; move the next page
+8045: C6 FD     80            DEC   TO+1       ; (if any)
+8047: CA        81            DEX              
+8048: D0 ED     82            BNE   MU1        
+                83   
+                84   * see if slot 4 has a driver already
+                85   
+804A: AE 31 BF  86   INSTALL  LDX   $BF31      ; get devcnt
+804D: BD 32 BF  87   INSLP    LDA   $BF32,X    ; get a devnum
+8050: 29 70     88            AND   #$70       ; isolate slot
+8052: C9 40     89            CMP   #$40       ; slot 4?
+8054: F0 2D     90            BEQ   INSOUT     ; yes, skip it
+8056: CA        91            DEX              
+8057: 10 F4     92            BPL   INSLP      ; keep up the search
+                93   
+                94   * restore the devnum to the list
+                95   
+8059: AE 31 BF  96            LDX   $BF31      ; get devcnt again
+805C: E0 0D     97            CPX   #$0D       device table full?
+805E: D0 03     98            BNE   INSLP2     
+                99   
+8060: 4C 83 80  100  ERROR    JMP   INSOUT      ; do something!
+                101  
+8063: BD 31 BF  102  INSLP2   LDA   $BF32-1,X  ; move all entries down
+8066: 9D 32 BF  103           STA   $BF32,X    ; to make room at front
+8069: CA        104           DEX              ; for a new entry
+806A: D0 F7     105           BNE   INSLP2     
+806C: A9 44     106           LDA   #$44       
+806E: 8D 32 BF  107           STA   $BF32      ; slot 4, drive 1 at top of list
+8071: EE 31 BF  108           INC   $BF31      ; update devcnt
+                109  
+                110  * now insert the device driver vector
+                111  
+8074: AD 85 80  112           LDA   BUFLSB     
+8077: 8D 18 BF  113           STA   $BF18      
+807A: AD 84 80  114           LDA   BUFMSB     
+807D: 8D 19 BF  115           STA   $BF19      
+8080: 20 26 96  116           JSR   INIT       ; init card 
+                              ===== Page 3 =====
+ 
+                117  
+8083: 60        118  INSOUT   RTS              
+                119  
+8084: 00        120  BUFMSB   DB    #0         
+8085: 00        121  BUFLSB   DB    #0         
+                122  
+                123  ********************************
+                124  *
+                125  * Jump table
+                126  *
+                127  ********************************
+                128  
+8086: 2C FF CF  129           BIT   $CFFF      
+8089: 4C 26 96  130           JMP   INIT       
+                131  
+                132  DRIVER1  =     *          
+                133           ORG   $9600      
+                134  
+9600: D8        135  DRIVER   CLD              
+9601: 2C FF CF  136           BIT   $CFFF      
+9604: A5 42     137           LDA   $42        
+9606: C9 00     138           CMP   #$00       
+9608: F0 10     139           BEQ   :STATUS    
+960A: C9 01     140           CMP   #$01       
+960C: F0 0F     141           BEQ   :READ      
+960E: C9 02     142           CMP   #$02       
+9610: F0 0E     143           BEQ   :WRITE     
+9612: C9 03     144           CMP   #$03       
+9614: F0 0D     145           BEQ   :FORMAT    
+9616: 38        146           SEC              ; unknown command
+9617: A9 01     147           LDA   #$01       
+9619: 60        148           RTS              
+                149  
+961A: 4C 5C 97  150  :STATUS  JMP   STATUS     
+961D: 4C 64 97  151  :READ    JMP   READ       
+9620: 4C 0F 98  152  :WRITE   JMP   WRITE      
+9623: 4C B6 98  153  :FORMAT  JMP   FORMAT     
+                154  
+                155  
+                156  ********************************
+                157  *
+                158  * Initialize SD card
+                159  *
+                160  * C Clear - No error
+                161  *   Set   - Error
+                162  * A $00   - No error
+                163  *   $27   - I/O error - Init failed
+                164  *   $28   - No card inserted
+                165  *
+                166  ********************************
+                167  
+9626: D8        168  INIT     CLD              
+9627: A9 03     169           LDA   #$03       ; set SPI mode 3
+9629: 8D C1 C0  170           STA   CTRL       
+962C: A9 0F     171           LDA   #SSNONE    
+962E: 8D C3 C0  172           STA   SS         
+9631: A9 07     173           LDA   #7          
+                              ===== Page 4 =====
+ 
+9633: 8D C2 C0  174           STA   DIV        
+9636: A2 0A     175           LDX   #10        
+9638: A9 FF     176           LDA   #DUMMY     
+                177  
+963A: 8D C0 C0  178  :LOOP    STA   DATA       
+963D: 2C C1 C0  179  :WAIT    BIT   CTRL       
+9640: 10 FB     180           BPL   :WAIT      
+9642: CA        181           DEX              
+9643: D0 F5     182           BNE   :LOOP      ; do 10 times
+9645: A9 0E     183           LDA   #SS0       ; set CS low
+9647: 8D C3 C0  184           STA   SS         
+                185  
+964A: A9 BA     186           LDA   #<CMD0     ; send CMD0
+964C: 85 FA     187           STA   CMDLO      
+964E: A9 98     188           LDA   #>CMD0     
+9650: 85 FB     189           STA   CMDHI      
+9652: 20 FD 96  190           JSR   CMD        
+9655: 20 0F 97  191           JSR   GETR1      ; get response
+9658: C9 01     192           CMP   #$01       
+965A: D0 39     193           BNE   ERROR1     ; error!
+                194  
+965C: A9 C6     195           LDA   #<CMD8     ; send CMD8
+965E: 85 FA     196           STA   CMDLO      
+9660: A9 98     197           LDA   #>CMD8     
+9662: 85 FB     198           STA   CMDHI      
+9664: 20 FD 96  199           JSR   CMD        
+9667: 20 2C 97  200           JSR   GETR3      
+966A: C9 01     201           CMP   #$01       
+966C: D0 2A     202           BNE   SDV1       ; may be SD Ver. 1
+                203  
+                204  * check for $01aa match!
+966E: A9 D2     205  SDV2     LDA   #<CMD55    
+9670: 85 FA     206           STA   CMDLO      
+9672: A9 98     207           LDA   #>CMD55    
+9674: 85 FB     208           STA   CMDHI      
+9676: 20 FD 96  209           JSR   CMD        
+9679: 20 0F 97  210           JSR   GETR1      
+967C: A9 D8     211           LDA   #<ACMD41_40 
+967E: 85 FA     212           STA   CMDLO      
+9680: A9 98     213           LDA   #>ACMD41_40 
+9682: 85 FB     214           STA   CMDHI      
+9684: 20 FD 96  215           JSR   CMD        
+9687: 20 0F 97  216           JSR   GETR1      
+968A: C9 01     217           CMP   #$01       
+968C: F0 E0     218           BEQ   SDV2       ; wait for ready
+968E: C9 00     219           CMP   #$00       
+9690: D0 03     220           BNE   ERROR1     ;  error!
+                221  * send CMD58
+                222  * SD Ver. 2 initialized!
+9692: 4C D2 96  223           JMP   BLOCKSZ    
+                224  
+9695: 4C EE 96  225  ERROR1   JMP   IOERROR    ; needed for far jump
+                226  
+9698: A9 D2     227  SDV1     LDA   #<CMD55    
+969A: 85 FA     228           STA   CMDLO      
+969C: A9 98     229           LDA   #>CMD55    
+969E: 85 FB     230           STA   CMDHI       
+                              ===== Page 5 =====
+ 
+96A0: 20 FD 96  231           JSR   CMD        ; ignore response
+96A3: A9 DE     232           LDA   #<ACMD41_0 
+96A5: 85 FA     233           STA   CMDLO      
+96A7: A9 98     234           LDA   #>ACMD41_0 
+96A9: 85 FB     235           STA   CMDHI      
+96AB: 20 FD 96  236           JSR   CMD        
+96AE: 20 0F 97  237           JSR   GETR1      
+96B1: C9 01     238           CMP   #$01       
+96B3: F0 E3     239           BEQ   SDV1       ; wait for ready
+96B5: C9 00     240           CMP   #$00       
+96B7: D0 03     241           BNE   MMC        ; may be MMC card
+                242  * SD Ver. 1 initialized!
+96B9: 4C D2 96  243           JMP   BLOCKSZ    
+                244  
+96BC: A9 C0     245  MMC      LDA   #<CMD1     
+96BE: 85 FA     246           STA   CMDLO      
+96C0: A9 98     247           LDA   #>CMD1     
+96C2: 85 FB     248           STA   CMDHI      
+96C4: 20 FD 96  249  :LOOP    JSR   CMD        
+96C7: 20 0F 97  250           JSR   GETR1      
+96CA: C9 01     251           CMP   #$01       
+96CC: F0 F6     252           BEQ   :LOOP      ; wait for ready
+96CE: C9 00     253           CMP   #$00       
+96D0: D0 1C     254           BNE   IOERROR    ; error!
+                255  * MMC Ver. 3 initialized!
+                256  
+96D2: A9 CC     257  BLOCKSZ  LDA   #<CMD16    
+96D4: 85 FA     258           STA   CMDLO      
+96D6: A9 98     259           LDA   #>CMD16    
+96D8: 85 FB     260           STA   CMDHI      
+96DA: 20 FD 96  261           JSR   CMD        
+96DD: 20 0F 97  262           JSR   GETR1      
+96E0: C9 00     263           CMP   #$00       
+96E2: D0 0A     264           BNE   IOERROR    ; error!
+                265  
+96E4: 18        266  END      CLC              ; all ok
+96E5: A0 00     267           LDY   #0         
+96E7: 90 08     268           BCC   END1       
+96E9: 38        269  CDERROR  SEC              
+96EA: A0 28     270           LDY   #$28       ; no card error
+96EC: B0 03     271           BCS   END1       
+96EE: 38        272  IOERROR  SEC              
+96EF: A0 27     273           LDY   #$27       ; init error
+96F1: A9 0F     274  END1     LDA   #SSNONE    ; deselect card
+96F3: 8D C3 C0  275           STA   SS         
+96F6: A9 00     276           LDA   #0         
+96F8: 8D C2 C0  277           STA   DIV        
+96FB: 98        278           TYA              ; retval in A
+96FC: 60        279           RTS              
+                280  
+                281  
+                282  ********************************
+                283  *
+                284  * Send SD command
+                285  * Call with command in CMDHI and CMDLO
+                286  *
+                287  ******************************** 
+                              ===== Page 6 =====
+ 
+                288  
+96FD: A0 00     289  CMD      LDY   #0         
+96FF: B1 FA     290  :LOOP    LDA   (CMDLO),Y  
+9701: 8D C0 C0  291           STA   DATA       
+9704: 2C C1 C0  292  :WAIT    BIT   CTRL       ; TC is in N
+9707: 10 FB     293           BPL   :WAIT      
+9709: C8        294           INY              
+970A: C0 06     295           CPY   #6         
+970C: 90 F1     296           BCC   :LOOP      
+970E: 60        297           RTS              
+                298  
+                299  
+                300  ********************************
+                301  *
+                302  * Get R1
+                303  * R1 is in A
+                304  *
+                305  ********************************
+                306  
+970F: A9 FF     307  GETR1    LDA   #DUMMY     
+9711: 8D C0 C0  308           STA   DATA       
+9714: 2C C1 C0  309  :WAIT    BIT   CTRL       
+9717: 10 FB     310           BPL   :WAIT      
+9719: AD C0 C0  311           LDA   DATA       ; get response
+971C: 8D 7C 04  312           STA   R30+SLOT   ; save R1
+971F: 29 80     313           AND   #$80       
+9721: D0 EC     314           BNE   GETR1      ; wait for MSB=0
+9723: A9 FF     315           LDA   #DUMMY     
+9725: 8D C0 C0  316           STA   DATA       ; send another dummy
+9728: AD 7C 04  317           LDA   R30+SLOT    ; restore R1
+972B: 60        318           RTS              
+                319  
+                320  
+                321  ********************************
+                322  *
+                323  * Get R3
+                324  * R1 is in A
+                325  * R3 is in scratchpad ram
+                326  *
+                327  ********************************
+                328  
+972C: 20 0F 97  329  GETR3    JSR   GETR1      ; get R1 first
+972F: 48        330           PHA              ; save R1
+9730: 5A        331           PHY              ; save Y
+9731: A0 04     332           LDY   #04        
+9733: A9 FF     333  :LOOP    LDA   #DUMMY     ; send dummy
+9735: 8D C0 C0  334           STA   DATA       
+9738: 2C C1 C0  335  :WAIT    BIT   CTRL       
+973B: 10 FB     336           BPL   :WAIT      
+973D: AD C0 C0  337           LDA   DATA       
+9740: 48        338           PHA              
+9741: 88        339           DEY              
+9742: D0 EF     340           BNE   :LOOP      ; do 4 times
+9744: 68        341           PLA              
+9745: 8D FC 05  342           STA   R33+SLOT   ; save R3
+9748: 68        343           PLA              
+9749: 8D 7C 05  344           STA   R32+SLOT    
+                              ===== Page 7 =====
+ 
+974C: 68        345           PLA              
+974D: 8D FC 04  346           STA   R31+SLOT   
+9750: 68        347           PLA              
+9751: 8D 7C 04  348           STA   R30+SLOT   
+9754: 7A        349           PLY              ; restore Y
+9755: A9 FF     350           LDA   #DUMMY     
+9757: 8D C0 C0  351           STA   DATA       ; send another dummy
+975A: 68        352           PLA              ; restore R1
+975B: 60        353           RTS              
+                354  
+                355  
+                356  ********************************
+                357  *
+                358  * Status request
+                359  * $43    Unt number DSSS000
+                360  * $44-45 Unused
+                361  * $46-47 Unused
+                362  *
+                363  * C Clear - No error
+                364  *   Set   - Error
+                365  * A $00   - No error
+                366  *   $27   - I/O error
+                367  *   $28   - No card inserted / no init
+                368  *   $2B   - Card write protected
+                369  * X       - Blocks avail (low byte)
+                370  * Y       - Blocks avail (high byte)
+                371  *
+                372  ********************************
+                373  
+975C: 18        374  STATUS   CLC              ; no error
+975D: A9 00     375           LDA   #0         
+975F: A2 FF     376           LDX   #$FF       ; 32 MB partition
+9761: A0 FF     377           LDY   #$FF       
+9763: 60        378           RTS              
+                379  
+                380  * TODO: check for card detect and write protect!
+                381  
+                382  
+                383  ********************************
+                384  *
+                385  * Read 512 byte block
+                386  * $43    Unit number DSSS0000
+                387  * $44-45 Address (LO/HI) of buffer
+                388  * $46-47 Block number (LO/HI)
+                389  *
+                390  * C Clear - No error
+                391  *   Set   - Error
+                392  * A $00   - No error
+                393  *   $27   - Bad block number
+                394  *   $28   - No card inserted
+                395  *
+                396  ********************************
+                397  
+                398  * TODO: check for card detect!
+                399  
+9764: A9 0E     400  READ     LDA   #SS0       ; enable /CS
+9766: 8D C3 C0  401           STA   SS          
+                              ===== Page 8 =====
+ 
+                402  
+9769: A5 46     403           LDA   $46        ; store block num
+976B: 8D FC 05  404           STA   R33+SLOT   ; in R30-R33
+976E: A5 47     405           LDA   $47        
+9770: 8D 7C 05  406           STA   R32+SLOT   
+9773: 9C FC 04  407           STZ   R31+SLOT   
+9776: 9C 7C 04  408           STZ   R30+SLOT   
+9779: A0 09     409           LDY   #9         
+977B: 0E FC 05  410  :LOOP    ASL   R33+SLOT   ; mul block num
+977E: 2E 7C 05  411           ROL   R32+SLOT   ; by 512 to get
+9781: 2E FC 04  412           ROL   R31+SLOT   ; real address
+9784: 2E 7C 04  413           ROL   R30+SLOT   
+9787: 88        414           DEY              
+9788: D0 F1     415           BNE   :LOOP      
+                416  
+978A: A9 51     417           LDA   #$51       ; send CMD17
+978C: 8D C0 C0  418           STA   DATA       
+978F: 2C C1 C0  419  :WAIT    BIT   CTRL       
+9792: 10 FB     420           BPL   :WAIT      
+9794: AD 7C 04  421  :ARG     LDA   R30+SLOT   ; get arg from R30 on
+9797: 8D C0 C0  422           STA   DATA       
+979A: 2C C1 C0  423  :WAIT1   BIT   CTRL       
+979D: 10 FB     424           BPL   :WAIT1     
+979F: AD FC 04  425           LDA   R31+SLOT   
+97A2: 8D C0 C0  426           STA   DATA       
+97A5: 2C C1 C0  427  :WAIT11  BIT   CTRL       
+97A8: 10 FB     428           BPL   :WAIT11    
+97AA: AD 7C 05  429           LDA   R32+SLOT   
+97AD: 8D C0 C0  430           STA   DATA       
+97B0: 2C C1 C0  431  :WAIT12  BIT   CTRL       
+97B3: 10 FB     432           BPL   :WAIT12    
+97B5: AD FC 05  433           LDA   R33+SLOT   
+97B8: 8D C0 C0  434           STA   DATA       
+97BB: 2C C1 C0  435  :WAIT13  BIT   CTRL       
+97BE: 10 FB     436           BPL   :WAIT13    
+97C0: A9 FF     437           LDA   #DUMMY     
+97C2: 8D C0 C0  438           STA   DATA       ; dummy crc
+97C5: 2C C1 C0  439  :WAIT2   BIT   CTRL       
+97C8: 10 FB     440           BPL   :WAIT2     
+97CA: A9 FF     441  :GETR1   LDA   #DUMMY     
+97CC: 8D C0 C0  442           STA   DATA       ; get R1
+97CF: 2C C1 C0  443  :WAIT3   BIT   CTRL       
+97D2: 10 FB     444           BPL   :WAIT3     
+97D4: AD C0 C0  445           LDA   DATA       ; get response
+                446  *
+                447  * TODO: check for error!
+                448  *
+97D7: C9 FE     449           CMP   #$FE       
+97D9: D0 EF     450           BNE   :GETR1     ; wait for $FE
+                451  
+97DB: A2 02     452           LDX   #2         ; read data from card
+97DD: A0 00     453  :LOOPX   LDY   #0         
+97DF: A9 FF     454  :LOOPY   LDA   #DUMMY     
+97E1: 8D C0 C0  455           STA   DATA       
+97E4: 2C C1 C0  456  :WAIT4   BIT   CTRL       
+97E7: 10 FB     457           BPL   :WAIT4     
+97E9: AD C0 C0  458           LDA   DATA        
+                              ===== Page 9 =====
+ 
+97EC: 92 44     459           STA   ($44)      
+97EE: E6 44     460           INC   $44        
+97F0: D0 02     461           BNE   :INY       
+97F2: E6 45     462           INC   $45        ; inc msb on page boundary
+97F4: C8        463  :INY     INY              
+97F5: D0 E8     464           BNE   :LOOPY     
+97F7: CA        465           DEX              
+97F8: D0 E3     466           BNE   :LOOPX     
+                467  
+97FA: 20 2C 97  468  :OK      JSR   GETR3      ; read 2 bytes crc
+97FD: A9 0F     469           LDA   #SSNONE    
+97FF: 8D C3 C0  470           STA   SS         ; disable /CS
+9802: 18        471           CLC              ; no error
+9803: A9 00     472           LDA   #$00       
+9805: 60        473           RTS              
+                474  
+9806: A9 0F     475  :ERROR   LDA   #SSNONE    
+9808: 8D C3 C0  476           STA   SS         ; disable /CS
+980B: 38        477           SEC              ; an error occured
+980C: A9 27     478           LDA   #$27       
+980E: 60        479           RTS              
+                480  
+                481  
+                482  ********************************
+                483  *
+                484  * Write 512 byte block
+                485  * $43    Unit number DSSS000
+                486  * $44-45 Address (LO/HI) of buffer
+                487  * $46-47 Block number (LO/HI)
+                488  *
+                489  * C Clear - No error
+                490  *   Set   - Error
+                491  * A $00   - No error
+                492  *   $27   - Bad block number
+                493  *   $28   - No card inserted
+                494  *
+                495  ********************************
+                496  
+                497  * TODO: check for card detect and write protect!
+                498  
+980F: A9 0E     499  WRITE    LDA   #SS0       ; enable /CS
+9811: 8D C3 C0  500           STA   SS         
+                501  
+9814: A5 46     502           LDA   $46        ; store block num
+9816: 8D FC 05  503           STA   R33+SLOT   
+9819: A5 47     504           LDA   $47        
+981B: 8D 7C 05  505           STA   R32+SLOT   
+981E: 9C FC 04  506           STZ   R31+SLOT   
+9821: 9C 7C 04  507           STZ   R30+SLOT   
+9824: A0 09     508           LDY   #9         
+9826: 0E FC 05  509  :LOOP    ASL   R33+SLOT   ; mul block num
+9829: 2E 7C 05  510           ROL   R32+SLOT   ; by 512 to get
+982C: 2E FC 04  511           ROL   R31+SLOT   ; real address
+982F: 2E 7C 04  512           ROL   R30+SLOT   
+9832: 88        513           DEY              
+9833: D0 F1     514           BNE   :LOOP      
+                515   
+                              ===== Page 10 =====
+ 
+9835: A9 58     516           LDA   #$58       ; send CMD24
+9837: 8D C0 C0  517           STA   DATA       
+983A: 2C C1 C0  518  :WAIT    BIT   CTRL       
+983D: 10 FB     519           BPL   :WAIT      
+983F: AD 7C 04  520  :ARG     LDA   R30+SLOT   ; get arg from R30 on
+9842: 8D C0 C0  521           STA   DATA       
+9845: 2C C1 C0  522  :WAIT1   BIT   CTRL       
+9848: 10 FB     523           BPL   :WAIT1     
+984A: AD FC 04  524           LDA   R31+SLOT   
+984D: 8D C0 C0  525           STA   DATA       
+9850: 2C C1 C0  526  :WAIT11  BIT   CTRL       
+9853: 10 FB     527           BPL   :WAIT11    
+9855: AD 7C 05  528           LDA   R32+SLOT   
+9858: 8D C0 C0  529           STA   DATA       
+985B: 2C C1 C0  530  :WAIT12  BIT   CTRL       
+985E: 10 FB     531           BPL   :WAIT12    
+9860: AD FC 05  532           LDA   R33+SLOT   
+9863: 8D C0 C0  533           STA   DATA       
+9866: 2C C1 C0  534  :WAIT13  BIT   CTRL       
+9869: 10 FB     535           BPL   :WAIT13    
+986B: A9 FF     536           LDA   #DUMMY     
+986D: 8D C0 C0  537           STA   DATA       ; dummy crc
+9870: 2C C1 C0  538  :WAIT2   BIT   CTRL       
+9873: 10 FB     539           BPL   :WAIT2     
+9875: A9 FF     540  :GETR1   LDA   #DUMMY     
+9877: 8D C0 C0  541           STA   DATA       ; get R1
+987A: 2C C1 C0  542  :WAIT3   BIT   CTRL       
+987D: 10 FB     543           BPL   :WAIT3     
+987F: AD C0 C0  544           LDA   DATA       : get response
+                545  *
+                546  * TODO: check for error!
+                547  *
+9882: C9 FE     548           CMP   #$FE       
+9884: D0 EF     549           BNE   :GETR1     ; wait for $FE
+9886: A2 02     550           LDX   #2         ; send data to card
+9888: A0 00     551  :LOOPX   LDY   #0         
+988A: B2 44     552  :LOOPY   LDA   ($44)      
+988C: 8D C0 C0  553           STA   DATA       
+988F: 2C C1 C0  554  :WAIT4   BIT   CTRL       
+9892: 10 FB     555           BPL   :WAIT4     
+9894: E6 44     556           INC   $44        
+9896: D0 02     557           BNE   :INY       
+9898: E6 45     558           INC   $45        ; inc msbon page boundary
+989A: C8        559  :INY     INY              
+989B: D0 ED     560           BNE   :LOOPY     
+989D: CA        561           DEX              
+989E: D0 E8     562           BNE   :LOOPX     
+                563  
+98A0: A0 02     564           LDY   #2         ; send 2 dummy crc bytes
+98A2: 8D C0 C0  565  :CRC     STA   DATA       
+98A5: 2C C1 C0  566  :WAIT5   BIT   CTRL       
+98A8: 10 FB     567           BPL   :WAIT5     
+98AA: 88        568           DEY              
+98AB: D0 F5     569           BNE   :CRC       
+                570  
+98AD: A9 0F     571  :OK      LDA   #SSNONE    ; disable /CS
+98AF: 8D C3 C0  572           STA   SS          
+                              ===== Page 11 =====
+ 
+98B2: 18        573           CLC              ; no error
+98B3: A9 00     574           LDA   #0         
+98B5: 60        575           RTS              
+                576  
+                577  
+                578  ********************************
+                579  *
+                580  * Format
+                581  * not supported!
+                582  *
+                583  ********************************
+                584  
+98B6: 38        585  FORMAT   SEC              
+98B7: A9 01     586           LDA   #$01       ; invalid command
+98B9: 60        587           RTS              
+                588  
+                589  
+                590  
+98BA: 40 00 00  591  CMD0     HEX   400000000095 
+98BD: 00 00 95 
+98C0: 41 00 00  592  CMD1     HEX   4100000000F9 
+98C3: 00 00 F9 
+98C6: 48 00 00  593  CMD8     HEX   48000001AA87 
+98C9: 01 AA 87 
+98CC: 50 00 00  594  CMD16    HEX   5000000200FF 
+98CF: 02 00 FF 
+98D2: 77 00 00  595  CMD55    HEX   770000000065 
+98D5: 00 00 65 
+98D8: 69 40 00  596  ACMD41_40 HEX  694000000077 
+98DB: 00 00 77 
+98DE: 69 00 00  597  ACMD41_0 HEX   6900000000FF 
+98E1: 00 00 FF 
+                598  
+                599  DRIVEND  =     *          
+ 
+ 
+--End assembly, 880 bytes, Errors: 0 
+
+
+Symbol table - alphabetical order:
+
+   ACMD41_0=$98DE      ACMD41_40=$98D8      BLOCKSZ =$96D2      BUFLSB  =$8085
+   BUFMSB  =$8084   ?  CDERROR =$96E9      CMD     =$96FD      CMD0    =$98BA
+   CMD1    =$98C0      CMD16   =$98CC      CMD55   =$98D2      CMD8    =$98C6
+   CMDHI   =$FB        CMDLO   =$FA        CTRL    =$C0C1      DATA    =$C0C0
+   DIV     =$C0C2      DRIVEND =$98E4      DRIVER  =$9600      DRIVER1 =$808C
+   DUMMY   =$FF     ?  END     =$96E4      END1    =$96F1      ERROR   =$8060
+   ERROR1  =$9695      FORMAT  =$98B6      FROM    =$FA     ?  GETBUF  =$8000
+   GETR1   =$970F      GETR3   =$972C      INIT    =$9626      INSLP   =$804D
+   INSLP2  =$8063      INSOUT  =$8083   ?  INSTALL =$804A      IOERROR =$96EE
+   MMC     =$96BC   ?  MOVEUP  =$8021      MU1     =$8037      MU2     =$803E
+   MU3     =$8042      R30     =$0478      R31     =$04F8      R32     =$0578
+   R33     =$05F8      READ    =$9764      SDV1    =$9698      SDV2    =$966E
+   SIZE    =$FE        SLOT    =$04        SS      =$C0C3      SS0     =$0E
+   SSNONE  =$0F        STATUS  =$975C   ?  TC      =$80        TO      =$FC
+   WRITE   =$980F   
+ 
+                              ===== Page 12 =====
+ 
+
+Symbol table - numerical order:
+
+   SLOT    =$04        SS0     =$0E        SSNONE  =$0F     ?  TC      =$80
+   CMDLO   =$FA        FROM    =$FA        CMDHI   =$FB        TO      =$FC
+   SIZE    =$FE        DUMMY   =$FF        R30     =$0478      R31     =$04F8
+   R32     =$0578      R33     =$05F8   ?  GETBUF  =$8000   ?  MOVEUP  =$8021
+   MU1     =$8037      MU2     =$803E      MU3     =$8042   ?  INSTALL =$804A
+   INSLP   =$804D      ERROR   =$8060      INSLP2  =$8063      INSOUT  =$8083
+   BUFMSB  =$8084      BUFLSB  =$8085      DRIVER1 =$808C      DRIVER  =$9600
+   INIT    =$9626      SDV2    =$966E      ERROR1  =$9695      SDV1    =$9698
+   MMC     =$96BC      BLOCKSZ =$96D2   ?  END     =$96E4   ?  CDERROR =$96E9
+   IOERROR =$96EE      END1    =$96F1      CMD     =$96FD      GETR1   =$970F
+   GETR3   =$972C      STATUS  =$975C      READ    =$9764      WRITE   =$980F
+   FORMAT  =$98B6      CMD0    =$98BA      CMD1    =$98C0      CMD8    =$98C6
+   CMD16   =$98CC      CMD55   =$98D2      ACMD41_40=$98D8      ACMD41_0=$98DE
+   DRIVEND =$98E4      DATA    =$C0C0      CTRL    =$C0C1      DIV     =$C0C2
+   SS      =$C0C3   
+
diff --git a/Hardware/SD_A2.brd b/Hardware/SD_A2.brd
new file mode 100644
index 0000000..2163fed
--- /dev/null
+++ b/Hardware/SD_A2.brd
@@ -0,0 +1,3102 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="8.2.1">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.25" unitdist="mm" unit="mm" style="dots" multiple="1" display="yes" altdistance="0.1" altunitdist="mil" altunit="mil"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
+<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="50" name="dxf" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="no" active="no"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="no" active="no"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="no" active="no"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="no"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="no" active="no"/>
+<layer number="95" name="Names" color="7" fill="1" visible="no" active="no"/>
+<layer number="96" name="Values" color="7" fill="1" visible="no" active="no"/>
+<layer number="97" name="Info" color="7" fill="1" visible="no" active="no"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/>
+<layer number="105" name="Beschreib" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="106" name="BGA-Top" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="107" name="BD-Top" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="200" name="200bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="250" name="Descript" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="251" name="SMDround" color="7" fill="1" visible="yes" active="yes"/>
+</layers>
+<board>
+<plain>
+<wire x1="0" y1="0" x2="100" y2="0" width="0" layer="20"/>
+<wire x1="100" y1="0" x2="100" y2="80" width="0" layer="20"/>
+<wire x1="100" y1="80" x2="0" y2="80" width="0" layer="20"/>
+<wire x1="0" y1="80" x2="0" y2="0" width="0" layer="20"/>
+<text x="2.25" y="11.25" size="1.27" layer="1" font="vector" ratio="7">Apple ][ SD V1.0
+(C) Florian Reitz 2017</text>
+</plain>
+<libraries>
+<library name="con-apple2">
+<description>&lt;b&gt;Apple ][ Expansion Card Templates&lt;/b&gt;
+&lt;br /&gt;
+Dimensions are taken from the Apple IIgs Tech Note #28</description>
+<packages>
+<package name="A2-50PIN-SL1-3">
+<description>&lt;B&gt;Apple ][ Peripheral Card&lt;/B&gt;
+&lt;br /&gt;
+Standard 50-pin edge connector for Apple ][ systems
+&lt;br /&gt;
+Dimensions for slot #1 to #3
+&lt;br /&gt;
+Dimensions taken from Tech Note #28</description>
+<wire x1="-9.652" y1="0.508" x2="-10.287" y2="-0.127" width="0.2032" layer="21"/>
+<wire x1="-10.287" y1="-0.127" x2="-74.803" y2="-0.127" width="0.2032" layer="21"/>
+<wire x1="-74.803" y1="-0.127" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
+<wire x1="-9.652" y1="7.747" x2="-9.652" y2="0.508" width="0.2032" layer="21"/>
+<wire x1="-0.127" y1="7.747" x2="-9.652" y2="7.747" width="0.2032" layer="21"/>
+<wire x1="-75.438" y1="7.747" x2="-177.927" y2="7.747" width="0.2032" layer="21"/>
+<wire x1="-75.438" y1="7.747" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
+<wire x1="-82.5246" y1="-0.127" x2="-87.5284" y2="-0.127" width="0" layer="48"/>
+<wire x1="-87.5284" y1="-0.127" x2="-86.8426" y2="1.4986" width="0" layer="48"/>
+<wire x1="-87.5284" y1="-0.127" x2="-88.4174" y2="-0.127" width="0" layer="48"/>
+<wire x1="-88.2142" y1="1.4986" x2="-87.5284" y2="-0.127" width="0" layer="48"/>
+<wire x1="-87.5284" y1="7.747" x2="-88.2396" y2="6.2484" width="0" layer="48"/>
+<wire x1="-88.2396" y1="6.2484" x2="-86.8172" y2="6.2484" width="0" layer="48"/>
+<wire x1="-86.8172" y1="6.2484" x2="-87.5284" y2="7.747" width="0" layer="48"/>
+<wire x1="-87.5284" y1="7.747" x2="-87.5284" y2="5.5372" width="0" layer="48"/>
+<wire x1="-87.5284" y1="-0.127" x2="-87.5284" y2="1.9558" width="0" layer="48"/>
+<wire x1="-86.8426" y1="1.4986" x2="-88.2142" y2="1.4986" width="0" layer="48"/>
+<wire x1="-75.438" y1="-1.143" x2="-75.438" y2="-8.382" width="0" layer="48"/>
+<wire x1="-9.652" y1="-0.2286" x2="-9.652" y2="-8.128" width="0" layer="48"/>
+<wire x1="-9.6774" y1="-6.985" x2="-75.4126" y2="-6.985" width="0" layer="48"/>
+<wire x1="-75.4126" y1="-6.985" x2="-73.025" y2="-5.715" width="0" layer="48"/>
+<wire x1="-73.025" y1="-5.715" x2="-73.025" y2="-8.255" width="0" layer="48"/>
+<wire x1="-73.025" y1="-8.255" x2="-75.4126" y2="-6.985" width="0" layer="48"/>
+<wire x1="-9.6774" y1="-6.985" x2="-12.065" y2="-5.715" width="0" layer="48"/>
+<wire x1="-12.065" y1="-5.715" x2="-12.065" y2="-8.255" width="0" layer="48"/>
+<wire x1="-12.065" y1="-8.255" x2="-9.6774" y2="-6.985" width="0" layer="48"/>
+<wire x1="-0.127" y1="77.597" x2="-177.927" y2="77.597" width="0.2032" layer="21"/>
+<wire x1="-75.438" y1="7.747" x2="-75.438" y2="5.715" width="0.1524" layer="21"/>
+<wire x1="-101.6" y1="2.54" x2="-101.6" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-99.06" y1="2.54" x2="-99.06" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-96.52" y1="2.54" x2="-96.52" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-93.98" y1="2.54" x2="-93.98" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-91.44" y1="2.54" x2="-91.44" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-88.9" y1="2.54" x2="-88.9" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-86.36" y1="2.54" x2="-86.36" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-83.82" y1="2.54" x2="-83.82" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-81.28" y1="2.54" x2="-81.28" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-78.74" y1="2.54" x2="-78.74" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-76.2" y1="2.54" x2="-76.2" y2="-3.81" width="1.016" layer="34"/>
+<wire x1="-73.66" y1="2.54" x2="-73.66" y2="-3.81" width="1.016" layer="34"/>
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+<text x="-2.54" y="11.938" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-10.16" y="11.938" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="8.255" y="-10.795" size="1.27" layer="21" ratio="10">44</text>
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+<rectangle x1="-0.127" y1="4.699" x2="0.127" y2="4.953" layer="21"/>
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+<rectangle x1="-0.254" y1="4.699" x2="-0.127" y2="4.826" layer="21"/>
+<rectangle x1="0.127" y1="4.699" x2="0.254" y2="4.826" layer="21"/>
+<rectangle x1="0.381" y1="4.445" x2="0.508" y2="4.572" layer="21"/>
+<rectangle x1="0.635" y1="4.191" x2="0.762" y2="4.318" layer="21"/>
+<rectangle x1="0.889" y1="3.81" x2="1.143" y2="3.937" layer="21"/>
+<rectangle x1="0.889" y1="3.937" x2="1.016" y2="4.064" layer="21"/>
+</package>
+</packages>
+</library>
+<library name="74xx-eu" urn="urn:adsk.eagle:library:85">
+<description>&lt;b&gt;TTL Devices, 74xx Series with European Symbols&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Texas Instruments &lt;i&gt;TTL Data Book&lt;/i&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Volume 1, 1996.
+&lt;li&gt;TTL Data Book, Volume 2 , 1993
+&lt;li&gt;National Seminconductor Databook 1990, ALS/LS Logic
+&lt;li&gt;ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+&lt;li&gt;http://icmaster.com/ViewCompare.asp
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL20">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="12.7" y1="2.921" x2="-12.7" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="-2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="12.7" y1="2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="2.921" x2="-12.7" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="-2.921" x2="-12.7" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="1.016" x2="-12.7" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="-11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-13.081" y="-3.048" size="1.27" layer="25" rot="R90">&gt;NAME</text>
+<text x="-9.779" y="-0.381" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="v-reg" urn="urn:adsk.eagle:library:409">
+<description>&lt;b&gt;Voltage Regulators&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="317TL">
+<description>&lt;b&gt;VOLTAGE REGULATOR&lt;/b&gt;</description>
+<wire x1="-5.207" y1="-1.27" x2="5.207" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="14.605" x2="-5.207" y2="14.605" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="-1.27" x2="5.207" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="11.176" x2="4.318" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="4.318" y1="11.176" x2="4.318" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="4.318" y1="12.7" x2="5.207" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="12.7" x2="5.207" y2="14.605" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="-1.27" x2="-5.207" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="11.176" x2="-4.318" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="-4.318" y1="11.176" x2="-4.318" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="-4.318" y1="12.7" x2="-5.207" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="12.7" x2="-5.207" y2="14.605" width="0.1524" layer="21"/>
+<wire x1="-4.572" y1="-0.635" x2="4.572" y2="-0.635" width="0.0508" layer="21"/>
+<wire x1="4.572" y1="7.62" x2="4.572" y2="-0.635" width="0.0508" layer="21"/>
+<wire x1="4.572" y1="7.62" x2="-4.572" y2="7.62" width="0.0508" layer="21"/>
+<wire x1="-4.572" y1="-0.635" x2="-4.572" y2="7.62" width="0.0508" layer="21"/>
+<circle x="0" y="11.176" radius="1.8034" width="0.1524" layer="21"/>
+<circle x="0" y="11.176" radius="4.191" width="0" layer="42"/>
+<circle x="0" y="11.176" radius="4.191" width="0" layer="43"/>
+<pad name="1" x="-2.54" y="-3.81" drill="1.016" shape="long" rot="R90"/>
+<pad name="2" x="0" y="-3.81" drill="1.016" shape="long" rot="R90"/>
+<pad name="3" x="2.54" y="-3.81" drill="1.016" shape="long" rot="R90"/>
+<text x="-3.81" y="5.08" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.937" y="2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-4.445" y="7.874" size="0.9906" layer="21" ratio="10">A15,2mm</text>
+<text x="-0.508" y="0" size="1.27" layer="51" ratio="10">O</text>
+<text x="2.032" y="0" size="1.27" layer="51" ratio="10">I</text>
+<text x="-3.048" y="0" size="1.27" layer="51" ratio="10">A</text>
+<rectangle x1="1.905" y1="-2.159" x2="3.175" y2="-1.27" layer="21"/>
+<rectangle x1="1.905" y1="-3.81" x2="3.175" y2="-2.159" layer="51"/>
+<rectangle x1="-0.635" y1="-2.159" x2="0.635" y2="-1.27" layer="21"/>
+<rectangle x1="-3.175" y1="-2.159" x2="-1.905" y2="-1.27" layer="21"/>
+<rectangle x1="-0.635" y1="-3.81" x2="0.635" y2="-2.159" layer="51"/>
+<rectangle x1="-3.175" y1="-3.81" x2="-1.905" y2="-2.159" layer="51"/>
+<hole x="0" y="11.176" drill="3.302"/>
+</package>
+</packages>
+</library>
+<library name="rcl" urn="urn:adsk.eagle:library:334">
+<description>&lt;b&gt;Resistors, Capacitors, Inductors&lt;/b&gt;&lt;p&gt;
+Based on the previous libraries:
+&lt;ul&gt;
+&lt;li&gt;r.lbr
+&lt;li&gt;cap.lbr 
+&lt;li&gt;cap-fe.lbr
+&lt;li&gt;captant.lbr
+&lt;li&gt;polcap.lbr
+&lt;li&gt;ipc-smd.lbr
+&lt;/ul&gt;
+All SMD packages are defined according to the IPC specifications and  CECC&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;&lt;p&gt;
+&lt;p&gt;
+for Electrolyt Capacitors see also :&lt;p&gt;
+www.bccomponents.com &lt;p&gt;
+www.panasonic.com&lt;p&gt;
+www.kemet.com&lt;p&gt;
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf &lt;b&gt;(SANYO)&lt;/b&gt;
+&lt;p&gt;
+for trimmer refence see : &lt;u&gt;www.electrospec-inc.com/cross_references/trimpotcrossref.asp&lt;/u&gt;&lt;p&gt;
+
+&lt;table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0&gt;
+&lt;tr valign="top"&gt;
+
+&lt;! &lt;td width="10"&gt;&amp;nbsp;&lt;/td&gt;
+&lt;td width="90%"&gt;
+
+&lt;b&gt;&lt;font color="#0000FF" size="4"&gt;TRIM-POT CROSS REFERENCE&lt;/font&gt;&lt;/b&gt;
+&lt;P&gt;
+&lt;TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;RECTANGULAR MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BOURNS&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BI&amp;nbsp;TECH&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;DALE-VISHAY&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PHILIPS/MEPCO&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MURATA&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
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+      EVMMCS&lt;BR&gt;
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+    &lt;/TD&gt;
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+      -&lt;BR&gt;
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+    &lt;/TD&gt;
+  &lt;/TR&gt;
+&lt;/TABLE&gt;
+&lt;P&gt;&amp;nbsp;&lt;P&gt;
+&lt;TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=7&gt;
+      &lt;FONT color="#0000FF" SIZE=4 FACE=ARIAL&gt;&lt;B&gt;SMD TRIM-POT CROSS REFERENCE&lt;/B&gt;&lt;/FONT&gt;
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+      &lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
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+  &lt;TR&gt;
+    &lt;TD&gt;
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+    &lt;TD&gt;
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+    &lt;/TD&gt;
+    &lt;TD&gt;
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+    &lt;/TD&gt;
+    &lt;TD&gt;
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+  &lt;TR&gt;
+    &lt;TD COLSPAN=7&gt;&amp;nbsp;
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+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      EVM-6YS&lt;BR&gt;
+      EVM-1E&lt;BR&gt;
+      EVM-1G&lt;BR&gt;
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+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
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+      G4A&lt;BR&gt;
+      TR04-3S1&lt;BR&gt;
+      TRG04-2S1&lt;BR&gt;
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+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;
+      DVR-43A&lt;BR&gt;
+      CVR-42C&lt;BR&gt;
+      CVR-42A/C&lt;BR&gt;
+      -&lt;BR&gt;
+      -&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+&lt;/TABLE&gt;
+&lt;P&gt;
+&lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;ALT =&amp;nbsp;ALTERNATE&lt;/B&gt;&lt;/FONT&gt;
+&lt;P&gt;
+
+&amp;nbsp;
+&lt;P&gt;
+&lt;/td&gt;
+&lt;/tr&gt;
+&lt;/table&gt;</description>
+<packages>
+<package name="C025-025X050">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 mm, outline 2.5 x 5 mm</description>
+<wire x1="-2.159" y1="1.27" x2="2.159" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="-1.27" x2="-2.159" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="2.413" y1="1.016" x2="2.413" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-2.413" y1="1.016" x2="-2.413" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="2.159" y1="1.27" x2="2.413" y2="1.016" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-2.413" y1="1.016" x2="-2.159" y2="1.27" width="0.1524" layer="21" curve="-90"/>
+<wire x1="2.159" y1="-1.27" x2="2.413" y2="-1.016" width="0.1524" layer="21" curve="90"/>
+<wire x1="-2.413" y1="-1.016" x2="-2.159" y2="-1.27" width="0.1524" layer="21" curve="90"/>
+<wire x1="0.762" y1="0" x2="0.381" y2="0" width="0.1524" layer="51"/>
+<wire x1="0.381" y1="0" x2="0.254" y2="0" width="0.1524" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="0.762" width="0.254" layer="21"/>
+<wire x1="0.254" y1="0" x2="0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0.762" x2="-0.254" y2="0" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.254" y2="-0.762" width="0.254" layer="21"/>
+<wire x1="-0.254" y1="0" x2="-0.381" y2="0" width="0.1524" layer="21"/>
+<wire x1="-0.381" y1="0" x2="-0.762" y2="0" width="0.1524" layer="51"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.286" y="1.524" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.286" y="-2.794" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="E2,5-5">
+<description>&lt;b&gt;ELECTROLYTIC CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.54 mm, diameter 5 mm</description>
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+<text x="2.413" y="1.27" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="2.413" y="-2.413" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="0.254" y1="-1.27" x2="0.762" y2="1.27" layer="51"/>
+</package>
+<package name="0204/7">
+<description>&lt;b&gt;RESISTOR&lt;/b&gt;&lt;p&gt;
+type 0204, grid 7.5 mm</description>
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+<wire x1="2.54" y1="-0.762" x2="2.54" y2="0.762" width="0.1524" layer="21"/>
+<pad name="1" x="-3.81" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="3.81" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.54" y="1.2954" size="0.9906" layer="25" ratio="10">&gt;NAME</text>
+<text x="-1.6256" y="-0.4826" size="0.9906" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="2.54" y1="-0.254" x2="2.921" y2="0.254" layer="21"/>
+<rectangle x1="-2.921" y1="-0.254" x2="-2.54" y2="0.254" layer="21"/>
+</package>
+</packages>
+</library>
+<library name="led" urn="urn:adsk.eagle:library:259">
+<description>&lt;b&gt;LEDs&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;&lt;br&gt;
+Extended by Federico Battaglin &lt;author&gt;&amp;lt;federico.rd@fdpinternational.com&amp;gt;&lt;/author&gt; with DUOLED</description>
+<packages>
+<package name="LED2X5">
+<description>&lt;B&gt;LED&lt;/B&gt;&lt;p&gt;
+2 x 5 mm, rectangle</description>
+<wire x1="-2.54" y1="-1.27" x2="2.54" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="1.27" x2="2.54" y2="-1.27" width="0.1524" layer="21"/>
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+<wire x1="-1.905" y1="0" x2="0.508" y2="0" width="0.1524" layer="51"/>
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+<wire x1="1.397" y1="-0.254" x2="1.651" y2="-0.762" width="0.1524" layer="51"/>
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+<wire x1="1.4478" y1="-0.6096" x2="1.651" y2="-0.508" width="0.1524" layer="51"/>
+<pad name="A" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="K" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="-2.54" y="1.397" size="1.016" layer="25" ratio="10">&gt;NAME</text>
+<text x="-2.54" y="-2.413" size="1.016" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="2.159" y1="-1.27" x2="2.413" y2="1.27" layer="21"/>
+</package>
+</packages>
+</library>
+<library name="memory" urn="urn:adsk.eagle:library:279">
+<description>&lt;b&gt;Generic Memories&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL24">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="-15.24" y1="6.731" x2="-15.24" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-15.24" y1="-6.731" x2="-15.24" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-15.24" y1="1.016" x2="-15.24" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
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+<wire x1="15.24" y1="6.731" x2="15.24" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="15.24" y1="6.731" x2="-15.24" y2="6.731" width="0.1524" layer="21"/>
+<pad name="1" x="-13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
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+<pad name="4" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="-3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="-6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="-8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="-11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="-13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<text x="-15.494" y="-6.731" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-11.303" y="-0.889" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="con-sd-attend2">
+<packages>
+<package name="104H-TDA0-R">
+<smd name="P4" x="0" y="-0.625" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P3" x="0" y="1.875" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P2" x="0" y="4.375" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P1" x="0" y="6.875" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P9" x="0" y="9.375" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P5" x="0" y="-3.125" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P6" x="0" y="-5.625" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P7" x="0" y="-8.125" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P8" x="0" y="-9.775" dx="1" dy="1.6" layer="1" rot="R90"/>
+<pad name="GND0" x="24.2" y="-13.4" drill="1.6"/>
+<wire x1="0" y1="-13.5" x2="29.5" y2="-13.5" width="0.127" layer="21"/>
+<wire x1="0" y1="14.65" x2="29.5" y2="14.65" width="0.127" layer="21"/>
+<wire x1="0" y1="-13.5" x2="0" y2="14.65" width="0.127" layer="21"/>
+<wire x1="29.5" y1="14.65" x2="29.5" y2="-13.5" width="0.127" layer="21"/>
+<pad name="GND1" x="24.2" y="14.55" drill="1.6"/>
+<smd name="CD" x="11.3" y="-13.125" dx="1.75" dy="1.2" layer="1" rot="R90"/>
+<smd name="WP" x="20.1" y="-13.125" dx="1.75" dy="1.2" layer="1" rot="R90"/>
+<smd name="SC" x="21.4" y="-13.125" dx="1.75" dy="1.2" layer="1" rot="R90"/>
+</package>
+</packages>
+</library>
+<library name="pinhead" urn="urn:adsk.eagle:library:325">
+<description>&lt;b&gt;Pin Header Connectors&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="1X06">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<wire x1="0.635" y1="1.27" x2="1.905" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="1.27" x2="2.54" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.635" x2="2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.635" x2="1.905" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.635" x2="3.175" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="1.27" x2="4.445" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="1.27" x2="5.08" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="0.635" x2="5.08" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-0.635" x2="4.445" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="-1.27" x2="3.175" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-1.27" x2="2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.635" x2="-1.905" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="1.27" x2="-0.635" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="1.27" x2="0" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="-0.635" width="0.1524" layer="21"/>
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+<wire x1="-0.635" y1="-1.27" x2="-1.905" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="-1.27" x2="-2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="1.27" x2="0" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="-0.635" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="-1.27" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-6.985" y1="1.27" x2="-5.715" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-5.715" y1="1.27" x2="-5.08" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.635" x2="-5.08" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-0.635" x2="-5.715" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.635" x2="-4.445" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="1.27" x2="-3.175" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="1.27" x2="-2.54" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.635" x2="-2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.635" x2="-3.175" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="-1.27" x2="-4.445" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="-1.27" x2="-5.08" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-7.62" y1="0.635" x2="-7.62" y2="-0.635" width="0.1524" layer="21"/>
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+<wire x1="-7.62" y1="-0.635" x2="-6.985" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-5.715" y1="-1.27" x2="-6.985" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.715" y1="1.27" x2="6.985" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="1.27" x2="7.62" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="0.635" x2="7.62" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="-0.635" x2="6.985" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.715" y1="1.27" x2="5.08" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-0.635" x2="5.715" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="-1.27" x2="5.715" y2="-1.27" width="0.1524" layer="21"/>
+<pad name="1" x="-6.35" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="2" x="-3.81" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="3" x="-1.27" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="4" x="1.27" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="5" x="3.81" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="6" x="6.35" y="0" drill="1.016" shape="long" rot="R90"/>
+<text x="-7.6962" y="1.8288" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-7.62" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="3.556" y1="-0.254" x2="4.064" y2="0.254" layer="51"/>
+<rectangle x1="1.016" y1="-0.254" x2="1.524" y2="0.254" layer="51"/>
+<rectangle x1="-1.524" y1="-0.254" x2="-1.016" y2="0.254" layer="51"/>
+<rectangle x1="-4.064" y1="-0.254" x2="-3.556" y2="0.254" layer="51"/>
+<rectangle x1="-6.604" y1="-0.254" x2="-6.096" y2="0.254" layer="51"/>
+<rectangle x1="6.096" y1="-0.254" x2="6.604" y2="0.254" layer="51"/>
+</package>
+</packages>
+</library>
+<library name="con-lstb" urn="urn:adsk.eagle:library:162">
+<description>&lt;b&gt;Pin Headers&lt;/b&gt;&lt;p&gt;
+Naming:&lt;p&gt;
+MA = male&lt;p&gt;
+# contacts - # rows&lt;p&gt;
+W = angled&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="MA03-1" library_version="1">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<wire x1="-3.175" y1="1.27" x2="-1.905" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="1.27" x2="-1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="-0.635" x2="-1.905" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="0.635" x2="-0.635" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="1.27" x2="0.635" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="1.27" x2="1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-0.635" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="-1.27" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="-1.27" x2="-1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-3.81" y1="0.635" x2="-3.81" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="1.27" x2="-3.81" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-3.81" y1="-0.635" x2="-3.175" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="-1.27" x2="-3.175" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.635" x2="1.905" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="1.27" x2="3.175" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="1.27" x2="3.81" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="3.81" y1="-0.635" x2="3.175" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-1.27" x2="1.905" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="-1.27" x2="1.27" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="3.81" y1="0.635" x2="3.81" y2="-0.635" width="0.1524" layer="21"/>
+<pad name="1" x="-2.54" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="2" x="0" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="3" x="2.54" y="0" drill="1.016" shape="long" rot="R90"/>
+<text x="-3.81" y="1.651" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-5.08" y="-0.635" size="1.27" layer="21" ratio="10">1</text>
+<text x="-3.81" y="-2.921" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-0.254" y1="-0.254" x2="0.254" y2="0.254" layer="51"/>
+<rectangle x1="-2.794" y1="-0.254" x2="-2.286" y2="0.254" layer="51"/>
+<rectangle x1="2.286" y1="-0.254" x2="2.794" y2="0.254" layer="51"/>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="PCB-POOL Standard">
+<description language="de">&lt;b&gt;EAGLE Design Rules Prototypen  für PCB-POOL(R)&lt;/b&gt;
+&lt;p&gt;
+Wir haben in diesem DRU File alle notwendigen Design Einstellungen vorgenommen, damit Sie Ihre Leiterplatte 
+gemaess unseren Mindestanforderungen im Standard bestellen koennen. Die Optionen Shapes und Misc sind dabei nicht relevant.
+Der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden.
+Bitte beachten Sie, daß die Mindesteinstellungen nicht geaendert werden, da ansonsten keine Gewaehrleistung für eine 
+fehlerfreie Produktion übernommen werden kann.&lt;br&gt;
+Abzudeckende Vias koennen in Masks (unter Limit) eingestellt werden.
+&lt;/p&gt;Ihr Beta LAYOUT Team
+&lt;p&gt;&lt;p&gt;
+&lt;b&gt;EAGLE Design Rules Prototypes to use with PCB-POOL(R)&lt;/b&gt;
+&lt;p&gt;
+The design rules in this DRU file have been set to cover our minimum standard requirements, the options Shapes and  Misc are not
+relevant. Values for Roundness (Shapes) can be chosen freely. Please do not change these minimum
+requirements to avoid problems during production.&lt;br&gt;
+Covered vias can be set in Masks (Limit).
+
+&lt;/p&gt;Your Beta LAYOUT Team</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>
+<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>
+<param name="mdWireWire" value="0.15mm"/>
+<param name="mdWirePad" value="0.15mm"/>
+<param name="mdWireVia" value="0.15mm"/>
+<param name="mdPadPad" value="0.15mm"/>
+<param name="mdPadVia" value="0.15mm"/>
+<param name="mdViaVia" value="0.15mm"/>
+<param name="mdSmdPad" value="0.15mm"/>
+<param name="mdSmdVia" value="0.15mm"/>
+<param name="mdSmdSmd" value="0.15mm"/>
+<param name="mdViaViaSameLayer" value="0.2mm"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="0.3mm"/>
+<param name="mdDrill" value="0.2mm"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="0.15mm"/>
+<param name="msDrill" value="0.3mm"/>
+<param name="msMicroVia" value="25mm"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0"/>
+<param name="rvPadInner" value="0"/>
+<param name="rvPadBottom" value="0"/>
+<param name="rvViaOuter" value="0"/>
+<param name="rvViaInner" value="0"/>
+<param name="rvMicroViaOuter" value="0"/>
+<param name="rvMicroViaInner" value="0"/>
+<param name="rlMinPadTop" value="0.2mm"/>
+<param name="rlMaxPadTop" value="2.5mm"/>
+<param name="rlMinPadInner" value="0.2mm"/>
+<param name="rlMaxPadInner" value="2.5mm"/>
+<param name="rlMinPadBottom" value="0.2mm"/>
+<param name="rlMaxPadBottom" value="2.5mm"/>
+<param name="rlMinViaOuter" value="0.15mm"/>
+<param name="rlMaxViaOuter" value="2.5mm"/>
+<param name="rlMinViaInner" value="0.2mm"/>
+<param name="rlMaxViaInner" value="2.5mm"/>
+<param name="rlMinMicroViaOuter" value="2.5mm"/>
+<param name="rlMaxMicroViaOuter" value="25mm"/>
+<param name="rlMinMicroViaInner" value="2.5mm"/>
+<param name="rlMaxMicroViaInner" value="25mm"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="0"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="0.075mm"/>
+<param name="mlMaxStopFrame" value="0.2mm"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0.2mm"/>
+<param name="mlViaStopLimit" value="0mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="0.2mm"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="ST1" library="con-apple2" package="A2-50PIN-SL1-3" value="" x="100.33" y="0"/>
+<element name="U$1" library="xilinx-xc9" library_urn="urn:adsk.eagle:library:416" package="S44" value="XC9572XL" x="36.81" y="64.21"/>
+<element name="IC1" library="74xx-eu" library_urn="urn:adsk.eagle:library:85" package="DIL20" value="74HCT245N" x="39.98" y="17.85" rot="R180"/>
+<element name="IC2" library="v-reg" library_urn="urn:adsk.eagle:library:409" package="317TL" value="LM317" x="83.77" y="21.07" rot="R270"/>
+<element name="C1" library="rcl" library_urn="urn:adsk.eagle:library:334" package="C025-025X050" value="100n" x="81.2" y="12.72"/>
+<element name="C2" library="rcl" library_urn="urn:adsk.eagle:library:334" package="E2,5-5" value="1u" x="75.42731875" y="21.02" rot="R180"/>
+<element name="R1" library="rcl" library_urn="urn:adsk.eagle:library:334" package="0204/7" value="200" x="76.26" y="28.01" rot="R180"/>
+<element name="R2" library="rcl" library_urn="urn:adsk.eagle:library:334" package="0204/7" value="330" x="76.24" y="25.52"/>
+<element name="R3" library="rcl" library_urn="urn:adsk.eagle:library:334" package="0204/7" value="22k" x="90.8" y="34.26" rot="R270"/>
+<element name="R4" library="rcl" library_urn="urn:adsk.eagle:library:334" package="0204/7" value="470" x="53.26" y="57.67" rot="R180"/>
+<element name="LED1" library="led" library_urn="urn:adsk.eagle:library:259" package="LED2X5" value="" x="57.11" y="72.8" rot="R270"/>
+<element name="IC3" library="memory" library_urn="urn:adsk.eagle:library:279" package="DIL24" value="2716" x="32.32" y="37.44" rot="R180"/>
+<element name="C3" library="rcl" library_urn="urn:adsk.eagle:library:334" package="C025-025X050" value="100n" x="58.45" y="14.18"/>
+<element name="C4" library="rcl" library_urn="urn:adsk.eagle:library:334" package="C025-025X050" value="100n" x="48.96" y="27.05" rot="R270"/>
+<element name="C5" library="rcl" library_urn="urn:adsk.eagle:library:334" package="C025-025X050" value="100n" x="52.01" y="72.95" rot="R90"/>
+<element name="U$2" library="con-sd-attend2" package="104H-TDA0-R" value="104H-TDA0-R" x="82.5" y="40.5" rot="R90"/>
+<element name="JP1" library="pinhead" library_urn="urn:adsk.eagle:library:325" package="1X06" value="" x="15.75" y="68" rot="R270"/>
+<element name="R5" library="rcl" library_urn="urn:adsk.eagle:library:334" package="0204/7" value="22k" x="73.25" y="34.25" rot="R90"/>
+<element name="R6" library="rcl" library_urn="urn:adsk.eagle:library:334" package="0204/7" value="22k" x="93.25" y="34.25" rot="R90"/>
+<element name="R7" library="rcl" library_urn="urn:adsk.eagle:library:334" package="0204/7" value="22k" x="76.75" y="34.25" rot="R270"/>
+<element name="R8" library="rcl" library_urn="urn:adsk.eagle:library:334" package="0204/7" value="22k" x="79.25" y="34.25" rot="R270"/>
+<element name="R9" library="rcl" library_urn="urn:adsk.eagle:library:334" package="0204/7" value="22k" x="64.75" y="56.75" rot="R90"/>
+<element name="SV1" library="con-lstb" library_urn="urn:adsk.eagle:library:162" package="MA03-1" value="" x="43.75" y="49">
+<attribute name="MF" value="" x="43.75" y="49" size="1.778" layer="27" display="off"/>
+<attribute name="MPN" value="" x="43.75" y="49" size="1.778" layer="27" display="off"/>
+<attribute name="OC_FARNELL" value="unknown" x="43.75" y="49" size="1.778" layer="27" display="off"/>
+<attribute name="OC_NEWARK" value="unknown" x="43.75" y="49" size="1.778" layer="27" display="off"/>
+</element>
+<element name="R10" library="rcl" library_urn="urn:adsk.eagle:library:334" package="0204/7" value="10k" x="76.25" y="16.25"/>
+</elements>
+<signals>
+<signal name="GND">
+<contactref element="IC1" pad="10"/>
+<contactref element="R2" pad="1"/>
+<contactref element="C1" pad="2"/>
+<contactref element="C2" pad="-"/>
+<contactref element="ST1" pad="26"/>
+<contactref element="U$1" pad="23"/>
+<contactref element="U$1" pad="10"/>
+<contactref element="U$1" pad="31"/>
+<contactref element="IC3" pad="12"/>
+<contactref element="C3" pad="2"/>
+<contactref element="C5" pad="2"/>
+<contactref element="C4" pad="2"/>
+<wire x1="88.265" y1="4.445" x2="88.265" y2="9.515" width="0.4" layer="16"/>
+<wire x1="88.265" y1="9.515" x2="90.25" y2="11.5" width="0.4" layer="16"/>
+<via x="90.25" y="11.5" extent="1-16" drill="0.3" diameter="0.6"/>
+<contactref element="U$2" pad="P6"/>
+<contactref element="U$2" pad="P3"/>
+<contactref element="U$2" pad="GND1"/>
+<contactref element="U$2" pad="GND0"/>
+<wire x1="28.55" y1="21.66" x2="26.16" y2="21.66" width="0.4" layer="16"/>
+<wire x1="26.16" y1="21.66" x2="26" y2="21.5" width="0.4" layer="16"/>
+<via x="26" y="21.5" extent="1-16" drill="0.3" diameter="0.6"/>
+<via x="59.5" y="25.75" extent="1-16" drill="0.3" diameter="0.6"/>
+<contactref element="JP1" pad="2"/>
+<wire x1="48.96" y1="25.78" x2="59.47" y2="25.78" width="0.4" layer="16"/>
+<wire x1="59.47" y1="25.78" x2="59.5" y2="25.75" width="0.4" layer="16"/>
+<wire x1="88.125" y1="40.5" x2="95.9" y2="64.7" width="0" layer="19" extent="1-1"/>
+<wire x1="80.625" y1="40.5" x2="88.125" y2="40.5" width="0" layer="19" extent="1-1"/>
+<wire x1="72.43" y1="25.52" x2="80.625" y2="40.5" width="0" layer="19" extent="1-1"/>
+<wire x1="74.15731875" y1="21.02" x2="72.43" y2="25.52" width="0" layer="19" extent="1-1"/>
+<wire x1="82.47" y1="12.72" x2="74.15731875" y2="21.02" width="0" layer="19" extent="1-1"/>
+<wire x1="88.265" y1="9.515" x2="82.47" y2="12.72" width="0" layer="19" extent="16-16"/>
+<wire x1="59.5" y1="25.75" x2="72.43" y2="25.52" width="0" layer="19" extent="1-1"/>
+<wire x1="59.72" y1="14.18" x2="59.5" y2="25.75" width="0" layer="19" extent="1-1"/>
+<wire x1="28.55" y1="21.66" x2="48.96" y2="25.78" width="0" layer="19" extent="1-1"/>
+<wire x1="18.35" y1="45.06" x2="26.16" y2="21.66" width="0" layer="19" extent="16-16"/>
+<wire x1="35.54" y1="57.86" x2="18.35" y2="45.06" width="0" layer="19" extent="1-1"/>
+<wire x1="45.7" y1="60.4" x2="35.54" y2="57.86" width="0" layer="19" extent="1-1"/>
+<wire x1="30.46" y1="68.02" x2="35.54" y2="57.86" width="0" layer="19" extent="1-1"/>
+<wire x1="52.01" y1="74.22" x2="45.7" y2="60.4" width="0" layer="19" extent="1-1"/>
+<wire x1="15.75" y1="71.81" x2="30.46" y2="68.02" width="0" layer="19" extent="1-1"/>
+<wire x1="67.95" y1="64.7" x2="52.01" y2="74.22" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="+5V">
+<contactref element="C1" pad="1"/>
+<contactref element="IC2" pad="3"/>
+<contactref element="ST1" pad="25"/>
+<contactref element="IC1" pad="20"/>
+<contactref element="IC3" pad="24"/>
+<contactref element="C3" pad="1"/>
+<contactref element="C4" pad="1"/>
+<wire x1="88.265" y1="4.445" x2="88.265" y2="9.485" width="0.4" layer="1"/>
+<wire x1="88.265" y1="9.485" x2="86.25" y2="11.5" width="0.4" layer="1"/>
+<wire x1="80" y1="11.5" x2="86.25" y2="11.5" width="0.4" layer="1"/>
+<wire x1="80" y1="11.5" x2="58.25" y2="11.5" width="0.4" layer="1"/>
+<wire x1="58.25" y1="11.5" x2="57.25" y2="12.5" width="0.4" layer="1"/>
+<wire x1="57.25" y1="12.5" x2="57.25" y2="14.11" width="0.4" layer="1"/>
+<wire x1="57.25" y1="14.11" x2="57.18" y2="14.18" width="0.4" layer="1"/>
+<wire x1="57.18" y1="14.18" x2="51.55" y2="14.18" width="0.4" layer="16"/>
+<wire x1="51.55" y1="14.18" x2="51.41" y2="14.04" width="0.4" layer="16"/>
+<wire x1="79.93" y1="11.57" x2="79.93" y2="12.72" width="0.4" layer="1"/>
+<wire x1="79.93" y1="11.57" x2="80" y2="11.5" width="0.4" layer="1"/>
+<wire x1="79.93" y1="16.25" x2="79.93" y2="12.72" width="0.4" layer="1"/>
+<wire x1="79.93" y1="16.25" x2="79.93" y2="18.5" width="0.4" layer="1"/>
+<wire x1="79.93" y1="18.5" x2="79.96" y2="18.53" width="0.4" layer="1"/>
+<wire x1="57.18" y1="14.18" x2="57.18" y2="27.82" width="0.4" layer="1"/>
+<wire x1="57.18" y1="27.82" x2="57" y2="28.25" width="0.4" layer="1"/>
+<via x="57" y="28.25" extent="1-16" drill="0.3" diameter="0.6"/>
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+<wire x1="30.36" y1="73" x2="30.46" y2="73.1" width="0.4" layer="1"/>
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+<signal name="DATA2">
+<contactref element="IC1" pad="7"/>
+<contactref element="IC3" pad="11"/>
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+<contactref element="U$1" pad="4"/>
+<wire x1="31.65" y1="71.75" x2="33" y2="73.1" width="0.4" layer="1"/>
+</signal>
+<signal name="DATA1">
+<contactref element="IC1" pad="8"/>
+<contactref element="IC3" pad="10"/>
+<wire x1="33.63" y1="19.63" x2="33" y2="19" width="0.4" layer="16"/>
+<wire x1="33" y1="19" x2="22.25" y2="19" width="0.4" layer="16"/>
+<via x="22.25" y="19" extent="1-16" drill="0.3" diameter="0.6"/>
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+<wire x1="25.25" y1="69.25" x2="31.69" y2="69.25" width="0.4" layer="1"/>
+</signal>
+<signal name="DATA0">
+<contactref element="IC1" pad="9"/>
+<contactref element="IC3" pad="9"/>
+<wire x1="31.09" y1="20.09" x2="30.75" y2="19.75" width="0.4" layer="16"/>
+<wire x1="30.75" y1="19.75" x2="24.75" y2="19.75" width="0.4" layer="16"/>
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+</signal>
+<signal name="WP">
+<contactref element="U$1" pad="39"/>
+<contactref element="U$2" pad="WP"/>
+<wire x1="64.75" y1="60.6" x2="95.625" y2="60.6" width="0.4" layer="1"/>
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+<contactref element="R9" pad="2"/>
+<wire x1="64.75" y1="60.56" x2="64.75" y2="60.6" width="0.4" layer="1"/>
+</signal>
+<signal name="CARD">
+<contactref element="U$1" pad="33"/>
+<wire x1="45.7" y1="62.94" x2="50.31" y2="62.94" width="0.4" layer="16"/>
+<wire x1="61.25" y1="51.75" x2="50.31" y2="62.94" width="0.4" layer="16"/>
+<contactref element="U$2" pad="CD"/>
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+<wire x1="61.25" y1="51.75" x2="95.575" y2="51.75" width="0.4" layer="1"/>
+<wire x1="95.575" y1="51.75" x2="95.625" y2="51.8" width="0.4" layer="1"/>
+</signal>
+<signal name="TCK">
+<contactref element="U$1" pad="17"/>
+<contactref element="JP1" pad="3"/>
+<wire x1="27.92" y1="57.86" x2="14.64" y2="57.86" width="0.4" layer="16"/>
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+<wire x1="13" y1="59.5" x2="13" y2="66.52" width="0.4" layer="16"/>
+</signal>
+<signal name="TDO">
+<contactref element="U$1" pad="30"/>
+<contactref element="JP1" pad="4"/>
+<wire x1="43.16" y1="57.86" x2="43.14" y2="57.86" width="0.4" layer="16"/>
+<wire x1="43.14" y1="57.86" x2="34.25" y2="66.75" width="0.4" layer="16"/>
+<wire x1="15.77" y1="66.75" x2="15.75" y2="66.73" width="0.4" layer="16"/>
+<wire x1="34.25" y1="66.75" x2="15.77" y2="66.75" width="0.4" layer="16"/>
+</signal>
+<signal name="TDI">
+<contactref element="U$1" pad="15"/>
+<contactref element="JP1" pad="5"/>
+<wire x1="27.92" y1="60.4" x2="19.54" y2="60.4" width="0.4" layer="16"/>
+<wire x1="19.54" y1="60.4" x2="15.75" y2="64.19" width="0.4" layer="16"/>
+</signal>
+<signal name="TMS">
+<contactref element="U$1" pad="16"/>
+<contactref element="JP1" pad="6"/>
+<wire x1="30.46" y1="60.4" x2="30.4" y2="60.4" width="0.4" layer="16"/>
+<wire x1="30.4" y1="60.4" x2="29.25" y2="59.25" width="0.4" layer="16"/>
+<wire x1="29.25" y1="59.25" x2="18.15" y2="59.25" width="0.4" layer="16"/>
+<wire x1="18.15" y1="59.25" x2="15.75" y2="61.65" width="0.4" layer="16"/>
+</signal>
+<signal name="!IO_STR">
+<contactref element="ST1" pad="20"/>
+<wire x1="75.565" y1="8.685" x2="73.5" y2="10.75" width="0.4" layer="1"/>
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+<contactref element="U$1" pad="40"/>
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+<wire x1="43.26" y1="73" x2="43.16" y2="73.1" width="0.4" layer="1"/>
+</signal>
+<signal name="!IO_SEL">
+<wire x1="36.17" y1="39.33" x2="35" y2="40.75" width="0.4" layer="1"/>
+<contactref element="ST1" pad="01"/>
+<via x="27.25" y="35.25" extent="1-16" drill="0.3" diameter="0.6"/>
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+<contactref element="U$1" pad="25"/>
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+<via x="36.25" y="35.25" extent="1-16" drill="0.35"/>
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+<wire x1="37" y1="50.75" x2="37" y2="56.78" width="0.4" layer="1"/>
+</signal>
+<signal name="!DEV_SEL">
+<wire x1="50.165" y1="9.915" x2="53.5" y2="13" width="0.4" layer="16"/>
+<via x="53.5" y="13" extent="1-16" drill="0.3" diameter="0.6"/>
+<wire x1="53.5" y1="13" x2="53.5" y2="53.25" width="0.4" layer="1"/>
+<via x="53.5" y="53.25" extent="1-16" drill="0.3" diameter="0.6"/>
+<contactref element="U$1" pad="24"/>
+<wire x1="38.08" y1="55.32" x2="38.08" y2="53.92" width="0.4" layer="16"/>
+<wire x1="38.08" y1="53.92" x2="38.75" y2="53.25" width="0.4" layer="16"/>
+<wire x1="38.75" y1="53.25" x2="53.5" y2="53.25" width="0.4" layer="16"/>
+<contactref element="ST1" pad="41"/>
+<wire x1="50.165" y1="4.445" x2="50.165" y2="9.915" width="0.4" layer="16"/>
+</signal>
+<signal name="!RESET">
+<contactref element="U$1" pad="20"/>
+<wire x1="33" y1="55.32" x2="33" y2="54.25" width="0.4" layer="16"/>
+<wire x1="33" y1="54.25" x2="34.75" y2="52.5" width="0.4" layer="16"/>
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+<via x="75.5" y="33.25" extent="1-16" drill="0.3" diameter="0.6"/>
+<wire x1="75.5" y1="33.25" x2="75.5" y2="38.25" width="0.4" layer="1"/>
+<wire x1="75.5" y1="38.25" x2="74.5" y2="39.25" width="0.4" layer="1"/>
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+<via x="60.5" y="48.75" extent="1-16" drill="0.3" diameter="0.6"/>
+<wire x1="75.54721875" y1="20.5436125" x2="75.565" y2="20.52583125" width="0.4" layer="16"/>
+<wire x1="75.54721875" y1="33.20278125" x2="75.5" y2="33.25" width="0.4" layer="16"/>
+<wire x1="75.54721875" y1="20.5436125" x2="75.54721875" y2="33.20278125" width="0.4" layer="16"/>
+<contactref element="ST1" pad="31"/>
+<wire x1="75.565" y1="20.52583125" x2="75.565" y2="4.445" width="0.4" layer="16"/>
+</signal>
+<signal name="CLK">
+<contactref element="U$2" pad="P5"/>
+<contactref element="U$1" pad="34"/>
+<wire x1="85.625" y1="40.5" x2="85.625" y2="48.125" width="0.4" layer="1"/>
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+<wire x1="83" y1="51" x2="60.75" y2="51" width="0.4" layer="1"/>
+<via x="60.75" y="51" extent="1-16" drill="0.3" diameter="0.6"/>
+<wire x1="43.16" y1="62.94" x2="43.31" y2="62.94" width="0.4" layer="16"/>
+<wire x1="44.5" y1="61.75" x2="43.31" y2="62.94" width="0.4" layer="16"/>
+<wire x1="60.75" y1="51" x2="50" y2="61.75" width="0.4" layer="16"/>
+<wire x1="50" y1="61.75" x2="44.5" y2="61.75" width="0.4" layer="16"/>
+</signal>
+<signal name="N$2">
+<contactref element="U$2" pad="P9"/>
+<contactref element="R5" pad="2"/>
+<wire x1="73.125" y1="40.5" x2="73.125" y2="38.185" width="0.4" layer="1"/>
+<wire x1="73.125" y1="38.185" x2="73.25" y2="38.06" width="0.4" layer="1"/>
+</signal>
+<signal name="N$3">
+<contactref element="U$2" pad="P8"/>
+<contactref element="R6" pad="2"/>
+<wire x1="92.275" y1="40.5" x2="92.275" y2="39.035" width="0.4" layer="1"/>
+<wire x1="92.275" y1="39.035" x2="93.25" y2="38.06" width="0.4" layer="1"/>
+</signal>
+<signal name="VPP">
+<contactref element="IC3" pad="21"/>
+<contactref element="SV1" pad="2"/>
+<wire x1="38.67" y1="29.82" x2="38.67" y2="42.17" width="0.4" layer="16"/>
+<wire x1="38.67" y1="42.17" x2="40" y2="43.5" width="0.4" layer="16"/>
+<wire x1="40" y1="43.5" x2="40" y2="50.75" width="0.4" layer="16"/>
+<wire x1="40" y1="50.75" x2="40.75" y2="51.5" width="0.4" layer="16"/>
+<wire x1="40.75" y1="51.5" x2="43.25" y2="51.5" width="0.4" layer="16"/>
+<wire x1="43.25" y1="51.5" x2="43.75" y2="51" width="0.4" layer="16"/>
+<wire x1="43.75" y1="51" x2="43.75" y2="49" width="0.4" layer="16"/>
+</signal>
+<signal name="!IRQ">
+<contactref element="ST1" pad="30"/>
+<contactref element="U$1" pad="2"/>
+<contactref element="R10" pad="1"/>
+<wire x1="35.54" y1="73.1" x2="35.54" y2="73.54" width="0.4" layer="1"/>
+<wire x1="35.54" y1="73.54" x2="36.25" y2="74.25" width="0.4" layer="1"/>
+<wire x1="36.25" y1="74.25" x2="48.25" y2="74.25" width="0.4" layer="1"/>
+<wire x1="48.25" y1="74.25" x2="49.5" y2="73" width="0.4" layer="1"/>
+<wire x1="59.5" y1="12.5" x2="58.65" y2="13.35" width="0.4" layer="1"/>
+<wire x1="72.5" y1="12.5" x2="59.5" y2="12.5" width="0.4" layer="1"/>
+<via x="78" y="12.5" extent="1-16" drill="0.35"/>
+<wire x1="72.5" y1="12.5" x2="78" y2="12.5" width="0.4" layer="1"/>
+<wire x1="78" y1="12.5" x2="78" y2="4.55" width="0.4" layer="16"/>
+<wire x1="78" y1="4.55" x2="78.105" y2="4.445" width="0.4" layer="16"/>
+<wire x1="72.44" y1="16.25" x2="72.44" y2="12.56" width="0.4" layer="1"/>
+<wire x1="72.44" y1="12.56" x2="72.5" y2="12.5" width="0.4" layer="1"/>
+<wire x1="49.5" y1="73" x2="57.75" y2="73" width="0.4" layer="1"/>
+<wire x1="58.65" y1="58.18075625" x2="58.65" y2="13.35" width="0.4" layer="1"/>
+<wire x1="57.75" y1="73" x2="58.25" y2="72.5" width="0.4" layer="1"/>
+<wire x1="58.25" y1="72.5" x2="58.25" y2="61.5" width="0.4" layer="1"/>
+<wire x1="58.25" y1="61.5" x2="57.85" y2="61.1" width="0.4" layer="1"/>
+<wire x1="57.85" y1="58.98075625" x2="58.65" y2="58.18075625" width="0.4" layer="1"/>
+<wire x1="57.85" y1="61.1" x2="57.85" y2="58.98075625" width="0.4" layer="1"/>
+</signal>
+</signals>
+<errors>
+<approved hash="5,1,53ca26de766f2b1a"/>
+</errors>
+</board>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+<note version="8.2" severity="warning">
+Since Version 8.2, Eagle supports online libraries. The ids
+of those online libraries will not be understood (or retained)
+with this version.
+</note>
+</compatibility>
+</eagle>
diff --git a/Hardware/SD_A2.sch b/Hardware/SD_A2.sch
new file mode 100644
index 0000000..e44101a
--- /dev/null
+++ b/Hardware/SD_A2.sch
@@ -0,0 +1,16677 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="8.2.1">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
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+<description>&lt;B&gt;Apple ][ Peripheral Card&lt;/B&gt;
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+<rectangle x1="-26.162" y1="1.778" x2="-24.638" y2="8.382" layer="33"/>
+<wire x1="-177.927" y1="77.597" x2="-177.927" y2="7.747" width="0.2032" layer="21"/>
+</package>
+<package name="A2-50PIN-SL4-7">
+<description>&lt;B&gt;Apple ][ Peripheral Card&lt;/B&gt;
+&lt;br /&gt;
+Standard 50-pin edge connector for Apple ][ systems
+&lt;br /&gt;
+Dimensions for slot #4 to #7
+&lt;br /&gt;
+Dimensions taken from Tech Note #28</description>
+<wire x1="-9.652" y1="0.508" x2="-10.287" y2="-0.127" width="0.2032" layer="21"/>
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+<wire x1="-75.438" y1="7.747" x2="-75.438" y2="0.508" width="0.2032" layer="21"/>
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+<text x="-5.715" y="3.175" size="1.778" layer="25">&gt;NAME</text>
+<text x="-94.5134" y="2.9718" size="1.778" layer="48">7,87 mm</text>
+<text x="-40.8432" y="-9.2964" size="1.778" layer="48">74.93 mm
+2.950"</text>
+<text x="-5.715" y="-0.635" size="1.778" layer="27">&gt;VALUE</text>
+<wire x1="-196.977" y1="77.597" x2="-254.127" y2="63.627" width="0.2032" layer="21"/>
+<wire x1="-254.127" y1="63.627" x2="-254.127" y2="7.747" width="0.2032" layer="21"/>
+</package>
+</packages>
+<symbols>
+<symbol name="ATPIN">
+<wire x1="0" y1="0.635" x2="3.175" y2="0.635" width="0.3048" layer="94"/>
+<wire x1="3.175" y1="0.635" x2="3.175" y2="-0.635" width="0.3048" layer="94"/>
+<wire x1="3.175" y1="-0.635" x2="0" y2="-0.635" width="0.3048" layer="94"/>
+<wire x1="0" y1="-0.635" x2="0" y2="0.635" width="0.3048" layer="94"/>
+<text x="4.445" y="-0.9652" size="1.778" layer="95">&gt;NAME</text>
+<pin name="P" x="-2.54" y="0" visible="pad" length="short" swaplevel="1"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="A2-50PIN" prefix="ST" uservalue="yes">
+<description>&lt;B&gt;Apple ][ Peripheral Card Connector&lt;/B&gt;
+&lt;br /&gt;
+This is the, default, 50-pin connector for slot #1 to #7
+&lt;br /&gt;
+Pins are laid out as seen from the top of the slot</description>
+<gates>
+<gate name="_-12V@2" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
+<gate name="_D0" symbol="ATPIN" x="-5.08" y="-35.56" addlevel="always"/>
+<gate name="_D1" symbol="ATPIN" x="-5.08" y="-33.02" addlevel="always"/>
+<gate name="_D2" symbol="ATPIN" x="-5.08" y="-30.48" addlevel="always"/>
+<gate name="_D3" symbol="ATPIN" x="-5.08" y="-27.94" addlevel="always"/>
+<gate name="_D4" symbol="ATPIN" x="-5.08" y="-25.4" addlevel="always"/>
+<gate name="_D5" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
+<gate name="_D6" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
+<gate name="_D7" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
+<gate name="_DEVSELECT\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
+<gate name="_00" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
+<gate name="_USER1" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
+<gate name="_01" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
+<gate name="_Q3" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
+<gate name="_7M" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
+<gate name="_NC@2" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
+<gate name="_-5V" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
+<gate name="_-12V@1" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
+<gate name="_INH\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
+<gate name="_RES\" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
+<gate name="_IRQ\" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
+<gate name="_NMI\" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
+<gate name="_INT_IN" symbol="ATPIN" x="-5.08" y="17.78" addlevel="always"/>
+<gate name="_DMA_IN" symbol="ATPIN" x="-5.08" y="20.32" addlevel="always"/>
+<gate name="_GND" symbol="ATPIN" x="-5.08" y="22.86" addlevel="always"/>
+<gate name="_IOSELECT\" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
+<gate name="_A00" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
+<gate name="_A01" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
+<gate name="_A02" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
+<gate name="_A03" symbol="ATPIN" x="27.94" y="-27.94" addlevel="always"/>
+<gate name="_A04" symbol="ATPIN" x="27.94" y="-25.4" addlevel="always"/>
+<gate name="_A05" symbol="ATPIN" x="27.94" y="-22.86" addlevel="always"/>
+<gate name="_A06" symbol="ATPIN" x="27.94" y="-20.32" addlevel="always"/>
+<gate name="_A07" symbol="ATPIN" x="27.94" y="-17.78" addlevel="always"/>
+<gate name="_A08" symbol="ATPIN" x="27.94" y="-15.24" addlevel="always"/>
+<gate name="_A09" symbol="ATPIN" x="27.94" y="-12.7" addlevel="always"/>
+<gate name="_A10" symbol="ATPIN" x="27.94" y="-10.16" addlevel="always"/>
+<gate name="_A11" symbol="ATPIN" x="27.94" y="-7.62" addlevel="always"/>
+<gate name="_A12" symbol="ATPIN" x="27.94" y="-5.08" addlevel="always"/>
+<gate name="_A13" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
+<gate name="_A14" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
+<gate name="_A15" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
+<gate name="_RW" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
+<gate name="_NC@1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
+<gate name="_IOSTR\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
+<gate name="_RDY" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
+<gate name="_DMA\" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
+<gate name="_INT_OUT" symbol="ATPIN" x="27.94" y="17.78" addlevel="always"/>
+<gate name="_DMA_OUT" symbol="ATPIN" x="27.94" y="20.32" addlevel="always"/>
+<gate name="_+5V" symbol="ATPIN" x="27.94" y="22.86" addlevel="always"/>
+</gates>
+<devices>
+<device name="SLOT1-3" package="A2-50PIN-SL1-3">
+<connects>
+<connect gate="_+5V" pin="P" pad="25"/>
+<connect gate="_-12V@1" pin="P" pad="33"/>
+<connect gate="_-12V@2" pin="P" pad="50"/>
+<connect gate="_-5V" pin="P" pad="34"/>
+<connect gate="_00" pin="P" pad="40"/>
+<connect gate="_01" pin="P" pad="38"/>
+<connect gate="_7M" pin="P" pad="36"/>
+<connect gate="_A00" pin="P" pad="02"/>
+<connect gate="_A01" pin="P" pad="03"/>
+<connect gate="_A02" pin="P" pad="04"/>
+<connect gate="_A03" pin="P" pad="05"/>
+<connect gate="_A04" pin="P" pad="06"/>
+<connect gate="_A05" pin="P" pad="07"/>
+<connect gate="_A06" pin="P" pad="08"/>
+<connect gate="_A07" pin="P" pad="09"/>
+<connect gate="_A08" pin="P" pad="10"/>
+<connect gate="_A09" pin="P" pad="11"/>
+<connect gate="_A10" pin="P" pad="12"/>
+<connect gate="_A11" pin="P" pad="13"/>
+<connect gate="_A12" pin="P" pad="14"/>
+<connect gate="_A13" pin="P" pad="15"/>
+<connect gate="_A14" pin="P" pad="16"/>
+<connect gate="_A15" pin="P" pad="17"/>
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+<connect gate="_RES\" pin="P" pad="31"/>
+<connect gate="_RW" pin="P" pad="18"/>
+<connect gate="_USER1" pin="P" pad="39"/>
+</connects>
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+</technologies>
+</device>
+<device name="SLOT4-7" package="A2-50PIN-SL4-7">
+<connects>
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+<connect gate="_-5V" pin="P" pad="34"/>
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+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="xilinx-xc9" urn="urn:adsk.eagle:library:416">
+<description>&lt;b&gt;XILINXIn-System Programmable CPLD Family&lt;/b&gt;&lt;p&gt;
+http://www.xilinx.com&lt;br&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;&lt;p&gt;</description>
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+<pin name="FB02/17" x="-10.16" y="30.48" length="middle" rot="R270"/>
+</symbol>
+<symbol name="SUPPLY">
+<text x="-0.635" y="-0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
+<text x="1.905" y="2.54" size="1.27" layer="95" rot="R90">VCCINT</text>
+<pin name="GND@1" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
+<pin name="VCCINT@0" x="-5.08" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
+<pin name="VCCINT@1" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
+<pin name="VCCIO" x="5.08" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
+<pin name="GND@0" x="-5.08" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
+<pin name="GND@2" x="5.08" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
+<text x="-3.175" y="2.54" size="1.27" layer="95" rot="R90">VCCINT</text>
+<text x="6.985" y="2.54" size="1.27" layer="95" rot="R90">VCCIO</text>
+<text x="-3.175" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
+<text x="6.985" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="XC9572_S44">
+<gates>
+<gate name="G$1" symbol="XC9572_PC44" x="0" y="0"/>
+<gate name="SUPPLY" symbol="SUPPLY" x="58.42" y="-2.54" addlevel="request"/>
+</gates>
+<devices>
+<device name="" package="S44">
+<connects>
+<connect gate="G$1" pin="FB01/02" pad="1"/>
+<connect gate="G$1" pin="FB01/05" pad="2"/>
+<connect gate="G$1" pin="FB01/06" pad="3"/>
+<connect gate="G$1" pin="FB01/08" pad="4"/>
+<connect gate="G$1" pin="FB01/09" pad="5"/>
+<connect gate="G$1" pin="FB01/11" pad="6"/>
+<connect gate="G$1" pin="FB01/14" pad="7"/>
+<connect gate="G$1" pin="FB01/15" pad="8"/>
+<connect gate="G$1" pin="FB01/17" pad="9"/>
+<connect gate="G$1" pin="FB02/02" pad="35"/>
+<connect gate="G$1" pin="FB02/05" pad="36"/>
+<connect gate="G$1" pin="FB02/06" pad="37"/>
+<connect gate="G$1" pin="FB02/08" pad="38"/>
+<connect gate="G$1" pin="FB02/09" pad="39"/>
+<connect gate="G$1" pin="FB02/11" pad="40"/>
+<connect gate="G$1" pin="FB02/14" pad="42"/>
+<connect gate="G$1" pin="FB02/15" pad="43"/>
+<connect gate="G$1" pin="FB02/17" pad="44"/>
+<connect gate="G$1" pin="FB03/02" pad="11"/>
+<connect gate="G$1" pin="FB03/05" pad="12"/>
+<connect gate="G$1" pin="FB03/08" pad="13"/>
+<connect gate="G$1" pin="FB03/09" pad="14"/>
+<connect gate="G$1" pin="FB03/11" pad="18"/>
+<connect gate="G$1" pin="FB03/14" pad="19"/>
+<connect gate="G$1" pin="FB03/15" pad="20"/>
+<connect gate="G$1" pin="FB03/16" pad="24"/>
+<connect gate="G$1" pin="FB03/17" pad="22"/>
+<connect gate="G$1" pin="FB04/02" pad="25"/>
+<connect gate="G$1" pin="FB04/05" pad="26"/>
+<connect gate="G$1" pin="FB04/08" pad="27"/>
+<connect gate="G$1" pin="FB04/11" pad="28"/>
+<connect gate="G$1" pin="FB04/14" pad="29"/>
+<connect gate="G$1" pin="FB04/15" pad="33"/>
+<connect gate="G$1" pin="FB04/17" pad="34"/>
+<connect gate="G$1" pin="TCK" pad="17"/>
+<connect gate="G$1" pin="TDI" pad="15"/>
+<connect gate="G$1" pin="TDO" pad="30"/>
+<connect gate="G$1" pin="TMS" pad="16"/>
+<connect gate="SUPPLY" pin="GND@0" pad="10"/>
+<connect gate="SUPPLY" pin="GND@1" pad="23"/>
+<connect gate="SUPPLY" pin="GND@2" pad="31"/>
+<connect gate="SUPPLY" pin="VCCINT@0" pad="21"/>
+<connect gate="SUPPLY" pin="VCCINT@1" pad="41"/>
+<connect gate="SUPPLY" pin="VCCIO" pad="32"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="74xx-eu" urn="urn:adsk.eagle:library:85">
+<description>&lt;b&gt;TTL Devices, 74xx Series with European Symbols&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Texas Instruments &lt;i&gt;TTL Data Book&lt;/i&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Volume 1, 1996.
+&lt;li&gt;TTL Data Book, Volume 2 , 1993
+&lt;li&gt;National Seminconductor Databook 1990, ALS/LS Logic
+&lt;li&gt;ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+&lt;li&gt;http://icmaster.com/ViewCompare.asp
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL20">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="12.7" y1="2.921" x2="-12.7" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="-2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="12.7" y1="2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="2.921" x2="-12.7" y2="1.016" width="0.1524" layer="21"/>
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+<wire x1="-12.7" y1="1.016" x2="-12.7" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
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+<text x="-13.081" y="-3.048" size="1.27" layer="25" rot="R90">&gt;NAME</text>
+<text x="-9.779" y="-0.381" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="SO20W">
+<description>&lt;b&gt;Wide Small Outline package&lt;/b&gt; 300 mil</description>
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+</package>
+<package name="LCC20">
+<description>&lt;b&gt;Leadless Chip Carrier&lt;/b&gt;&lt;p&gt; Ceramic Package</description>
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+<wire x1="-2.9401" y1="4.3985" x2="-2.1399" y2="4.3985" width="0.2032" layer="51" curve="180"/>
+<wire x1="-1.6701" y1="4.4" x2="-2.14" y2="4.4" width="0.2032" layer="51"/>
+<wire x1="-4.3985" y1="-2.9401" x2="-4.3985" y2="-2.1399" width="0.2032" layer="51" curve="180"/>
+<wire x1="-4.4" y1="-1.6701" x2="-4.4" y2="-2.14" width="0.2032" layer="51"/>
+<wire x1="1.6701" y1="-4.4" x2="2.14" y2="-4.4" width="0.2032" layer="51"/>
+<wire x1="2.14" y1="-4.3985" x2="2.94" y2="-4.3985" width="0.2032" layer="51" curve="-180"/>
+<wire x1="4.3985" y1="2.9401" x2="4.3985" y2="2.1399" width="0.2032" layer="51" curve="180"/>
+<wire x1="4.4" y1="1.6701" x2="4.4" y2="2.14" width="0.2032" layer="51"/>
+<wire x1="-3.3" y1="4.4" x2="-4.4" y2="3.3" width="0.2032" layer="21"/>
+<wire x1="-4.4" y1="-3.1941" x2="-4.4" y2="-4.4" width="0.2032" layer="21"/>
+<wire x1="-4.4" y1="-4.4" x2="-3.1941" y2="-4.4" width="0.2032" layer="21"/>
+<wire x1="3.1941" y1="-4.4" x2="4.4" y2="-4.4" width="0.2032" layer="21"/>
+<wire x1="4.4" y1="-4.4" x2="4.4" y2="-3.1941" width="0.2032" layer="21"/>
+<wire x1="4.4" y1="3.1941" x2="4.4" y2="4.4" width="0.2032" layer="21"/>
+<wire x1="4.4" y1="4.4" x2="3.1941" y2="4.4" width="0.2032" layer="21"/>
+<smd name="2" x="-1.27" y="4.5001" dx="0.8" dy="2" layer="1"/>
+<smd name="1" x="0" y="3.8001" dx="0.8" dy="3.4" layer="1"/>
+<smd name="3" x="-2.54" y="4.5001" dx="0.8" dy="2" layer="1"/>
+<smd name="4" x="-4.5001" y="2.54" dx="2" dy="0.8" layer="1"/>
+<smd name="5" x="-4.5001" y="1.27" dx="2" dy="0.8" layer="1"/>
+<smd name="6" x="-4.5001" y="0" dx="2" dy="0.8" layer="1"/>
+<smd name="7" x="-4.5001" y="-1.27" dx="2" dy="0.8" layer="1"/>
+<smd name="8" x="-4.5001" y="-2.54" dx="2" dy="0.8" layer="1"/>
+<smd name="9" x="-2.54" y="-4.5001" dx="0.8" dy="2" layer="1"/>
+<smd name="10" x="-1.27" y="-4.5001" dx="0.8" dy="2" layer="1"/>
+<smd name="11" x="0" y="-4.5001" dx="0.8" dy="2" layer="1"/>
+<smd name="12" x="1.27" y="-4.5001" dx="0.8" dy="2" layer="1"/>
+<smd name="13" x="2.54" y="-4.5001" dx="0.8" dy="2" layer="1"/>
+<smd name="14" x="4.5001" y="-2.54" dx="2" dy="0.8" layer="1"/>
+<smd name="15" x="4.5001" y="-1.27" dx="2" dy="0.8" layer="1"/>
+<smd name="16" x="4.5001" y="0" dx="2" dy="0.8" layer="1"/>
+<smd name="17" x="4.5001" y="1.27" dx="2" dy="0.8" layer="1"/>
+<smd name="18" x="4.5001" y="2.54" dx="2" dy="0.8" layer="1"/>
+<smd name="19" x="2.54" y="4.5001" dx="0.8" dy="2" layer="1"/>
+<smd name="20" x="1.27" y="4.5001" dx="0.8" dy="2" layer="1"/>
+<text x="-4.0051" y="6.065" size="1.778" layer="25">&gt;NAME</text>
+<text x="-3.9751" y="-7.5601" size="1.778" layer="27">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="74245">
+<wire x1="-7.62" y1="-15.24" x2="7.62" y2="-15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="-15.24" x2="7.62" y2="15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="15.24" x2="-7.62" y2="15.24" width="0.4064" layer="94"/>
+<wire x1="-7.62" y1="15.24" x2="-7.62" y2="-15.24" width="0.4064" layer="94"/>
+<text x="-7.62" y="15.875" size="1.778" layer="95">&gt;NAME</text>
+<text x="-7.62" y="-17.78" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="DIR" x="-12.7" y="-10.16" length="middle" direction="in"/>
+<pin name="A1" x="-12.7" y="12.7" length="middle"/>
+<pin name="A2" x="-12.7" y="10.16" length="middle"/>
+<pin name="A3" x="-12.7" y="7.62" length="middle"/>
+<pin name="A4" x="-12.7" y="5.08" length="middle"/>
+<pin name="A5" x="-12.7" y="2.54" length="middle"/>
+<pin name="A6" x="-12.7" y="0" length="middle"/>
+<pin name="A7" x="-12.7" y="-2.54" length="middle"/>
+<pin name="A8" x="-12.7" y="-5.08" length="middle"/>
+<pin name="B8" x="12.7" y="-5.08" length="middle" rot="R180"/>
+<pin name="B7" x="12.7" y="-2.54" length="middle" rot="R180"/>
+<pin name="B6" x="12.7" y="0" length="middle" rot="R180"/>
+<pin name="B5" x="12.7" y="2.54" length="middle" rot="R180"/>
+<pin name="B4" x="12.7" y="5.08" length="middle" rot="R180"/>
+<pin name="B3" x="12.7" y="7.62" length="middle" rot="R180"/>
+<pin name="B2" x="12.7" y="10.16" length="middle" rot="R180"/>
+<pin name="B1" x="12.7" y="12.7" length="middle" rot="R180"/>
+<pin name="G" x="-12.7" y="-12.7" length="middle" direction="in" function="dot"/>
+</symbol>
+<symbol name="PWRN">
+<text x="-0.635" y="-0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
+<text x="1.905" y="2.54" size="1.27" layer="95" rot="R90">VCC</text>
+<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
+<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="74*245" prefix="IC">
+<description>Octal &lt;b&gt;BUS TRANSCEIVER&lt;/b&gt;, 3-state</description>
+<gates>
+<gate name="A" symbol="74245" x="20.32" y="0"/>
+<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="N" package="DIL20">
+<connects>
+<connect gate="A" pin="A1" pad="2"/>
+<connect gate="A" pin="A2" pad="3"/>
+<connect gate="A" pin="A3" pad="4"/>
+<connect gate="A" pin="A4" pad="5"/>
+<connect gate="A" pin="A5" pad="6"/>
+<connect gate="A" pin="A6" pad="7"/>
+<connect gate="A" pin="A7" pad="8"/>
+<connect gate="A" pin="A8" pad="9"/>
+<connect gate="A" pin="B1" pad="18"/>
+<connect gate="A" pin="B2" pad="17"/>
+<connect gate="A" pin="B3" pad="16"/>
+<connect gate="A" pin="B4" pad="15"/>
+<connect gate="A" pin="B5" pad="14"/>
+<connect gate="A" pin="B6" pad="13"/>
+<connect gate="A" pin="B7" pad="12"/>
+<connect gate="A" pin="B8" pad="11"/>
+<connect gate="A" pin="DIR" pad="1"/>
+<connect gate="A" pin="G" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+</technologies>
+</device>
+<device name="DW" package="SO20W">
+<connects>
+<connect gate="A" pin="A1" pad="2"/>
+<connect gate="A" pin="A2" pad="3"/>
+<connect gate="A" pin="A3" pad="4"/>
+<connect gate="A" pin="A4" pad="5"/>
+<connect gate="A" pin="A5" pad="6"/>
+<connect gate="A" pin="A6" pad="7"/>
+<connect gate="A" pin="A7" pad="8"/>
+<connect gate="A" pin="A8" pad="9"/>
+<connect gate="A" pin="B1" pad="18"/>
+<connect gate="A" pin="B2" pad="17"/>
+<connect gate="A" pin="B3" pad="16"/>
+<connect gate="A" pin="B4" pad="15"/>
+<connect gate="A" pin="B5" pad="14"/>
+<connect gate="A" pin="B6" pad="13"/>
+<connect gate="A" pin="B7" pad="12"/>
+<connect gate="A" pin="B8" pad="11"/>
+<connect gate="A" pin="DIR" pad="1"/>
+<connect gate="A" pin="G" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+</technologies>
+</device>
+<device name="FK" package="LCC20">
+<connects>
+<connect gate="A" pin="A1" pad="2"/>
+<connect gate="A" pin="A2" pad="3"/>
+<connect gate="A" pin="A3" pad="4"/>
+<connect gate="A" pin="A4" pad="5"/>
+<connect gate="A" pin="A5" pad="6"/>
+<connect gate="A" pin="A6" pad="7"/>
+<connect gate="A" pin="A7" pad="8"/>
+<connect gate="A" pin="A8" pad="9"/>
+<connect gate="A" pin="B1" pad="18"/>
+<connect gate="A" pin="B2" pad="17"/>
+<connect gate="A" pin="B3" pad="16"/>
+<connect gate="A" pin="B4" pad="15"/>
+<connect gate="A" pin="B5" pad="14"/>
+<connect gate="A" pin="B6" pad="13"/>
+<connect gate="A" pin="B7" pad="12"/>
+<connect gate="A" pin="B8" pad="11"/>
+<connect gate="A" pin="DIR" pad="1"/>
+<connect gate="A" pin="G" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="v-reg" urn="urn:adsk.eagle:library:409">
+<description>&lt;b&gt;Voltage Regulators&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="317TL">
+<description>&lt;b&gt;VOLTAGE REGULATOR&lt;/b&gt;</description>
+<wire x1="-5.207" y1="-1.27" x2="5.207" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="14.605" x2="-5.207" y2="14.605" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="-1.27" x2="5.207" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="11.176" x2="4.318" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="4.318" y1="11.176" x2="4.318" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="4.318" y1="12.7" x2="5.207" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="5.207" y1="12.7" x2="5.207" y2="14.605" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="-1.27" x2="-5.207" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="11.176" x2="-4.318" y2="11.176" width="0.1524" layer="21"/>
+<wire x1="-4.318" y1="11.176" x2="-4.318" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="-4.318" y1="12.7" x2="-5.207" y2="12.7" width="0.1524" layer="21"/>
+<wire x1="-5.207" y1="12.7" x2="-5.207" y2="14.605" width="0.1524" layer="21"/>
+<wire x1="-4.572" y1="-0.635" x2="4.572" y2="-0.635" width="0.0508" layer="21"/>
+<wire x1="4.572" y1="7.62" x2="4.572" y2="-0.635" width="0.0508" layer="21"/>
+<wire x1="4.572" y1="7.62" x2="-4.572" y2="7.62" width="0.0508" layer="21"/>
+<wire x1="-4.572" y1="-0.635" x2="-4.572" y2="7.62" width="0.0508" layer="21"/>
+<circle x="0" y="11.176" radius="1.8034" width="0.1524" layer="21"/>
+<circle x="0" y="11.176" radius="4.191" width="0" layer="42"/>
+<circle x="0" y="11.176" radius="4.191" width="0" layer="43"/>
+<pad name="1" x="-2.54" y="-3.81" drill="1.016" shape="long" rot="R90"/>
+<pad name="2" x="0" y="-3.81" drill="1.016" shape="long" rot="R90"/>
+<pad name="3" x="2.54" y="-3.81" drill="1.016" shape="long" rot="R90"/>
+<text x="-3.81" y="5.08" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-3.937" y="2.54" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-4.445" y="7.874" size="0.9906" layer="21" ratio="10">A15,2mm</text>
+<text x="-0.508" y="0" size="1.27" layer="51" ratio="10">O</text>
+<text x="2.032" y="0" size="1.27" layer="51" ratio="10">I</text>
+<text x="-3.048" y="0" size="1.27" layer="51" ratio="10">A</text>
+<rectangle x1="1.905" y1="-2.159" x2="3.175" y2="-1.27" layer="21"/>
+<rectangle x1="1.905" y1="-3.81" x2="3.175" y2="-2.159" layer="51"/>
+<rectangle x1="-0.635" y1="-2.159" x2="0.635" y2="-1.27" layer="21"/>
+<rectangle x1="-3.175" y1="-2.159" x2="-1.905" y2="-1.27" layer="21"/>
+<rectangle x1="-0.635" y1="-3.81" x2="0.635" y2="-2.159" layer="51"/>
+<rectangle x1="-3.175" y1="-3.81" x2="-1.905" y2="-2.159" layer="51"/>
+<hole x="0" y="11.176" drill="3.302"/>
+</package>
+</packages>
+<symbols>
+<symbol name="78ADJ">
+<wire x1="-5.08" y1="-5.08" x2="5.08" y2="-5.08" width="0.4064" layer="94"/>
+<wire x1="5.08" y1="-5.08" x2="5.08" y2="2.54" width="0.4064" layer="94"/>
+<wire x1="5.08" y1="2.54" x2="-5.08" y2="2.54" width="0.4064" layer="94"/>
+<wire x1="-5.08" y1="2.54" x2="-5.08" y2="-5.08" width="0.4064" layer="94"/>
+<text x="2.54" y="-7.62" size="1.778" layer="95">&gt;NAME</text>
+<text x="2.54" y="-10.16" size="1.778" layer="96">&gt;VALUE</text>
+<text x="-2.032" y="-4.318" size="1.524" layer="95">ADJ</text>
+<text x="-4.445" y="-0.635" size="1.524" layer="95">IN</text>
+<text x="0.127" y="-0.635" size="1.524" layer="95">OUT</text>
+<pin name="IN" x="-7.62" y="0" visible="off" length="short" direction="in"/>
+<pin name="ADJ" x="0" y="-7.62" visible="off" length="short" direction="in" rot="R90"/>
+<pin name="OUT" x="7.62" y="0" visible="off" length="short" direction="pas" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LM317TL" prefix="IC" uservalue="yes">
+<description>&lt;b&gt;VOLTAGE REGULATOR&lt;/b&gt;</description>
+<gates>
+<gate name="A" symbol="78ADJ" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="317TL">
+<connects>
+<connect gate="A" pin="ADJ" pad="1"/>
+<connect gate="A" pin="IN" pad="3"/>
+<connect gate="A" pin="OUT" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="rcl" urn="urn:adsk.eagle:library:334">
+<description>&lt;b&gt;Resistors, Capacitors, Inductors&lt;/b&gt;&lt;p&gt;
+Based on the previous libraries:
+&lt;ul&gt;
+&lt;li&gt;r.lbr
+&lt;li&gt;cap.lbr 
+&lt;li&gt;cap-fe.lbr
+&lt;li&gt;captant.lbr
+&lt;li&gt;polcap.lbr
+&lt;li&gt;ipc-smd.lbr
+&lt;/ul&gt;
+All SMD packages are defined according to the IPC specifications and  CECC&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;&lt;p&gt;
+&lt;p&gt;
+for Electrolyt Capacitors see also :&lt;p&gt;
+www.bccomponents.com &lt;p&gt;
+www.panasonic.com&lt;p&gt;
+www.kemet.com&lt;p&gt;
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf &lt;b&gt;(SANYO)&lt;/b&gt;
+&lt;p&gt;
+for trimmer refence see : &lt;u&gt;www.electrospec-inc.com/cross_references/trimpotcrossref.asp&lt;/u&gt;&lt;p&gt;
+
+&lt;table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0&gt;
+&lt;tr valign="top"&gt;
+
+&lt;! &lt;td width="10"&gt;&amp;nbsp;&lt;/td&gt;
+&lt;td width="90%"&gt;
+
+&lt;b&gt;&lt;font color="#0000FF" size="4"&gt;TRIM-POT CROSS REFERENCE&lt;/font&gt;&lt;/b&gt;
+&lt;P&gt;
+&lt;TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2&gt;
+  &lt;TR&gt;
+    &lt;TD COLSPAN=8&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;RECTANGULAR MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BOURNS&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BI&amp;nbsp;TECH&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;DALE-VISHAY&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PHILIPS/MEPCO&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MURATA&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PANASONIC&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;SPECTROL&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;
+    &lt;TD ALIGN=CENTER&gt;
+      &lt;B&gt;
+      &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MILSPEC&lt;/FONT&gt;
+      &lt;/B&gt;
+    &lt;/TD&gt;&lt;TD&gt;&amp;nbsp;&lt;/TD&gt;
+  &lt;/TR&gt;
+  &lt;TR&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3 &gt;
+      3005P&lt;BR&gt;
+      3006P&lt;BR&gt;
+      3006W&lt;BR&gt;
+      3006Y&lt;BR&gt;
+      3009P&lt;BR&gt;
+      3009W&lt;BR&gt;
+      3009Y&lt;BR&gt;
+      3057J&lt;BR&gt;
+      3057L&lt;BR&gt;
+      3057P&lt;BR&gt;
+      3057Y&lt;BR&gt;
+      3059J&lt;BR&gt;
+      3059L&lt;BR&gt;
+      3059P&lt;BR&gt;
+      3059Y&lt;BR&gt;&lt;/FONT&gt;
+    &lt;/TD&gt;
+    &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+      -&lt;BR&gt;
+      89P&lt;BR&gt;
+      89W&lt;BR&gt;
+      89X&lt;BR&gt;
+      89PH&lt;BR&gt;
+      76P&lt;BR&gt;
+      89XH&lt;BR&gt;
+      78SLT&lt;BR&gt;
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+Source: VISHAY .. vta56.pdf</description>
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+Source: VISHAY .. vta56.pdf</description>
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+Source: VISHAY .. vta56.pdf</description>
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+Source: VISHAY .. vta56.pdf</description>
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+Source: VISHAY .. vta56.pdf</description>
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+Source: VISHAY .. vta56.pdf</description>
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+<description>&lt;b&gt;Wirewound Resistors, Precision Power&lt;/b&gt;&lt;p&gt;
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+<package name="R1218">
+<description>&lt;b&gt;CRCW1218 Thick Film, Rectangular Chip Resistors&lt;/b&gt;&lt;p&gt;
+Source: http://www.vishay.com .. dcrcw.pdf</description>
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+<package name="1812X7R">
+<description>&lt;b&gt;Chip Monolithic Ceramic Capacitors&lt;/b&gt; Medium Voltage High Capacitance for General Use&lt;p&gt;
+Source: http://www.murata.com .. GRM43DR72E224KW01.pdf</description>
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+<description>&lt;b&gt;PRL1632 are realized as 1W for 3.2 × 1.6mm(1206)&lt;/b&gt;&lt;p&gt;
+Source: http://www.mouser.com/ds/2/392/products_18-2245.pdf</description>
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+<device name="225-087X268" package="C225-087X268">
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+<device name="225-108X268" package="C225-108X268">
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+<device name="225-113X268" package="C225-113X268">
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+<device name="275-093X316" package="C275-093X316">
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+<device name="325-137X374" package="C325-137X374">
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+<device name="325-162X374" package="C325-162X374">
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+<device name="375-192X418" package="C375-192X418">
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+<device name="050-035X075" package="C050-035X075">
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+<connect gate="G$1" pin="1" pad="1"/>
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+<device name="075-063X106" package="C075-063X106">
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+<device name="275-173X316" package="C275-173X316">
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+<device name="C0402K" package="C0402K">
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+<deviceset name="CPOL-EU" prefix="C" uservalue="yes">
+<description>&lt;B&gt;POLARIZED CAPACITOR&lt;/B&gt;, European symbol</description>
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+<gate name="G$1" symbol="CPOL" x="0" y="0"/>
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+</technologies>
+</device>
+<device name="SMCP" package="SMC_P">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SMCB" package="SMC_B">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SMCC" package="SMC_C">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SMCD" package="SMC_D">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SMCE" package="SMC_E">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_9E" package="SANYO-OSCON_9E">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_9F" package="SANYO-OSCON_9F">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_A" package="SANYO-OSCON_A">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_A'" package="SANYO-OSCON_A'">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_B" package="SANYO-OSCON_B">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_B'" package="SANYO-OSCON_B'">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_C" package="SANYO-OSCON_C">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_C'" package="SANYO-OSCON_C'">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_C6" package="SANYO-OSCON_C6">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_D" package="SANYO-OSCON_D">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_E" package="SANYO-OSCON_E">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_E'" package="SANYO-OSCON_E'">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_E1" package="SANYO-OSCON_E1">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_E12" package="SANYO-OSCON_E12">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_E13" package="SANYO-OSCON_E13">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_E7" package="SANYO-OSCON_E7">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_E9" package="SANYO-OSCON_E9">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_F" package="SANYO-OSCON_F">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_F'" package="SANYO-OSCON_F'">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_F0" package="SANYO-OSCON_F0">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_F13" package="SANYO-OSCON_F13">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_F8" package="SANYO-OSCON_F8">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_G" package="SANYO-OSCON_G">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_H" package="SANYO-OSCON_H">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_SMD_A5" package="SANYO-OSCON_SMD_A5">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_SMD_B6" package="SANYO-OSCON_SMD_B6">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_SMD_C6" package="SANYO-OSCON_SMD_C6">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_SMD_E12" package="SANYO-OSCON_SMD_E12">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_SMD_E7" package="SANYO-OSCON_SMD_E7">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_SMD_F12" package="SANYO-OSCON_SMD_F12">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SANYO_SMD_F8" package="SANYO-OSCON_SMD_F8">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="UD-10X10" package="UD-10X10_NICHICON">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="UD-4X5,8" package="UD-4X5,8_NICHICON">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="UD-5X5,8" package="UD-5X5,8_NICHICON">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="UD-6,3X8,8" package="UD-6,3X5,8_NICHICON">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="UD-6,3X7,7" package="UD-6,3X7,7_NICHICON">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="UD-8X10" package="UD-8X10_NICHICON">
+<connects>
+<connect gate="G$1" pin="+" pad="+"/>
+<connect gate="G$1" pin="-" pad="-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="R-EU_" prefix="R" uservalue="yes">
+<description>&lt;B&gt;RESISTOR&lt;/B&gt;, European symbol</description>
+<gates>
+<gate name="G$1" symbol="R-EU" x="0" y="0"/>
+</gates>
+<devices>
+<device name="R0402" package="R0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R0603" package="R0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R0805" package="R0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R0805W" package="R0805W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R1206" package="R1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R1206W" package="R1206W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R1210" package="R1210">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R1210W" package="R1210W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2010" package="R2010">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2010W" package="R2010W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2012" package="R2012">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2012W" package="R2012W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2512" package="R2512">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R2512W" package="R2512W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R3216" package="R3216">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R3216W" package="R3216W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R3225" package="R3225">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R3225W" package="R3225W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R5025" package="R5025">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R5025W" package="R5025W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R6332" package="R6332">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R6332W" package="R6332W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M0805" package="M0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M1206" package="M1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M1406" package="M1406">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M2012" package="M2012">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M2309" package="M2309">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M3216" package="M3216">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M3516" package="M3516">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="M5923" package="M5923">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0204/5" package="0204/5">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0204/7" package="0204/7">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0204/2V" package="0204V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/10" package="0207/10">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/12" package="0207/12">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/15" package="0207/15">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/2V" package="0207/2V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/5V" package="0207/5V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0207/7" package="0207/7">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0309/10" package="0309/10">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0309/12" package="0309/12">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0309/V" package="0309V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0411/12" package="0411/12">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0411/15" package="0411/15">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0411/3V" package="0411V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0414/15" package="0414/15">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0414/5V" package="0414V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0617/17" package="0617/17">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0617/22" package="0617/22">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0617/5V" package="0617V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0922/22" package="0922/22">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0613/5V" package="P0613V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0613/15" package="P0613/15">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0817/22" package="P0817/22">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0817/7V" package="P0817V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="V234/12" package="V234/12">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="V235/17" package="V235/17">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="V526-0" package="V526-0">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0102R" package="MINI_MELF-0102R">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0102W" package="MINI_MELF-0102W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0204R" package="MINI_MELF-0204R">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0204W" package="MINI_MELF-0204W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0207R" package="MINI_MELF-0207R">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0207W" package="MINI_MELF-0207W">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0922V" package="0922V">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="RDH/15" package="RDH/15">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MELF0102AX" package="MINI_MELF-0102AX">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R0201" package="R0201">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VTA52" package="VTA52">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VTA53" package="VTA53">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VTA54" package="VTA54">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VTA55" package="VTA55">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VTA56" package="VTA56">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VMTA55" package="VMTA55">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="VMTB60" package="VMTB60">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R4527" package="R4527">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC0001" package="WSC0001">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC0002" package="WSC0002">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC01/2" package="WSC01/2">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC2515" package="WSC2515">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC4527" package="WSC4527">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="WSC6927" package="WSC6927">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="R1218" package="R1218">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="1812X7R" package="1812X7R">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="PRL1632" package="PRL1632">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="01005" package="R01005">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="supply1" urn="urn:adsk.eagle:library:371">
+<description>&lt;b&gt;Supply Symbols&lt;/b&gt;&lt;p&gt;
+ GND, VCC, 0V, +5V, -5V, etc.&lt;p&gt;
+ Please keep in mind, that these devices are necessary for the
+ automatic wiring of the supply signals.&lt;p&gt;
+ The pin name defined in the symbol is identical to the net which is to be wired automatically.&lt;p&gt;
+ In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.&lt;p&gt;
+ &lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="+3V3">
+<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/>
+<text x="-2.54" y="-5.08" size="1.778" layer="96" rot="R90">&gt;VALUE</text>
+<pin name="+3V3" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="+5V">
+<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/>
+<text x="-2.54" y="-5.08" size="1.778" layer="96" rot="R90">&gt;VALUE</text>
+<pin name="+5V" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="-2.54" y="-2.54" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="+3V3" prefix="+3V3">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="+3V3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="+5V" prefix="P+">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="1" symbol="+5V" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="GND" prefix="GND">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="led" urn="urn:adsk.eagle:library:259">
+<description>&lt;b&gt;LEDs&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;&lt;br&gt;
+Extended by Federico Battaglin &lt;author&gt;&amp;lt;federico.rd@fdpinternational.com&amp;gt;&lt;/author&gt; with DUOLED</description>
+<packages>
+<package name="1206">
+<description>&lt;b&gt;CHICAGO MINIATURE LAMP, INC.&lt;/b&gt;&lt;p&gt;
+7022X Series SMT LEDs 1206 Package Size</description>
+<wire x1="1.55" y1="-0.75" x2="-1.55" y2="-0.75" width="0.1016" layer="51"/>
+<wire x1="-1.55" y1="-0.75" x2="-1.55" y2="0.75" width="0.1016" layer="51"/>
+<wire x1="-1.55" y1="0.75" x2="1.55" y2="0.75" width="0.1016" layer="51"/>
+<wire x1="1.55" y1="0.75" x2="1.55" y2="-0.75" width="0.1016" layer="51"/>
+<wire x1="-0.55" y1="-0.5" x2="0.55" y2="-0.5" width="0.1016" layer="21" curve="95.452622"/>
+<wire x1="-0.55" y1="-0.5" x2="-0.55" y2="0.5" width="0.1016" layer="51" curve="-84.547378"/>
+<wire x1="-0.55" y1="0.5" x2="0.55" y2="0.5" width="0.1016" layer="21" curve="-95.452622"/>
+<wire x1="0.55" y1="0.5" x2="0.55" y2="-0.5" width="0.1016" layer="51" curve="-84.547378"/>
+<smd name="A" x="-1.422" y="0" dx="1.6" dy="1.803" layer="1"/>
+<smd name="C" x="1.422" y="0" dx="1.6" dy="1.803" layer="1"/>
+<text x="-1.27" y="1.27" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1.27" y="-2.54" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.1" y1="-0.1" x2="0.1" y2="0.1" layer="21"/>
+<rectangle x1="0.45" y1="-0.7" x2="0.8" y2="-0.45" layer="51"/>
+<rectangle x1="0.8" y1="-0.7" x2="0.9" y2="0.5" layer="51"/>
+<rectangle x1="0.8" y1="0.55" x2="0.9" y2="0.7" layer="51"/>
+<rectangle x1="-0.9" y1="-0.7" x2="-0.8" y2="0.5" layer="51"/>
+<rectangle x1="-0.9" y1="0.55" x2="-0.8" y2="0.7" layer="51"/>
+<rectangle x1="0.45" y1="-0.7" x2="0.6" y2="-0.45" layer="21"/>
+</package>
+<package name="LD260">
+<description>&lt;B&gt;LED&lt;/B&gt;&lt;p&gt;
+5 mm, square, Siemens</description>
+<wire x1="-1.27" y1="-1.27" x2="0" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0" y1="-1.27" x2="1.27" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="1.27" x2="0" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="0" y1="1.27" x2="-1.27" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-1.27" x2="1.27" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="1.27" x2="1.27" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.889" x2="1.27" y2="0" width="0.1524" layer="51"/>
+<wire x1="1.27" y1="0" x2="1.27" y2="-0.889" width="0.1524" layer="51"/>
+<wire x1="-1.27" y1="1.27" x2="-1.27" y2="0.889" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="-1.27" x2="-1.27" y2="-0.889" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="-0.889" x2="-1.27" y2="0" width="0.1524" layer="51"/>
+<wire x1="-1.27" y1="0" x2="-1.27" y2="0.889" width="0.1524" layer="51"/>
+<wire x1="0" y1="1.27" x2="0.9917" y2="0.7934" width="0.1524" layer="21" curve="-51.33923"/>
+<wire x1="-0.9917" y1="0.7934" x2="0" y2="1.27" width="0.1524" layer="21" curve="-51.33923"/>
+<wire x1="0" y1="-1.27" x2="0.9917" y2="-0.7934" width="0.1524" layer="21" curve="51.33923"/>
+<wire x1="-0.9917" y1="-0.7934" x2="0" y2="-1.27" width="0.1524" layer="21" curve="51.33923"/>
+<wire x1="0.9558" y1="-0.8363" x2="1.27" y2="0" width="0.1524" layer="51" curve="41.185419"/>
+<wire x1="0.9756" y1="0.813" x2="1.2699" y2="0" width="0.1524" layer="51" curve="-39.806332"/>
+<wire x1="-1.27" y1="0" x2="-0.9643" y2="-0.8265" width="0.1524" layer="51" curve="40.600331"/>
+<wire x1="-1.27" y1="0" x2="-0.9643" y2="0.8265" width="0.1524" layer="51" curve="-40.600331"/>
+<wire x1="-0.889" y1="0" x2="0" y2="0.889" width="0.1524" layer="51" curve="-90"/>
+<wire x1="-0.508" y1="0" x2="0" y2="0.508" width="0.1524" layer="51" curve="-90"/>
+<wire x1="0" y1="-0.508" x2="0.508" y2="0" width="0.1524" layer="21" curve="90"/>
+<wire x1="0" y1="-0.889" x2="0.889" y2="0" width="0.1524" layer="51" curve="90"/>
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+<package name="LED10MM">
+<description>&lt;B&gt;LED&lt;/B&gt;&lt;p&gt;
+10 mm, round</description>
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+</package>
+<package name="KA-3528ASYC">
+<description>&lt;b&gt;SURFACE MOUNT LED LAMP&lt;/b&gt; 3.5x2.8mm&lt;p&gt;
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+</package>
+<package name="SML0805">
+<description>&lt;b&gt;SML0805-2CW-TR (0805 PROFILE)&lt;/b&gt; COOL WHITE&lt;p&gt;
+Source: http://www.ledtronics.com/ds/smd-0603/Dstr0093.pdf</description>
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+<text x="-1.5" y="-2" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="SML1206">
+<description>&lt;b&gt;SML10XXKH-TR (HIGH INTENSITY) LED&lt;/b&gt;&lt;p&gt;
+&lt;table&gt;
+&lt;tr&gt;&lt;td&gt;SML10R3KH-TR&lt;/td&gt;&lt;td&gt;ULTRA RED&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10E3KH-TR&lt;/td&gt;&lt;td&gt;SUPER REDSUPER BLUE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10O3KH-TR&lt;/td&gt;&lt;td&gt;SUPER ORANGE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10PY3KH-TR&lt;/td&gt;&lt;td&gt;PURE YELLOW&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10OY3KH-TR&lt;/td&gt;&lt;td&gt;ULTRA YELLOW&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10AG3KH-TR&lt;/td&gt;&lt;td&gt;AQUA GREEN&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10BG3KH-TR&lt;/td&gt;&lt;td&gt;BLUE GREEN&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10PB1KH-TR&lt;/td&gt;&lt;td&gt;SUPER BLUE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;SML10CW1KH-TR&lt;/td&gt;&lt;td&gt;WHITE&lt;/td&gt;&lt;/tr&gt;
+&lt;/table&gt;
+
+Source: http://www.ledtronics.com/ds/smd-1206/dstr0094.PDF</description>
+<wire x1="-1.5" y1="0.5" x2="-1.5" y2="-0.5" width="0.2032" layer="51" curve="-180"/>
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+<rectangle x1="-0.1" y1="-0.1" x2="0.1" y2="0.1" layer="21"/>
+</package>
+<package name="SML0603">
+<description>&lt;b&gt;SML0603-XXX (HIGH INTENSITY) LED&lt;/b&gt;&lt;p&gt;
+&lt;table&gt;
+&lt;tr&gt;&lt;td&gt;AG3K&lt;/td&gt;&lt;td&gt;AQUA GREEN&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;B1K&lt;/td&gt;&lt;td&gt;SUPER BLUE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;R1K&lt;/td&gt;&lt;td&gt;SUPER RED&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;R3K&lt;/td&gt;&lt;td&gt;ULTRA RED&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;O3K&lt;/td&gt;&lt;td&gt;SUPER ORANGE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;O3KH&lt;/td&gt;&lt;td&gt;SOFT ORANGE&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;Y3KH&lt;/td&gt;&lt;td&gt;SUPER YELLOW&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;Y3K&lt;/td&gt;&lt;td&gt;SUPER YELLOW&lt;/td&gt;&lt;/tr&gt;
+&lt;tr&gt;&lt;td&gt;2CW&lt;/td&gt;&lt;td&gt;WHITE&lt;/td&gt;&lt;/tr&gt;
+&lt;/table&gt;
+Source: http://www.ledtronics.com/ds/smd-0603/Dstr0092.pdf</description>
+<wire x1="-0.75" y1="0.35" x2="0.75" y2="0.35" width="0.1016" layer="51"/>
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+<wire x1="0.45" y1="0.3" x2="0.45" y2="-0.3" width="0.1016" layer="51"/>
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+<smd name="A" x="0.75" y="0" dx="0.8" dy="0.8" layer="1"/>
+<text x="-1" y="1" size="1.27" layer="25">&gt;NAME</text>
+<text x="-1" y="-2" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.4" y1="0.175" x2="0" y2="0.4" layer="51"/>
+<rectangle x1="-0.25" y1="0.175" x2="0" y2="0.4" layer="21"/>
+</package>
+</packages>
+<symbols>
+<symbol name="LED">
+<wire x1="1.27" y1="0" x2="0" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="0" y1="-2.54" x2="-1.27" y2="0" width="0.254" layer="94"/>
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+<wire x1="1.27" y1="0" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="0" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="-2.032" y1="-0.762" x2="-3.429" y2="-2.159" width="0.1524" layer="94"/>
+<wire x1="-1.905" y1="-1.905" x2="-3.302" y2="-3.302" width="0.1524" layer="94"/>
+<text x="3.556" y="-4.572" size="1.778" layer="95" rot="R90">&gt;NAME</text>
+<text x="5.715" y="-4.572" size="1.778" layer="96" rot="R90">&gt;VALUE</text>
+<pin name="C" x="0" y="-5.08" visible="off" length="short" direction="pas" rot="R90"/>
+<pin name="A" x="0" y="2.54" visible="off" length="short" direction="pas" rot="R270"/>
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+<vertex x="-2.921" y="-2.413"/>
+<vertex x="-2.413" y="-2.921"/>
+</polygon>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="LED" prefix="LED" uservalue="yes">
+<description>&lt;b&gt;LED&lt;/b&gt;&lt;p&gt;
+&lt;u&gt;OSRAM&lt;/u&gt;:&lt;br&gt;
+
+- &lt;u&gt;CHIPLED&lt;/u&gt;&lt;br&gt;
+LG R971, LG N971, LY N971, LG Q971, LY Q971, LO R971, LY R971
+LH N974, LH R974&lt;br&gt;
+LS Q976, LO Q976, LY Q976&lt;br&gt;
+LO Q996&lt;br&gt;
+
+- &lt;u&gt;Hyper CHIPLED&lt;/u&gt;&lt;br&gt;
+LW Q18S&lt;br&gt;
+LB Q993, LB Q99A, LB R99A&lt;br&gt;
+
+- &lt;u&gt;SideLED&lt;/u&gt;&lt;br&gt;
+LS A670, LO A670, LY A670, LG A670, LP A670&lt;br&gt;
+LB A673, LV A673, LT A673, LW A673&lt;br&gt;
+LH A674&lt;br&gt;
+LY A675&lt;br&gt;
+LS A676, LA A676, LO A676, LY A676, LW A676&lt;br&gt;
+LS A679, LY A679, LG A679&lt;br&gt;
+
+-  &lt;u&gt;Hyper Micro SIDELED®&lt;/u&gt;&lt;br&gt;
+LS Y876, LA Y876, LO Y876, LY Y876&lt;br&gt;
+LT Y87S&lt;br&gt;
+
+- &lt;u&gt;SmartLED&lt;/u&gt;&lt;br&gt;
+LW L88C, LW L88S&lt;br&gt;
+LB L89C, LB L89S, LG L890&lt;br&gt;
+LS L89K, LO L89K, LY L89K&lt;br&gt;
+LS L896, LA L896, LO L896, LY L896&lt;br&gt;
+
+- &lt;u&gt;TOPLED&lt;/u&gt;&lt;br&gt;
+LS T670, LO T670, LY T670, LG T670, LP T670&lt;br&gt;
+LSG T670, LSP T670, LSY T670, LOP T670, LYG T670&lt;br&gt;
+LG T671, LOG T671, LSG T671&lt;br&gt;
+LB T673, LV T673, LT T673, LW T673&lt;br&gt;
+LH T674&lt;br&gt;
+LS T676, LA T676, LO T676, LY T676, LB T676, LH T676, LSB T676, LW T676&lt;br&gt;
+LB T67C, LV T67C, LT T67C, LS T67K, LO T67K, LY T67K, LW E67C&lt;br&gt;
+LS E67B, LA E67B, LO E67B, LY E67B, LB E67C, LV E67C, LT E67C&lt;br&gt;
+LW T67C&lt;br&gt;
+LS T679, LY T679, LG T679&lt;br&gt;
+LS T770, LO T770, LY T770, LG T770, LP T770&lt;br&gt;
+LB T773, LV T773, LT T773, LW T773&lt;br&gt;
+LH T774&lt;br&gt;
+LS E675, LA E675, LY E675, LS T675&lt;br&gt;
+LS T776, LA T776, LO T776, LY T776, LB T776&lt;br&gt;
+LHGB T686&lt;br&gt;
+LT T68C, LB T68C&lt;br&gt;
+
+- &lt;u&gt;Hyper Mini TOPLED®&lt;/u&gt;&lt;br&gt;
+LB M676&lt;br&gt;
+
+- &lt;u&gt;Mini TOPLED Santana®&lt;/u&gt;&lt;br&gt;
+LG M470&lt;br&gt;
+LS M47K, LO M47K, LY M47K
+&lt;p&gt;
+Source: http://www.osram.convergy.de&lt;p&gt;
+
+&lt;u&gt;LUXEON:&lt;/u&gt;&lt;br&gt;
+- &lt;u&gt;LUMILED®&lt;/u&gt;&lt;br&gt;
+LXK2-PW12-R00, LXK2-PW12-S00, LXK2-PW14-U00, LXK2-PW14-V00&lt;br&gt;
+LXK2-PM12-R00, LXK2-PM12-S00, LXK2-PM14-U00&lt;br&gt;
+LXK2-PE12-Q00, LXK2-PE12-R00, LXK2-PE12-S00, LXK2-PE14-T00, LXK2-PE14-U00&lt;br&gt;
+LXK2-PB12-K00, LXK2-PB12-L00, LXK2-PB12-M00, LXK2-PB14-N00, LXK2-PB14-P00, LXK2-PB14-Q00&lt;br&gt;
+LXK2-PR12-L00, LXK2-PR12-M00, LXK2-PR14-Q00, LXK2-PR14-R00&lt;br&gt;
+LXK2-PD12-Q00, LXK2-PD12-R00, LXK2-PD12-S00&lt;br&gt;
+LXK2-PH12-R00, LXK2-PH12-S00&lt;br&gt;
+LXK2-PL12-P00, LXK2-PL12-Q00, LXK2-PL12-R00
+&lt;p&gt;
+Source: www.luxeon.com&lt;p&gt;
+
+&lt;u&gt;KINGBRIGHT:&lt;/U&gt;&lt;p&gt;
+KA-3528ASYC&lt;br&gt;
+Source: www.kingbright.com</description>
+<gates>
+<gate name="G$1" symbol="LED" x="0" y="0"/>
+</gates>
+<devices>
+<device name="SMT1206" package="1206">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LD260" package="LD260">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SQR2X5" package="LED2X5">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="3MM" package="LED3MM">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="5MM" package="LED5MM">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LSU260" package="LSU260">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="LZR181" package="LZR181">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="B152" package="Q62902-B152">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="B153" package="Q62902-B153">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="B155" package="Q62902-B155">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="B156" package="Q62902-B156">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SFH480" package="SFH480">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SFH482" package="SFH482">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SQR5.7X3.2" package="U57X32">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="IRL80A" package="IRL80A">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="P-LCC-2" package="P-LCC-2">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MINI-TOP" package="OSRAM-MINI-TOP-LED">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SIDELED" package="OSRAM-SIDELED">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SMART-LED" package="SMART-LED">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="B"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="P-LCC-2-BACK" package="P-LCC-2-TOPLED-RG">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="MICRO-SIDELED" package="MICRO-SIDELED">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="P-LCC-4" package="P-LCC-4">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C@4"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIP-LED0603" package="CHIP-LED0603">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIP-LED0805" package="CHIP-LED0805">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="TOPLED-SANTANA" package="MINI-TOPLED-SANTANA">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIPLED_0805" package="CHIPLED_0805">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIPLED_1206" package="CHIPLED_1206">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIPLED_0603" package="CHIPLED_0603">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CHIPLED-0603-TTW" package="CHIPLED-0603-TTW">
+<connects>
+<connect gate="G$1" pin="A" pad="A@1"/>
+<connect gate="G$1" pin="C" pad="C@1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="" package="SMARTLED-TTW">
+<connects>
+<connect gate="G$1" pin="A" pad="A@1"/>
+<connect gate="G$1" pin="C" pad="C@1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-LUMILED+" package="LUMILED+">
+<connects>
+<connect gate="G$1" pin="A" pad="2+"/>
+<connect gate="G$1" pin="C" pad="4-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-LUMILED" package="LUMILED">
+<connects>
+<connect gate="G$1" pin="A" pad="2+"/>
+<connect gate="G$1" pin="C" pad="4-"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="10MM" package="LED10MM">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="K"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="KA-3528ASYC" package="KA-3528ASYC">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SML0805" package="SML0805">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SML1206" package="SML1206">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SML0603" package="SML0603">
+<connects>
+<connect gate="G$1" pin="A" pad="A"/>
+<connect gate="G$1" pin="C" pad="C"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="memory" urn="urn:adsk.eagle:library:279">
+<description>&lt;b&gt;Generic Memories&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL24">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="-15.24" y1="6.731" x2="-15.24" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-15.24" y1="-6.731" x2="-15.24" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-15.24" y1="1.016" x2="-15.24" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<wire x1="-15.24" y1="-6.731" x2="15.24" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="15.24" y1="6.731" x2="15.24" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="15.24" y1="6.731" x2="-15.24" y2="6.731" width="0.1524" layer="21"/>
+<pad name="1" x="-13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="-3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="-6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="-8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="-11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="-13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<text x="-15.494" y="-6.731" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-11.303" y="-0.889" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="2716" library_version="1">
+<wire x1="-10.16" y1="-20.32" x2="5.08" y2="-20.32" width="0.4064" layer="94"/>
+<wire x1="5.08" y1="-20.32" x2="5.08" y2="20.32" width="0.4064" layer="94"/>
+<wire x1="5.08" y1="20.32" x2="-10.16" y2="20.32" width="0.4064" layer="94"/>
+<wire x1="-10.16" y1="20.32" x2="-10.16" y2="-20.32" width="0.4064" layer="94"/>
+<text x="-10.16" y="20.955" size="1.778" layer="95">&gt;NAME</text>
+<text x="-10.16" y="-22.86" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="A7" x="-15.24" y="0" length="middle" direction="in"/>
+<pin name="A6" x="-15.24" y="2.54" length="middle" direction="in"/>
+<pin name="A5" x="-15.24" y="5.08" length="middle" direction="in"/>
+<pin name="A4" x="-15.24" y="7.62" length="middle" direction="in"/>
+<pin name="A3" x="-15.24" y="10.16" length="middle" direction="in"/>
+<pin name="A2" x="-15.24" y="12.7" length="middle" direction="in"/>
+<pin name="A1" x="-15.24" y="15.24" length="middle" direction="in"/>
+<pin name="A0" x="-15.24" y="17.78" length="middle" direction="in"/>
+<pin name="O0" x="10.16" y="17.78" length="middle" direction="hiz" rot="R180"/>
+<pin name="O1" x="10.16" y="15.24" length="middle" direction="hiz" rot="R180"/>
+<pin name="O2" x="10.16" y="12.7" length="middle" direction="hiz" rot="R180"/>
+<pin name="O3" x="10.16" y="10.16" length="middle" direction="hiz" rot="R180"/>
+<pin name="O4" x="10.16" y="7.62" length="middle" direction="hiz" rot="R180"/>
+<pin name="O5" x="10.16" y="5.08" length="middle" direction="hiz" rot="R180"/>
+<pin name="O6" x="10.16" y="2.54" length="middle" direction="hiz" rot="R180"/>
+<pin name="O7" x="10.16" y="0" length="middle" direction="hiz" rot="R180"/>
+<pin name="!CE" x="-15.24" y="-12.7" length="middle" direction="in"/>
+<pin name="A10" x="-15.24" y="-7.62" length="middle" direction="in"/>
+<pin name="!OE" x="-15.24" y="-15.24" length="middle" direction="in"/>
+<pin name="VPP" x="-15.24" y="-17.78" length="middle" direction="in"/>
+<pin name="A9" x="-15.24" y="-5.08" length="middle" direction="in"/>
+<pin name="A8" x="-15.24" y="-2.54" length="middle" direction="in"/>
+</symbol>
+<symbol name="PWRN">
+<text x="-0.635" y="-0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.905" y="-5.588" size="1.27" layer="95" rot="R90">GND</text>
+<text x="1.905" y="2.413" size="1.27" layer="95" rot="R90">VCC</text>
+<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
+<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="2716" prefix="IC" uservalue="yes" library_version="1">
+<description>&lt;b&gt;MEMORY&lt;/b&gt;</description>
+<gates>
+<gate name="A" symbol="2716" x="22.86" y="0"/>
+<gate name="P" symbol="PWRN" x="-7.62" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="" package="DIL24">
+<connects>
+<connect gate="A" pin="!CE" pad="18"/>
+<connect gate="A" pin="!OE" pad="20"/>
+<connect gate="A" pin="A0" pad="8"/>
+<connect gate="A" pin="A1" pad="7"/>
+<connect gate="A" pin="A10" pad="19"/>
+<connect gate="A" pin="A2" pad="6"/>
+<connect gate="A" pin="A3" pad="5"/>
+<connect gate="A" pin="A4" pad="4"/>
+<connect gate="A" pin="A5" pad="3"/>
+<connect gate="A" pin="A6" pad="2"/>
+<connect gate="A" pin="A7" pad="1"/>
+<connect gate="A" pin="A8" pad="23"/>
+<connect gate="A" pin="A9" pad="22"/>
+<connect gate="A" pin="O0" pad="9"/>
+<connect gate="A" pin="O1" pad="10"/>
+<connect gate="A" pin="O2" pad="11"/>
+<connect gate="A" pin="O3" pad="13"/>
+<connect gate="A" pin="O4" pad="14"/>
+<connect gate="A" pin="O5" pad="15"/>
+<connect gate="A" pin="O6" pad="16"/>
+<connect gate="A" pin="O7" pad="17"/>
+<connect gate="A" pin="VPP" pad="21"/>
+<connect gate="P" pin="GND" pad="12"/>
+<connect gate="P" pin="VCC" pad="24"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="con-sd-attend2">
+<packages>
+<package name="104H-TDA0-R">
+<smd name="P4" x="0" y="-0.625" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P3" x="0" y="1.875" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P2" x="0" y="4.375" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P1" x="0" y="6.875" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P9" x="0" y="9.375" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P5" x="0" y="-3.125" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P6" x="0" y="-5.625" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P7" x="0" y="-8.125" dx="1" dy="1.6" layer="1" rot="R90"/>
+<smd name="P8" x="0" y="-9.775" dx="1" dy="1.6" layer="1" rot="R90"/>
+<pad name="GND0" x="24.2" y="-13.4" drill="1.6"/>
+<wire x1="0" y1="-13.5" x2="29.5" y2="-13.5" width="0.127" layer="21"/>
+<wire x1="0" y1="14.65" x2="29.5" y2="14.65" width="0.127" layer="21"/>
+<wire x1="0" y1="-13.5" x2="0" y2="14.65" width="0.127" layer="21"/>
+<wire x1="29.5" y1="14.65" x2="29.5" y2="-13.5" width="0.127" layer="21"/>
+<pad name="GND1" x="24.2" y="14.55" drill="1.6"/>
+<smd name="CD" x="11.3" y="-13.125" dx="1.75" dy="1.2" layer="1" rot="R90"/>
+<smd name="WP" x="20.1" y="-13.125" dx="1.75" dy="1.2" layer="1" rot="R90"/>
+<smd name="SC" x="21.4" y="-13.125" dx="1.75" dy="1.2" layer="1" rot="R90"/>
+</package>
+</packages>
+<symbols>
+<symbol name="104H-TDA0-R">
+<pin name="DAT3/CS/CD" x="0" y="0" length="middle"/>
+<pin name="CMD" x="0" y="5.08" length="middle"/>
+<pin name="VSS1" x="0" y="10.16" length="middle"/>
+<pin name="VDD" x="0" y="15.24" length="middle"/>
+<pin name="CLK" x="0" y="20.32" length="middle"/>
+<pin name="VSS2" x="0" y="25.4" length="middle"/>
+<pin name="DAT0" x="0" y="30.48" length="middle"/>
+<pin name="DAT1" x="0" y="35.56" length="middle"/>
+<pin name="DAT2" x="0" y="40.64" length="middle"/>
+<wire x1="5.08" y1="43.18" x2="5.08" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="5.08" y1="-2.54" x2="38.1" y2="-2.54" width="0.254" layer="94"/>
+<wire x1="38.1" y1="-2.54" x2="38.1" y2="43.18" width="0.254" layer="94"/>
+<wire x1="38.1" y1="43.18" x2="5.08" y2="43.18" width="0.254" layer="94"/>
+<text x="22.86" y="20.32" size="1.27" layer="94">104H-TDA0-R</text>
+<text x="22.86" y="22.86" size="1.27" layer="94">SD-CARD-SLOT</text>
+<pin name="GND" x="33.02" y="-7.62" length="middle" rot="R90"/>
+<pin name="SC" x="33.02" y="48.26" length="middle" rot="R270"/>
+<pin name="WP" x="27.94" y="48.26" length="middle" rot="R270"/>
+<pin name="CD" x="22.86" y="48.26" length="middle" rot="R270"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="104H-TDA0-R">
+<gates>
+<gate name="G$1" symbol="104H-TDA0-R" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="104H-TDA0-R">
+<connects>
+<connect gate="G$1" pin="CD" pad="CD"/>
+<connect gate="G$1" pin="CLK" pad="P5"/>
+<connect gate="G$1" pin="CMD" pad="P2"/>
+<connect gate="G$1" pin="DAT0" pad="P7"/>
+<connect gate="G$1" pin="DAT1" pad="P8"/>
+<connect gate="G$1" pin="DAT2" pad="P9"/>
+<connect gate="G$1" pin="DAT3/CS/CD" pad="P1"/>
+<connect gate="G$1" pin="GND" pad="GND0 GND1"/>
+<connect gate="G$1" pin="SC" pad="SC"/>
+<connect gate="G$1" pin="VDD" pad="P4"/>
+<connect gate="G$1" pin="VSS1" pad="P3"/>
+<connect gate="G$1" pin="VSS2" pad="P6"/>
+<connect gate="G$1" pin="WP" pad="WP"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="pinhead" urn="urn:adsk.eagle:library:325">
+<description>&lt;b&gt;Pin Header Connectors&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="1X06">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<wire x1="0.635" y1="1.27" x2="1.905" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="1.27" x2="2.54" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.635" x2="2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.635" x2="1.905" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.635" x2="3.175" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="1.27" x2="4.445" y2="1.27" width="0.1524" layer="21"/>
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+</devices>
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+</devicesets>
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+<description>&lt;b&gt;Pin Headers&lt;/b&gt;&lt;p&gt;
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+# contacts - # rows&lt;p&gt;
+W = angled&lt;p&gt;
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+<pin name="1" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="2" x="7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="3" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="MA03-1" prefix="SV" uservalue="yes" library_version="1">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="MA03-1" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="MA03-1">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="ST1" library="con-apple2" deviceset="A2-50PIN" device="SLOT1-3"/>
+<part name="U$1" library="xilinx-xc9" library_urn="urn:adsk.eagle:library:416" deviceset="XC9572_S44" device="" value="XC9572XL"/>
+<part name="IC1" library="74xx-eu" library_urn="urn:adsk.eagle:library:85" deviceset="74*245" device="N" technology="HCT"/>
+<part name="IC2" library="v-reg" library_urn="urn:adsk.eagle:library:409" deviceset="LM317TL" device="" value="LM317"/>
+<part name="C1" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="C-EU" device="025-025X050" value="100n"/>
+<part name="C2" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="CPOL-EU" device="E2.5-5" value="1u"/>
+<part name="R1" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="R-EU_" device="0204/7" value="200"/>
+<part name="R2" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="R-EU_" device="0204/7" value="330"/>
+<part name="R3" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="R-EU_" device="0204/7" value="22k"/>
+<part name="+3V1" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/>
+<part name="P+1" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+5V" device=""/>
+<part name="GND1" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
+<part name="P+2" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+5V" device=""/>
+<part name="GND5" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
+<part name="+3V5" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/>
+<part name="+3V2" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/>
+<part name="P+3" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+5V" device=""/>
+<part name="GND2" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
+<part name="GND3" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
+<part name="GND6" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
+<part name="R4" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="R-EU_" device="0204/7" value="470"/>
+<part name="+3V4" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+3V3" device=""/>
+<part name="LED1" library="led" library_urn="urn:adsk.eagle:library:259" deviceset="LED" device="SQR2X5"/>
+<part name="IC3" library="memory" library_urn="urn:adsk.eagle:library:279" deviceset="2716" device="" value="2716"/>
+<part name="P+4" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+5V" device=""/>
+<part name="GND7" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="GND" device=""/>
+<part name="C3" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="C-EU" device="025-025X050" value="100n"/>
+<part name="C4" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="C-EU" device="025-025X050" value="100n"/>
+<part name="C5" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="C-EU" device="025-025X050" value="100n"/>
+<part name="U$2" library="con-sd-attend2" deviceset="104H-TDA0-R" device=""/>
+<part name="JP1" library="pinhead" library_urn="urn:adsk.eagle:library:325" deviceset="PINHD-1X6" device=""/>
+<part name="FRAME1" library="frames" library_urn="urn:adsk.eagle:library:229" deviceset="A3L-LOC" device=""/>
+<part name="R5" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="R-EU_" device="0204/7" value="22k"/>
+<part name="R6" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="R-EU_" device="0204/7" value="22k"/>
+<part name="R7" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="R-EU_" device="0204/7" value="22k"/>
+<part name="R8" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="R-EU_" device="0204/7" value="22k"/>
+<part name="R9" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="R-EU_" device="0204/7" value="22k"/>
+<part name="P+5" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+5V" device=""/>
+<part name="SV1" library="con-lstb" library_urn="urn:adsk.eagle:library:162" deviceset="MA03-1" device=""/>
+<part name="R10" library="rcl" library_urn="urn:adsk.eagle:library:334" deviceset="R-EU_" device="0204/7" value="10k"/>
+<part name="P+6" library="supply1" library_urn="urn:adsk.eagle:library:371" deviceset="+5V" device=""/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<text x="299.72" y="86.36" size="1.778" layer="91">SV1
+1-2: Read Only
+2-3: Read / Write</text>
+</plain>
+<instances>
+<instance part="ST1" gate="_-12V@2" x="5.08" y="43.18"/>
+<instance part="ST1" gate="_D0" x="73.66" y="134.62" rot="R180"/>
+<instance part="ST1" gate="_D1" x="73.66" y="132.08" rot="R180"/>
+<instance part="ST1" gate="_D2" x="73.66" y="129.54" rot="R180"/>
+<instance part="ST1" gate="_D3" x="73.66" y="127" rot="R180"/>
+<instance part="ST1" gate="_D4" x="73.66" y="124.46" rot="R180"/>
+<instance part="ST1" gate="_D5" x="73.66" y="121.92" rot="R180"/>
+<instance part="ST1" gate="_D6" x="73.66" y="119.38" rot="R180"/>
+<instance part="ST1" gate="_D7" x="73.66" y="116.84" rot="R180"/>
+<instance part="ST1" gate="_DEVSELECT\" x="73.66" y="81.28" rot="R180"/>
+<instance part="ST1" gate="_00" x="73.66" y="162.56" rot="R180"/>
+<instance part="ST1" gate="_USER1" x="5.08" y="58.42"/>
+<instance part="ST1" gate="_01" x="5.08" y="48.26"/>
+<instance part="ST1" gate="_Q3" x="5.08" y="50.8"/>
+<instance part="ST1" gate="_7M" x="73.66" y="165.1" rot="R180"/>
+<instance part="ST1" gate="_NC@2" x="5.08" y="68.58"/>
+<instance part="ST1" gate="_-5V" x="5.08" y="38.1"/>
+<instance part="ST1" gate="_-12V@1" x="5.08" y="40.64"/>
+<instance part="ST1" gate="_INH\" x="5.08" y="78.74"/>
+<instance part="ST1" gate="_RES\" x="73.66" y="83.82" rot="R180"/>
+<instance part="ST1" gate="_IRQ\" x="73.66" y="160.02" rot="R180"/>
+<instance part="ST1" gate="_NMI\" x="5.08" y="81.28"/>
+<instance part="ST1" gate="_INT_IN" x="73.66" y="144.78" rot="R180"/>
+<instance part="ST1" gate="_DMA_IN" x="73.66" y="149.86" rot="R180"/>
+<instance part="ST1" gate="_GND" x="73.66" y="99.06" rot="R180"/>
+<instance part="ST1" gate="_IOSELECT\" x="73.66" y="78.74" rot="R180"/>
+<instance part="ST1" gate="_A00" x="73.66" y="50.8" rot="R180"/>
+<instance part="ST1" gate="_A01" x="73.66" y="53.34" rot="R180"/>
+<instance part="ST1" gate="_A02" x="73.66" y="55.88" rot="R180"/>
+<instance part="ST1" gate="_A03" x="73.66" y="58.42" rot="R180"/>
+<instance part="ST1" gate="_A04" x="73.66" y="60.96" rot="R180"/>
+<instance part="ST1" gate="_A05" x="73.66" y="63.5" rot="R180"/>
+<instance part="ST1" gate="_A06" x="73.66" y="66.04" rot="R180"/>
+<instance part="ST1" gate="_A07" x="73.66" y="68.58" rot="R180"/>
+<instance part="ST1" gate="_A08" x="73.66" y="177.8" rot="R180"/>
+<instance part="ST1" gate="_A09" x="73.66" y="175.26" rot="R180"/>
+<instance part="ST1" gate="_A10" x="73.66" y="172.72" rot="R180"/>
+<instance part="ST1" gate="_A11" x="5.08" y="104.14"/>
+<instance part="ST1" gate="_A12" x="5.08" y="106.68"/>
+<instance part="ST1" gate="_A13" x="5.08" y="109.22"/>
+<instance part="ST1" gate="_A14" x="5.08" y="111.76"/>
+<instance part="ST1" gate="_A15" x="5.08" y="114.3"/>
+<instance part="ST1" gate="_RW" x="73.66" y="157.48" rot="R180"/>
+<instance part="ST1" gate="_NC@1" x="5.08" y="66.04"/>
+<instance part="ST1" gate="_IOSTR\" x="73.66" y="170.18" rot="R180"/>
+<instance part="ST1" gate="_RDY" x="5.08" y="55.88"/>
+<instance part="ST1" gate="_DMA\" x="5.08" y="83.82"/>
+<instance part="ST1" gate="_INT_OUT" x="73.66" y="142.24" rot="R180"/>
+<instance part="ST1" gate="_DMA_OUT" x="73.66" y="152.4" rot="R180"/>
+<instance part="ST1" gate="_+5V" x="73.66" y="101.6" rot="R180"/>
+<instance part="U$1" gate="G$1" x="200.66" y="124.46"/>
+<instance part="IC1" gate="A" x="106.68" y="129.54" rot="R180"/>
+<instance part="IC2" gate="A" x="124.46" y="30.48"/>
+<instance part="C1" gate="G$1" x="109.22" y="20.32"/>
+<instance part="C2" gate="G$1" x="144.78" y="20.32"/>
+<instance part="R1" gate="G$1" x="137.16" y="22.86" rot="R90"/>
+<instance part="R2" gate="G$1" x="124.46" y="12.7" rot="R90"/>
+<instance part="R3" gate="G$1" x="271.78" y="154.94"/>
+<instance part="+3V1" gate="G$1" x="144.78" y="38.1"/>
+<instance part="P+1" gate="1" x="109.22" y="38.1"/>
+<instance part="GND1" gate="1" x="124.46" y="5.08"/>
+<instance part="P+2" gate="1" x="81.28" y="109.22"/>
+<instance part="GND5" gate="1" x="81.28" y="96.52"/>
+<instance part="IC1" gate="P" x="177.8" y="22.86"/>
+<instance part="+3V5" gate="G$1" x="276.86" y="177.8"/>
+<instance part="U$1" gate="SUPPLY" x="203.2" y="22.86"/>
+<instance part="+3V2" gate="G$1" x="203.2" y="38.1"/>
+<instance part="P+3" gate="1" x="177.8" y="38.1"/>
+<instance part="GND2" gate="1" x="203.2" y="5.08"/>
+<instance part="GND3" gate="1" x="177.8" y="5.08"/>
+<instance part="GND6" gate="1" x="279.4" y="93.98"/>
+<instance part="R4" gate="G$1" x="246.38" y="132.08" rot="R180"/>
+<instance part="+3V4" gate="G$1" x="251.46" y="154.94"/>
+<instance part="LED1" gate="G$1" x="251.46" y="147.32"/>
+<instance part="IC3" gate="A" x="266.7" y="68.58" rot="MR180"/>
+<instance part="IC3" gate="P" x="226.06" y="22.86"/>
+<instance part="P+4" gate="1" x="226.06" y="38.1"/>
+<instance part="GND7" gate="1" x="226.06" y="5.08"/>
+<instance part="C3" gate="G$1" x="170.18" y="22.86"/>
+<instance part="C4" gate="G$1" x="233.68" y="22.86"/>
+<instance part="C5" gate="G$1" x="190.5" y="22.86"/>
+<instance part="U$2" gate="G$1" x="292.1" y="109.22"/>
+<instance part="JP1" gate="A" x="259.08" y="111.76"/>
+<instance part="FRAME1" gate="G$1" x="-35.56" y="-58.42"/>
+<instance part="R5" gate="G$1" x="287.02" y="149.86"/>
+<instance part="R6" gate="G$1" x="281.94" y="144.78"/>
+<instance part="R7" gate="G$1" x="271.78" y="124.46"/>
+<instance part="R8" gate="G$1" x="271.78" y="132.08"/>
+<instance part="R9" gate="G$1" x="287.02" y="165.1"/>
+<instance part="P+5" gate="1" x="226.06" y="96.52"/>
+<instance part="SV1" gate="G$1" x="233.68" y="101.6" rot="R270"/>
+<instance part="R10" gate="G$1" x="172.72" y="154.94"/>
+<instance part="P+6" gate="1" x="182.88" y="160.02"/>
+</instances>
+<busses>
+<bus name="DATA">
+<segment>
+<wire x1="134.62" y1="147.32" x2="157.48" y2="147.32" width="0.762" layer="92"/>
+<label x="147.32" y="149.86" size="1.778" layer="95"/>
+</segment>
+<segment>
+<wire x1="289.56" y1="73.66" x2="289.56" y2="53.34" width="0.762" layer="92"/>
+<label x="292.1" y="73.66" size="1.778" layer="95"/>
+</segment>
+</bus>
+</busses>
+<nets>
+<net name="GND" class="0">
+<segment>
+<pinref part="R2" gate="G$1" pin="1"/>
+<pinref part="GND1" gate="1" pin="GND"/>
+<wire x1="124.46" y1="7.62" x2="109.22" y2="7.62" width="0.1524" layer="91"/>
+<junction x="124.46" y="7.62"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="109.22" y1="7.62" x2="109.22" y2="15.24" width="0.1524" layer="91"/>
+<wire x1="124.46" y1="7.62" x2="144.78" y2="7.62" width="0.1524" layer="91"/>
+<pinref part="C2" gate="G$1" pin="-"/>
+<wire x1="144.78" y1="7.62" x2="144.78" y2="15.24" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="ST1" gate="_GND" pin="P"/>
+<pinref part="GND5" gate="1" pin="GND"/>
+<wire x1="76.2" y1="99.06" x2="81.28" y2="99.06" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="P" pin="GND"/>
+<pinref part="GND3" gate="1" pin="GND"/>
+<wire x1="177.8" y1="15.24" x2="177.8" y2="7.62" width="0.1524" layer="91"/>
+<pinref part="C3" gate="G$1" pin="2"/>
+<wire x1="170.18" y1="17.78" x2="170.18" y2="15.24" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="15.24" x2="177.8" y2="15.24" width="0.1524" layer="91"/>
+<junction x="177.8" y="15.24"/>
+</segment>
+<segment>
+<pinref part="U$1" gate="SUPPLY" pin="GND@1"/>
+<pinref part="GND2" gate="1" pin="GND"/>
+<wire x1="203.2" y1="15.24" x2="203.2" y2="12.7" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="SUPPLY" pin="GND@0"/>
+<wire x1="203.2" y1="12.7" x2="203.2" y2="7.62" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="15.24" x2="198.12" y2="12.7" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="12.7" x2="203.2" y2="12.7" width="0.1524" layer="91"/>
+<junction x="203.2" y="12.7"/>
+<pinref part="U$1" gate="SUPPLY" pin="GND@2"/>
+<wire x1="208.28" y1="15.24" x2="208.28" y2="12.7" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="12.7" x2="203.2" y2="12.7" width="0.1524" layer="91"/>
+<pinref part="C5" gate="G$1" pin="2"/>
+<wire x1="190.5" y1="17.78" x2="190.5" y2="12.7" width="0.1524" layer="91"/>
+<wire x1="190.5" y1="12.7" x2="198.12" y2="12.7" width="0.1524" layer="91"/>
+<junction x="198.12" y="12.7"/>
+</segment>
+<segment>
+<pinref part="IC3" gate="P" pin="GND"/>
+<pinref part="GND7" gate="1" pin="GND"/>
+<wire x1="226.06" y1="15.24" x2="226.06" y2="7.62" width="0.1524" layer="91"/>
+<pinref part="C4" gate="G$1" pin="2"/>
+<wire x1="233.68" y1="17.78" x2="233.68" y2="15.24" width="0.1524" layer="91"/>
+<wire x1="233.68" y1="15.24" x2="226.06" y2="15.24" width="0.1524" layer="91"/>
+<junction x="226.06" y="15.24"/>
+</segment>
+<segment>
+<pinref part="U$2" gate="G$1" pin="VSS2"/>
+<wire x1="292.1" y1="134.62" x2="279.4" y2="134.62" width="0.1524" layer="91"/>
+<pinref part="GND6" gate="1" pin="GND"/>
+<wire x1="279.4" y1="134.62" x2="279.4" y2="119.38" width="0.1524" layer="91"/>
+<pinref part="U$2" gate="G$1" pin="VSS1"/>
+<wire x1="279.4" y1="119.38" x2="279.4" y2="116.84" width="0.1524" layer="91"/>
+<wire x1="279.4" y1="116.84" x2="279.4" y2="101.6" width="0.1524" layer="91"/>
+<wire x1="279.4" y1="101.6" x2="279.4" y2="96.52" width="0.1524" layer="91"/>
+<wire x1="292.1" y1="119.38" x2="279.4" y2="119.38" width="0.1524" layer="91"/>
+<junction x="279.4" y="119.38"/>
+<pinref part="U$2" gate="G$1" pin="GND"/>
+<wire x1="325.12" y1="101.6" x2="279.4" y2="101.6" width="0.1524" layer="91"/>
+<junction x="279.4" y="101.6"/>
+<pinref part="JP1" gate="A" pin="2"/>
+<wire x1="256.54" y1="116.84" x2="279.4" y2="116.84" width="0.1524" layer="91"/>
+<junction x="279.4" y="116.84"/>
+</segment>
+</net>
+<net name="+5V" class="0">
+<segment>
+<pinref part="P+1" gate="1" pin="+5V"/>
+<pinref part="C1" gate="G$1" pin="1"/>
+<wire x1="109.22" y1="35.56" x2="109.22" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="IC2" gate="A" pin="IN"/>
+<wire x1="109.22" y1="30.48" x2="109.22" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="116.84" y1="30.48" x2="109.22" y2="30.48" width="0.1524" layer="91"/>
+<junction x="109.22" y="30.48"/>
+</segment>
+<segment>
+<pinref part="P+2" gate="1" pin="+5V"/>
+<wire x1="81.28" y1="106.68" x2="81.28" y2="101.6" width="0.1524" layer="91"/>
+<pinref part="ST1" gate="_+5V" pin="P"/>
+<wire x1="81.28" y1="101.6" x2="76.2" y2="101.6" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="P+3" gate="1" pin="+5V"/>
+<pinref part="IC1" gate="P" pin="VCC"/>
+<wire x1="177.8" y1="35.56" x2="177.8" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="C3" gate="G$1" pin="1"/>
+<wire x1="170.18" y1="25.4" x2="170.18" y2="30.48" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="30.48" x2="177.8" y2="30.48" width="0.1524" layer="91"/>
+<junction x="177.8" y="30.48"/>
+</segment>
+<segment>
+<pinref part="P+4" gate="1" pin="+5V"/>
+<pinref part="IC3" gate="P" pin="VCC"/>
+<wire x1="226.06" y1="35.56" x2="226.06" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="C4" gate="G$1" pin="1"/>
+<wire x1="233.68" y1="25.4" x2="233.68" y2="30.48" width="0.1524" layer="91"/>
+<wire x1="233.68" y1="30.48" x2="226.06" y2="30.48" width="0.1524" layer="91"/>
+<junction x="226.06" y="30.48"/>
+</segment>
+<segment>
+<pinref part="SV1" gate="G$1" pin="1"/>
+<wire x1="231.14" y1="93.98" x2="231.14" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="91.44" x2="226.06" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="P+5" gate="1" pin="+5V"/>
+<wire x1="226.06" y1="91.44" x2="226.06" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="R10" gate="G$1" pin="2"/>
+<pinref part="P+6" gate="1" pin="+5V"/>
+<wire x1="177.8" y1="154.94" x2="182.88" y2="154.94" width="0.1524" layer="91"/>
+<wire x1="182.88" y1="154.94" x2="182.88" y2="157.48" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="+3V3" class="0">
+<segment>
+<pinref part="+3V1" gate="G$1" pin="+3V3"/>
+<pinref part="C2" gate="G$1" pin="+"/>
+<wire x1="144.78" y1="35.56" x2="144.78" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="IC2" gate="A" pin="OUT"/>
+<wire x1="144.78" y1="30.48" x2="144.78" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="132.08" y1="30.48" x2="137.16" y2="30.48" width="0.1524" layer="91"/>
+<junction x="144.78" y="30.48"/>
+<pinref part="R1" gate="G$1" pin="2"/>
+<wire x1="137.16" y1="30.48" x2="144.78" y2="30.48" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="27.94" x2="137.16" y2="30.48" width="0.1524" layer="91"/>
+<junction x="137.16" y="30.48"/>
+</segment>
+<segment>
+<pinref part="R3" gate="G$1" pin="2"/>
+<pinref part="+3V5" gate="G$1" pin="+3V3"/>
+<wire x1="276.86" y1="154.94" x2="276.86" y2="165.1" width="0.1524" layer="91"/>
+<wire x1="276.86" y1="165.1" x2="276.86" y2="175.26" width="0.1524" layer="91"/>
+<wire x1="276.86" y1="154.94" x2="276.86" y2="149.86" width="0.1524" layer="91"/>
+<junction x="276.86" y="154.94"/>
+<pinref part="U$2" gate="G$1" pin="VDD"/>
+<wire x1="276.86" y1="149.86" x2="276.86" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="276.86" y1="144.78" x2="276.86" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="276.86" y1="132.08" x2="276.86" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="276.86" y1="124.46" x2="292.1" y2="124.46" width="0.1524" layer="91"/>
+<pinref part="JP1" gate="A" pin="1"/>
+<wire x1="256.54" y1="119.38" x2="276.86" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="276.86" y1="119.38" x2="276.86" y2="124.46" width="0.1524" layer="91"/>
+<junction x="276.86" y="124.46"/>
+<pinref part="R5" gate="G$1" pin="1"/>
+<wire x1="281.94" y1="149.86" x2="276.86" y2="149.86" width="0.1524" layer="91"/>
+<junction x="276.86" y="149.86"/>
+<pinref part="R6" gate="G$1" pin="1"/>
+<junction x="276.86" y="144.78"/>
+<pinref part="R7" gate="G$1" pin="2"/>
+<pinref part="R8" gate="G$1" pin="2"/>
+<junction x="276.86" y="132.08"/>
+<pinref part="R9" gate="G$1" pin="1"/>
+<wire x1="281.94" y1="165.1" x2="276.86" y2="165.1" width="0.1524" layer="91"/>
+<junction x="276.86" y="165.1"/>
+</segment>
+<segment>
+<pinref part="U$1" gate="SUPPLY" pin="VCCINT@1"/>
+<pinref part="+3V2" gate="G$1" pin="+3V3"/>
+<wire x1="203.2" y1="30.48" x2="203.2" y2="33.02" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="SUPPLY" pin="VCCINT@0"/>
+<wire x1="203.2" y1="33.02" x2="203.2" y2="35.56" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="30.48" x2="198.12" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="33.02" x2="203.2" y2="33.02" width="0.1524" layer="91"/>
+<junction x="203.2" y="33.02"/>
+<pinref part="U$1" gate="SUPPLY" pin="VCCIO"/>
+<wire x1="208.28" y1="30.48" x2="208.28" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="33.02" x2="203.2" y2="33.02" width="0.1524" layer="91"/>
+<pinref part="C5" gate="G$1" pin="1"/>
+<wire x1="190.5" y1="25.4" x2="190.5" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="190.5" y1="33.02" x2="198.12" y2="33.02" width="0.1524" layer="91"/>
+<junction x="198.12" y="33.02"/>
+</segment>
+<segment>
+<pinref part="+3V4" gate="G$1" pin="+3V3"/>
+<pinref part="LED1" gate="G$1" pin="A"/>
+<wire x1="251.46" y1="152.4" x2="251.46" y2="149.86" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$1" class="0">
+<segment>
+<pinref part="R1" gate="G$1" pin="1"/>
+<pinref part="R2" gate="G$1" pin="2"/>
+<wire x1="137.16" y1="17.78" x2="124.46" y2="17.78" width="0.1524" layer="91"/>
+<pinref part="IC2" gate="A" pin="ADJ"/>
+<wire x1="124.46" y1="17.78" x2="124.46" y2="22.86" width="0.1524" layer="91"/>
+<junction x="124.46" y="17.78"/>
+</segment>
+</net>
+<net name="R/!W" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="DIR"/>
+<wire x1="160.02" y1="139.7" x2="119.38" y2="139.7" width="0.1524" layer="91"/>
+<label x="124.46" y="139.7" size="1.778" layer="95"/>
+<pinref part="ST1" gate="_RW" pin="P"/>
+<wire x1="76.2" y1="157.48" x2="160.02" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="160.02" y1="139.7" x2="160.02" y2="157.48" width="0.1524" layer="91"/>
+<wire x1="160.02" y1="139.7" x2="160.02" y2="137.16" width="0.1524" layer="91"/>
+<junction x="160.02" y="139.7"/>
+<pinref part="U$1" gate="G$1" pin="FB01/02"/>
+<wire x1="160.02" y1="137.16" x2="170.18" y2="137.16" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="SV1" gate="G$1" pin="3"/>
+<wire x1="236.22" y1="93.98" x2="236.22" y2="88.9" width="0.1524" layer="91"/>
+<label x="238.76" y="88.9" size="1.778" layer="95" rot="R90"/>
+</segment>
+</net>
+<net name="PHI_0" class="0">
+<segment>
+<pinref part="ST1" gate="_00" pin="P"/>
+<wire x1="76.2" y1="162.56" x2="190.5" y2="162.56" width="0.1524" layer="91"/>
+<label x="190.5" y="157.48" size="1.778" layer="95" rot="R90"/>
+<pinref part="U$1" gate="G$1" pin="FB02/17"/>
+<wire x1="190.5" y1="162.56" x2="190.5" y2="154.94" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="!CS" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="FB04/11"/>
+<wire x1="231.14" y1="129.54" x2="266.7" y2="129.54" width="0.1524" layer="91"/>
+<label x="233.68" y="129.54" size="1.778" layer="95"/>
+<wire x1="266.7" y1="129.54" x2="266.7" y2="124.46" width="0.1524" layer="91"/>
+<pinref part="U$2" gate="G$1" pin="DAT3/CS/CD"/>
+<wire x1="266.7" y1="124.46" x2="266.7" y2="109.22" width="0.1524" layer="91"/>
+<wire x1="266.7" y1="109.22" x2="292.1" y2="109.22" width="0.1524" layer="91"/>
+<pinref part="R7" gate="G$1" pin="1"/>
+<junction x="266.7" y="124.46"/>
+</segment>
+</net>
+<net name="MOSI" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="FB02/02"/>
+<wire x1="264.16" y1="165.1" x2="210.82" y2="165.1" width="0.1524" layer="91"/>
+<wire x1="210.82" y1="165.1" x2="210.82" y2="154.94" width="0.1524" layer="91"/>
+<label x="210.82" y="157.48" size="1.778" layer="95" rot="R90"/>
+<wire x1="264.16" y1="165.1" x2="264.16" y2="132.08" width="0.1524" layer="91"/>
+<pinref part="U$2" gate="G$1" pin="CMD"/>
+<wire x1="264.16" y1="132.08" x2="264.16" y2="114.3" width="0.1524" layer="91"/>
+<wire x1="264.16" y1="114.3" x2="292.1" y2="114.3" width="0.1524" layer="91"/>
+<pinref part="R8" gate="G$1" pin="1"/>
+<wire x1="266.7" y1="132.08" x2="264.16" y2="132.08" width="0.1524" layer="91"/>
+<junction x="264.16" y="132.08"/>
+</segment>
+</net>
+<net name="MISO" class="0">
+<segment>
+<wire x1="193.04" y1="167.64" x2="266.7" y2="167.64" width="0.1524" layer="91"/>
+<wire x1="266.7" y1="167.64" x2="266.7" y2="154.94" width="0.1524" layer="91"/>
+<pinref part="R3" gate="G$1" pin="1"/>
+<label x="193.04" y="157.48" size="1.778" layer="95" rot="R90"/>
+<wire x1="266.7" y1="154.94" x2="266.7" y2="139.7" width="0.1524" layer="91"/>
+<junction x="266.7" y="154.94"/>
+<pinref part="U$2" gate="G$1" pin="DAT0"/>
+<wire x1="266.7" y1="139.7" x2="292.1" y2="139.7" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB02/15"/>
+<wire x1="193.04" y1="154.94" x2="193.04" y2="167.64" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="7M" class="0">
+<segment>
+<pinref part="ST1" gate="_7M" pin="P"/>
+<wire x1="76.2" y1="165.1" x2="195.58" y2="165.1" width="0.1524" layer="91"/>
+<label x="195.58" y="157.48" size="1.778" layer="95" rot="R90"/>
+<pinref part="U$1" gate="G$1" pin="FB02/14"/>
+<wire x1="195.58" y1="165.1" x2="195.58" y2="154.94" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="!LED" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="FB04/14"/>
+<pinref part="R4" gate="G$1" pin="2"/>
+<wire x1="231.14" y1="132.08" x2="241.3" y2="132.08" width="0.1524" layer="91"/>
+<label x="233.68" y="132.08" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="N$29" class="0">
+<segment>
+<pinref part="LED1" gate="G$1" pin="C"/>
+<wire x1="251.46" y1="142.24" x2="251.46" y2="132.08" width="0.1524" layer="91"/>
+<pinref part="R4" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="!G" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="G"/>
+<wire x1="119.38" y1="142.24" x2="121.92" y2="142.24" width="0.1524" layer="91"/>
+<label x="127" y="88.9" size="1.778" layer="95"/>
+<wire x1="121.92" y1="142.24" x2="121.92" y2="88.9" width="0.1524" layer="91"/>
+<wire x1="121.92" y1="88.9" x2="193.04" y2="88.9" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB03/05"/>
+<wire x1="193.04" y1="93.98" x2="193.04" y2="88.9" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="A10_B" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="A10"/>
+<label x="231.14" y="76.2" size="1.778" layer="95"/>
+<wire x1="251.46" y1="76.2" x2="210.82" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="210.82" y1="76.2" x2="210.82" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB03/17"/>
+</segment>
+</net>
+<net name="A9_B" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="A9"/>
+<wire x1="251.46" y1="73.66" x2="248.92" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="248.92" y1="73.66" x2="248.92" y2="127" width="0.1524" layer="91"/>
+<label x="233.68" y="127" size="1.778" layer="95"/>
+<pinref part="U$1" gate="G$1" pin="FB04/08"/>
+<wire x1="248.92" y1="127" x2="231.14" y2="127" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="A8_B" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="A8"/>
+<wire x1="251.46" y1="71.12" x2="246.38" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="246.38" y1="71.12" x2="246.38" y2="124.46" width="0.1524" layer="91"/>
+<label x="233.68" y="124.46" size="1.778" layer="95"/>
+<pinref part="U$1" gate="G$1" pin="FB04/05"/>
+<wire x1="246.38" y1="124.46" x2="231.14" y2="124.46" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="!OE" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="FB03/09"/>
+<wire x1="198.12" y1="93.98" x2="198.12" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="198.12" y1="86.36" x2="228.6" y2="86.36" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="!OE"/>
+<wire x1="251.46" y1="83.82" x2="228.6" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="83.82" x2="228.6" y2="86.36" width="0.1524" layer="91"/>
+<label x="226.06" y="86.36" size="1.778" layer="95"/>
+<pinref part="IC3" gate="A" pin="!CE"/>
+<wire x1="251.46" y1="81.28" x2="228.6" y2="81.28" width="0.1524" layer="91"/>
+<wire x1="228.6" y1="81.28" x2="228.6" y2="83.82" width="0.1524" layer="91"/>
+<junction x="228.6" y="83.82"/>
+</segment>
+</net>
+<net name="N$5" class="0">
+<segment>
+<pinref part="ST1" gate="_DMA_OUT" pin="P"/>
+<wire x1="76.2" y1="152.4" x2="78.74" y2="152.4" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="152.4" x2="78.74" y2="149.86" width="0.1524" layer="91"/>
+<pinref part="ST1" gate="_DMA_IN" pin="P"/>
+<wire x1="78.74" y1="149.86" x2="76.2" y2="149.86" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$6" class="0">
+<segment>
+<pinref part="ST1" gate="_INT_IN" pin="P"/>
+<wire x1="76.2" y1="144.78" x2="78.74" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="144.78" x2="78.74" y2="142.24" width="0.1524" layer="91"/>
+<pinref part="ST1" gate="_INT_OUT" pin="P"/>
+<wire x1="78.74" y1="142.24" x2="76.2" y2="142.24" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$7" class="0">
+<segment>
+<pinref part="ST1" gate="_D0" pin="P"/>
+<pinref part="IC1" gate="A" pin="B8"/>
+<wire x1="76.2" y1="134.62" x2="93.98" y2="134.62" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$8" class="0">
+<segment>
+<pinref part="ST1" gate="_D7" pin="P"/>
+<pinref part="IC1" gate="A" pin="B1"/>
+<wire x1="76.2" y1="116.84" x2="93.98" y2="116.84" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$10" class="0">
+<segment>
+<pinref part="ST1" gate="_D6" pin="P"/>
+<pinref part="IC1" gate="A" pin="B2"/>
+<wire x1="76.2" y1="119.38" x2="93.98" y2="119.38" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$11" class="0">
+<segment>
+<pinref part="ST1" gate="_D5" pin="P"/>
+<pinref part="IC1" gate="A" pin="B3"/>
+<wire x1="76.2" y1="121.92" x2="93.98" y2="121.92" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$14" class="0">
+<segment>
+<pinref part="ST1" gate="_D4" pin="P"/>
+<pinref part="IC1" gate="A" pin="B4"/>
+<wire x1="76.2" y1="124.46" x2="93.98" y2="124.46" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$15" class="0">
+<segment>
+<pinref part="ST1" gate="_D3" pin="P"/>
+<pinref part="IC1" gate="A" pin="B5"/>
+<wire x1="76.2" y1="127" x2="93.98" y2="127" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$16" class="0">
+<segment>
+<pinref part="ST1" gate="_D2" pin="P"/>
+<pinref part="IC1" gate="A" pin="B6"/>
+<wire x1="76.2" y1="129.54" x2="93.98" y2="129.54" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$17" class="0">
+<segment>
+<pinref part="ST1" gate="_D1" pin="P"/>
+<pinref part="IC1" gate="A" pin="B7"/>
+<wire x1="76.2" y1="132.08" x2="93.98" y2="132.08" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="ADD0" class="0">
+<segment>
+<pinref part="ST1" gate="_A00" pin="P"/>
+<label x="78.74" y="50.8" size="1.778" layer="95"/>
+<pinref part="U$1" gate="G$1" pin="FB03/14"/>
+<wire x1="203.2" y1="50.8" x2="203.2" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="50.8" x2="203.2" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="A0"/>
+<wire x1="203.2" y1="50.8" x2="251.46" y2="50.8" width="0.1524" layer="91"/>
+<label x="231.14" y="50.8" size="1.778" layer="95"/>
+<junction x="203.2" y="50.8"/>
+</segment>
+</net>
+<net name="ADD1" class="0">
+<segment>
+<pinref part="ST1" gate="_A01" pin="P"/>
+<label x="78.74" y="53.34" size="1.778" layer="95"/>
+<pinref part="U$1" gate="G$1" pin="FB03/11"/>
+<wire x1="200.66" y1="53.34" x2="200.66" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="76.2" y1="53.34" x2="200.66" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="A1"/>
+<label x="231.14" y="53.34" size="1.778" layer="95"/>
+<wire x1="200.66" y1="53.34" x2="251.46" y2="53.34" width="0.1524" layer="91"/>
+<junction x="200.66" y="53.34"/>
+</segment>
+</net>
+<net name="ADD2" class="0">
+<segment>
+<pinref part="ST1" gate="_A02" pin="P"/>
+<label x="78.74" y="55.88" size="1.778" layer="95"/>
+<pinref part="IC3" gate="A" pin="A2"/>
+<label x="231.14" y="55.88" size="1.778" layer="95"/>
+<wire x1="76.2" y1="55.88" x2="251.46" y2="55.88" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="ADD3" class="0">
+<segment>
+<pinref part="ST1" gate="_A03" pin="P"/>
+<label x="78.74" y="58.42" size="1.778" layer="95"/>
+<pinref part="IC3" gate="A" pin="A3"/>
+<label x="231.14" y="58.42" size="1.778" layer="95"/>
+<wire x1="76.2" y1="58.42" x2="251.46" y2="58.42" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="ADD4" class="0">
+<segment>
+<pinref part="ST1" gate="_A04" pin="P"/>
+<label x="78.74" y="60.96" size="1.778" layer="95"/>
+<pinref part="IC3" gate="A" pin="A4"/>
+<label x="231.14" y="60.96" size="1.778" layer="95"/>
+<wire x1="76.2" y1="60.96" x2="251.46" y2="60.96" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="ADD5" class="0">
+<segment>
+<pinref part="ST1" gate="_A05" pin="P"/>
+<label x="78.74" y="63.5" size="1.778" layer="95"/>
+<pinref part="IC3" gate="A" pin="A5"/>
+<label x="231.14" y="63.5" size="1.778" layer="95"/>
+<wire x1="76.2" y1="63.5" x2="251.46" y2="63.5" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="ADD6" class="0">
+<segment>
+<pinref part="ST1" gate="_A06" pin="P"/>
+<label x="78.74" y="66.04" size="1.778" layer="95"/>
+<pinref part="IC3" gate="A" pin="A6"/>
+<label x="231.14" y="66.04" size="1.778" layer="95"/>
+<wire x1="76.2" y1="66.04" x2="251.46" y2="66.04" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="ADD7" class="0">
+<segment>
+<pinref part="ST1" gate="_A07" pin="P"/>
+<wire x1="76.2" y1="68.58" x2="88.9" y2="68.58" width="0.1524" layer="91"/>
+<label x="78.74" y="68.58" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC3" gate="A" pin="A7"/>
+<label x="231.14" y="68.58" size="1.778" layer="95"/>
+<wire x1="251.46" y1="68.58" x2="88.9" y2="68.58" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="ADD8" class="0">
+<segment>
+<pinref part="ST1" gate="_A08" pin="P"/>
+<wire x1="76.2" y1="177.8" x2="208.28" y2="177.8" width="0.1524" layer="91"/>
+<label x="78.74" y="177.8" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$1" gate="G$1" pin="FB02/05"/>
+<wire x1="208.28" y1="154.94" x2="208.28" y2="177.8" width="0.1524" layer="91"/>
+<label x="208.28" y="157.48" size="1.778" layer="95" rot="R90"/>
+</segment>
+</net>
+<net name="ADD9" class="0">
+<segment>
+<pinref part="ST1" gate="_A09" pin="P"/>
+<wire x1="76.2" y1="175.26" x2="205.74" y2="175.26" width="0.1524" layer="91"/>
+<label x="78.74" y="175.26" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="U$1" gate="G$1" pin="FB02/06"/>
+<wire x1="205.74" y1="154.94" x2="205.74" y2="175.26" width="0.1524" layer="91"/>
+<label x="205.74" y="157.48" size="1.778" layer="95" rot="R90"/>
+</segment>
+</net>
+<net name="ADD10" class="0">
+<segment>
+<pinref part="ST1" gate="_A10" pin="P"/>
+<wire x1="76.2" y1="172.72" x2="203.2" y2="172.72" width="0.1524" layer="91"/>
+<label x="78.74" y="172.72" size="1.778" layer="95"/>
+<pinref part="U$1" gate="G$1" pin="FB02/08"/>
+<wire x1="203.2" y1="154.94" x2="203.2" y2="172.72" width="0.1524" layer="91"/>
+<label x="203.2" y="157.48" size="1.778" layer="95" rot="R90"/>
+</segment>
+</net>
+<net name="DATA7" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="A1"/>
+<wire x1="119.38" y1="116.84" x2="152.4" y2="116.84" width="0.1524" layer="91"/>
+<label x="124.46" y="116.84" size="1.778" layer="95"/>
+<wire x1="154.94" y1="147.32" x2="152.4" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="144.78" x2="152.4" y2="116.84" width="0.1524" layer="91"/>
+<wire x1="152.4" y1="86.36" x2="152.4" y2="116.84" width="0.1524" layer="91"/>
+<junction x="152.4" y="116.84"/>
+<pinref part="U$1" gate="G$1" pin="FB03/08"/>
+<wire x1="195.58" y1="93.98" x2="195.58" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="195.58" y1="86.36" x2="152.4" y2="86.36" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="289.56" y1="71.12" x2="287.02" y2="68.58" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="O7"/>
+<wire x1="287.02" y1="68.58" x2="276.86" y2="68.58" width="0.1524" layer="91"/>
+<label x="279.4" y="68.58" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="DATA6" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="A2"/>
+<wire x1="119.38" y1="119.38" x2="149.86" y2="119.38" width="0.1524" layer="91"/>
+<label x="124.46" y="119.38" size="1.778" layer="95"/>
+<wire x1="152.4" y1="147.32" x2="149.86" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="149.86" y1="144.78" x2="149.86" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="149.86" y1="119.38" x2="149.86" y2="91.44" width="0.1524" layer="91"/>
+<junction x="149.86" y="119.38"/>
+<wire x1="149.86" y1="91.44" x2="190.5" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB03/02"/>
+<wire x1="190.5" y1="91.44" x2="190.5" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="289.56" y1="68.58" x2="287.02" y2="66.04" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="O6"/>
+<wire x1="287.02" y1="66.04" x2="276.86" y2="66.04" width="0.1524" layer="91"/>
+<label x="279.4" y="66.04" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="DATA5" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="A3"/>
+<wire x1="119.38" y1="121.92" x2="147.32" y2="121.92" width="0.1524" layer="91"/>
+<label x="124.46" y="121.92" size="1.778" layer="95"/>
+<wire x1="149.86" y1="147.32" x2="147.32" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="147.32" y1="144.78" x2="147.32" y2="121.92" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB01/17"/>
+<wire x1="170.18" y1="116.84" x2="154.94" y2="116.84" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="116.84" x2="154.94" y2="121.92" width="0.1524" layer="91"/>
+<wire x1="154.94" y1="121.92" x2="147.32" y2="121.92" width="0.1524" layer="91"/>
+<junction x="147.32" y="121.92"/>
+</segment>
+<segment>
+<wire x1="289.56" y1="66.04" x2="287.02" y2="63.5" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="O5"/>
+<wire x1="287.02" y1="63.5" x2="276.86" y2="63.5" width="0.1524" layer="91"/>
+<label x="279.4" y="63.5" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="DATA4" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="A4"/>
+<wire x1="119.38" y1="124.46" x2="144.78" y2="124.46" width="0.1524" layer="91"/>
+<label x="124.46" y="124.46" size="1.778" layer="95"/>
+<wire x1="147.32" y1="147.32" x2="144.78" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="144.78" y1="144.78" x2="144.78" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="144.78" y1="124.46" x2="157.48" y2="124.46" width="0.1524" layer="91"/>
+<junction x="144.78" y="124.46"/>
+<wire x1="157.48" y1="124.46" x2="157.48" y2="121.92" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB01/14"/>
+<wire x1="157.48" y1="121.92" x2="170.18" y2="121.92" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="289.56" y1="63.5" x2="287.02" y2="60.96" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="O4"/>
+<wire x1="287.02" y1="60.96" x2="276.86" y2="60.96" width="0.1524" layer="91"/>
+<label x="279.4" y="60.96" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="DATA3" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="A5"/>
+<wire x1="119.38" y1="127" x2="142.24" y2="127" width="0.1524" layer="91"/>
+<label x="124.46" y="127" size="1.778" layer="95"/>
+<wire x1="144.78" y1="147.32" x2="142.24" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="144.78" x2="142.24" y2="127" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="127" x2="160.02" y2="127" width="0.1524" layer="91"/>
+<junction x="142.24" y="127"/>
+<wire x1="160.02" y1="127" x2="160.02" y2="124.46" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB01/11"/>
+<wire x1="160.02" y1="124.46" x2="170.18" y2="124.46" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="289.56" y1="60.96" x2="287.02" y2="58.42" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="O3"/>
+<wire x1="287.02" y1="58.42" x2="276.86" y2="58.42" width="0.1524" layer="91"/>
+<label x="279.4" y="58.42" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="DATA2" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="A6"/>
+<wire x1="119.38" y1="129.54" x2="139.7" y2="129.54" width="0.1524" layer="91"/>
+<label x="124.46" y="129.54" size="1.778" layer="95"/>
+<wire x1="142.24" y1="147.32" x2="139.7" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="139.7" y1="144.78" x2="139.7" y2="129.54" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB01/08"/>
+<wire x1="139.7" y1="129.54" x2="170.18" y2="129.54" width="0.1524" layer="91"/>
+<junction x="139.7" y="129.54"/>
+</segment>
+<segment>
+<wire x1="289.56" y1="58.42" x2="287.02" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="O2"/>
+<wire x1="287.02" y1="55.88" x2="276.86" y2="55.88" width="0.1524" layer="91"/>
+<label x="279.4" y="55.88" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="DATA1" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="A7"/>
+<wire x1="119.38" y1="132.08" x2="137.16" y2="132.08" width="0.1524" layer="91"/>
+<label x="124.46" y="132.08" size="1.778" layer="95"/>
+<wire x1="139.7" y1="147.32" x2="137.16" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="144.78" x2="137.16" y2="132.08" width="0.1524" layer="91"/>
+<wire x1="137.16" y1="132.08" x2="162.56" y2="132.08" width="0.1524" layer="91"/>
+<junction x="137.16" y="132.08"/>
+<wire x1="162.56" y1="132.08" x2="162.56" y2="127" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB01/09"/>
+<wire x1="162.56" y1="127" x2="170.18" y2="127" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="289.56" y1="55.88" x2="287.02" y2="53.34" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="O1"/>
+<wire x1="287.02" y1="53.34" x2="276.86" y2="53.34" width="0.1524" layer="91"/>
+<label x="279.4" y="53.34" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="DATA0" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="A8"/>
+<wire x1="119.38" y1="134.62" x2="134.62" y2="134.62" width="0.1524" layer="91"/>
+<label x="124.46" y="134.62" size="1.778" layer="95"/>
+<wire x1="137.16" y1="147.32" x2="134.62" y2="144.78" width="0.1524" layer="91"/>
+<wire x1="134.62" y1="144.78" x2="134.62" y2="134.62" width="0.1524" layer="91"/>
+<wire x1="134.62" y1="134.62" x2="165.1" y2="134.62" width="0.1524" layer="91"/>
+<junction x="134.62" y="134.62"/>
+<wire x1="165.1" y1="134.62" x2="165.1" y2="132.08" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB01/06"/>
+<wire x1="165.1" y1="132.08" x2="170.18" y2="132.08" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="289.56" y1="53.34" x2="287.02" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="O0"/>
+<wire x1="287.02" y1="50.8" x2="276.86" y2="50.8" width="0.1524" layer="91"/>
+<label x="279.4" y="50.8" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="WP" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="FB02/09"/>
+<wire x1="320.04" y1="170.18" x2="292.1" y2="170.18" width="0.1524" layer="91"/>
+<wire x1="292.1" y1="170.18" x2="200.66" y2="170.18" width="0.1524" layer="91"/>
+<wire x1="200.66" y1="170.18" x2="200.66" y2="154.94" width="0.1524" layer="91"/>
+<label x="200.66" y="157.48" size="1.778" layer="95" rot="R90"/>
+<pinref part="U$2" gate="G$1" pin="WP"/>
+<wire x1="320.04" y1="157.48" x2="320.04" y2="170.18" width="0.1524" layer="91"/>
+<pinref part="R9" gate="G$1" pin="2"/>
+<wire x1="292.1" y1="165.1" x2="292.1" y2="170.18" width="0.1524" layer="91"/>
+<junction x="292.1" y="170.18"/>
+</segment>
+</net>
+<net name="CARD" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="FB04/15"/>
+<wire x1="241.3" y1="134.62" x2="231.14" y2="134.62" width="0.1524" layer="91"/>
+<label x="233.68" y="134.62" size="1.778" layer="95"/>
+<wire x1="241.3" y1="134.62" x2="241.3" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="241.3" y1="160.02" x2="314.96" y2="160.02" width="0.1524" layer="91"/>
+<pinref part="U$2" gate="G$1" pin="CD"/>
+<wire x1="314.96" y1="160.02" x2="314.96" y2="157.48" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="TCK" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="TCK"/>
+<label x="233.68" y="114.3" size="1.778" layer="95"/>
+<pinref part="JP1" gate="A" pin="3"/>
+<wire x1="231.14" y1="114.3" x2="256.54" y2="114.3" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="TDO" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="TDO"/>
+<label x="233.68" y="111.76" size="1.778" layer="95"/>
+<pinref part="JP1" gate="A" pin="4"/>
+<wire x1="231.14" y1="111.76" x2="256.54" y2="111.76" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="TDI" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="TDI"/>
+<label x="233.68" y="109.22" size="1.778" layer="95"/>
+<pinref part="JP1" gate="A" pin="5"/>
+<wire x1="231.14" y1="109.22" x2="256.54" y2="109.22" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="TMS" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="TMS"/>
+<label x="233.68" y="106.68" size="1.778" layer="95"/>
+<pinref part="JP1" gate="A" pin="6"/>
+<wire x1="231.14" y1="106.68" x2="256.54" y2="106.68" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="!IO_STR" class="0">
+<segment>
+<label x="198.12" y="157.48" size="1.778" layer="95" rot="R90"/>
+<pinref part="U$1" gate="G$1" pin="FB02/11"/>
+<wire x1="198.12" y1="170.18" x2="198.12" y2="154.94" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="ST1" gate="_IOSTR\" pin="P"/>
+<wire x1="198.12" y1="170.18" x2="76.2" y2="170.18" width="0.1524" layer="91"/>
+<label x="78.74" y="170.18" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="!IO_SEL" class="0">
+<segment>
+<label x="231.14" y="78.74" size="1.778" layer="95"/>
+<pinref part="U$1" gate="G$1" pin="FB04/02"/>
+<wire x1="231.14" y1="121.92" x2="243.84" y2="121.92" width="0.1524" layer="91"/>
+<wire x1="243.84" y1="121.92" x2="243.84" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="ST1" gate="_IOSELECT\" pin="P"/>
+<wire x1="243.84" y1="78.74" x2="76.2" y2="78.74" width="0.1524" layer="91"/>
+<label x="78.74" y="78.74" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="!DEV_SEL" class="0">
+<segment>
+<pinref part="U$1" gate="G$1" pin="FB03/16"/>
+<label x="78.74" y="81.28" size="1.778" layer="95"/>
+<wire x1="208.28" y1="81.28" x2="208.28" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="208.28" y1="81.28" x2="76.2" y2="81.28" width="0.1524" layer="91"/>
+<pinref part="ST1" gate="_DEVSELECT\" pin="P"/>
+</segment>
+</net>
+<net name="!RESET" class="0">
+<segment>
+<wire x1="76.2" y1="83.82" x2="205.74" y2="83.82" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB03/15"/>
+<wire x1="205.74" y1="83.82" x2="205.74" y2="93.98" width="0.1524" layer="91"/>
+<label x="78.74" y="83.82" size="1.778" layer="95"/>
+<pinref part="ST1" gate="_RES\" pin="P"/>
+</segment>
+</net>
+<net name="CLK" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="CLK"/>
+<wire x1="292.1" y1="129.54" x2="281.94" y2="129.54" width="0.1524" layer="91"/>
+<label x="233.68" y="137.16" size="1.778" layer="95"/>
+<pinref part="U$1" gate="G$1" pin="FB04/17"/>
+<wire x1="231.14" y1="137.16" x2="281.94" y2="137.16" width="0.1524" layer="91"/>
+<wire x1="281.94" y1="137.16" x2="281.94" y2="129.54" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="DAT2"/>
+<pinref part="R5" gate="G$1" pin="2"/>
+</segment>
+</net>
+<net name="N$3" class="0">
+<segment>
+<pinref part="U$2" gate="G$1" pin="DAT1"/>
+<pinref part="R6" gate="G$1" pin="2"/>
+<wire x1="292.1" y1="144.78" x2="287.02" y2="144.78" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="VPP" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="VPP"/>
+<pinref part="SV1" gate="G$1" pin="2"/>
+<wire x1="251.46" y1="86.36" x2="233.68" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="233.68" y1="86.36" x2="233.68" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="!IRQ" class="0">
+<segment>
+<pinref part="ST1" gate="_IRQ\" pin="P"/>
+<wire x1="76.2" y1="160.02" x2="167.64" y2="160.02" width="0.1524" layer="91"/>
+<wire x1="167.64" y1="160.02" x2="167.64" y2="154.94" width="0.1524" layer="91"/>
+<pinref part="U$1" gate="G$1" pin="FB01/05"/>
+<wire x1="167.64" y1="154.94" x2="167.64" y2="134.62" width="0.1524" layer="91"/>
+<wire x1="167.64" y1="134.62" x2="170.18" y2="134.62" width="0.1524" layer="91"/>
+<pinref part="R10" gate="G$1" pin="1"/>
+<junction x="167.64" y="154.94"/>
+<label x="78.74" y="160.02" size="1.778" layer="95"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+<note version="8.2" severity="warning">
+Since Version 8.2, Eagle supports online libraries. The ids
+of those online libraries will not be understood (or retained)
+with this version.
+</note>
+</compatibility>
+</eagle>
diff --git a/Hardware/con-apple2.lbr b/Hardware/con-apple2.lbr
new file mode 100644
index 0000000..93e4251
--- /dev/null
+++ b/Hardware/con-apple2.lbr
@@ -0,0 +1,771 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.2.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.05" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
+<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<library>
+<description>&lt;b&gt;Apple ][ Expansion Card Templates&lt;/b&gt;
+&lt;br /&gt;
+Dimensions are taken from the Apple IIgs Tech Note #28</description>
+<packages>
+<package name="A2-50PIN-SL1-3">
+<description>&lt;B&gt;Apple ][ Peripheral Card&lt;/B&gt;
+&lt;br /&gt;
+Standard 50-pin edge connector for Apple ][ systems
+&lt;br /&gt;
+Dimensions for slot #1 to #3
+&lt;br /&gt;
+Dimensions taken from Tech Note #28</description>
+<wire x1="-9.652" y1="0.508" x2="-10.287" y2="-0.127" width="0.2032" layer="21"/>
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+<wire x1="-253.2126" y1="-6.985" x2="-250.825" y2="-5.715" width="0" layer="48"/>
+<wire x1="-250.825" y1="-5.715" x2="-250.825" y2="-8.255" width="0" layer="48"/>
+<wire x1="-250.825" y1="-8.255" x2="-253.2126" y2="-6.985" width="0" layer="48"/>
+<wire x1="-439.293" y1="77.597" x2="-242.443" y2="77.597" width="0.2032" layer="22"/>
+<wire x1="-195.072" y1="7.747" x2="-195.072" y2="5.715" width="0.1524" layer="22"/>
+<wire x1="-439.293" y1="77.597" x2="-439.293" y2="7.778" width="0.2032" layer="22"/>
+<smd name="23" x="-250.825" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="24" x="-248.285" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="25" x="-245.745" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="26" x="-243.205" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="27" x="-240.665" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="28" x="-238.125" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="29" x="-235.585" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="30" x="-233.045" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="31" x="-230.505" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="32" x="-227.965" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="33" x="-225.425" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="34" x="-222.885" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="35" x="-220.345" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="36" x="-217.805" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="37" x="-215.265" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="38" x="-212.725" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="39" x="-210.185" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="40" x="-207.645" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="41" x="-205.105" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="42" x="-202.565" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="43" x="-200.025" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="44" x="-197.485" y="4.445" dx="1.524" dy="6.477" layer="1" rot="R180" cream="no"/>
+<smd name="22" x="-250.825" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
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+<smd name="20" x="-245.745" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="19" x="-243.205" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="18" x="-240.665" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="17" x="-238.125" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="16" x="-235.585" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="15" x="-233.045" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="14" x="-230.505" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="13" x="-227.965" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="12" x="-225.425" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="11" x="-222.885" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="10" x="-220.345" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="09" x="-217.805" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="08" x="-215.265" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="07" x="-212.725" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="06" x="-210.185" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="05" x="-207.645" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="04" x="-205.105" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="03" x="-202.565" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="02" x="-200.025" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<smd name="01" x="-197.485" y="4.445" dx="1.524" dy="6.477" layer="16" rot="R180" cream="no"/>
+<text x="-280.035" y="4.445" size="1.778" layer="25">&gt;NAME</text>
+<text x="-182.3466" y="2.9718" size="1.778" layer="48">7,87 mm</text>
+<text x="-229.6668" y="-9.2964" size="1.778" layer="48">57,658 mm
+2.270"</text>
+<text x="-280.035" y="0.635" size="1.778" layer="27">&gt;VALUE</text>
+<wire x1="-242.443" y1="77.597" x2="-185.293" y2="63.627" width="0.2032" layer="22"/>
+<wire x1="-185.293" y1="63.627" x2="-185.293" y2="7.747" width="0.2032" layer="22"/>
+</package>
+</packages>
+<symbols>
+<symbol name="ATPIN">
+<wire x1="0" y1="0.635" x2="3.175" y2="0.635" width="0.3048" layer="94"/>
+<wire x1="3.175" y1="0.635" x2="3.175" y2="-0.635" width="0.3048" layer="94"/>
+<wire x1="3.175" y1="-0.635" x2="0" y2="-0.635" width="0.3048" layer="94"/>
+<wire x1="0" y1="-0.635" x2="0" y2="0.635" width="0.3048" layer="94"/>
+<text x="4.445" y="-0.9652" size="1.778" layer="95">&gt;NAME</text>
+<pin name="P" x="-2.54" y="0" visible="pad" length="short" swaplevel="1"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="A2-50PIN" prefix="ST" uservalue="yes">
+<description>&lt;B&gt;Apple ][ Peripheral Card Connector&lt;/B&gt;
+&lt;br /&gt;
+This is the, default, 50-pin connector for slot #1 to #7
+&lt;br /&gt;
+Pins are laid out as seen from the top of the slot</description>
+<gates>
+<gate name="_-12V@2" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
+<gate name="_D0" symbol="ATPIN" x="-5.08" y="-35.56" addlevel="always"/>
+<gate name="_D1" symbol="ATPIN" x="-5.08" y="-33.02" addlevel="always"/>
+<gate name="_D2" symbol="ATPIN" x="-5.08" y="-30.48" addlevel="always"/>
+<gate name="_D3" symbol="ATPIN" x="-5.08" y="-27.94" addlevel="always"/>
+<gate name="_D4" symbol="ATPIN" x="-5.08" y="-25.4" addlevel="always"/>
+<gate name="_D5" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
+<gate name="_D6" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
+<gate name="_D7" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
+<gate name="_DEVSELECT\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
+<gate name="_00" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
+<gate name="_USER1" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
+<gate name="_01" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
+<gate name="_Q3" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
+<gate name="_7M" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
+<gate name="_NC@2" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
+<gate name="_-5V" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
+<gate name="_-12V@1" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
+<gate name="_INH\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
+<gate name="_RES\" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
+<gate name="_IRQ\" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
+<gate name="_NMI\" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
+<gate name="_INT_IN" symbol="ATPIN" x="-5.08" y="17.78" addlevel="always"/>
+<gate name="_DMA_IN" symbol="ATPIN" x="-5.08" y="20.32" addlevel="always"/>
+<gate name="_GND" symbol="ATPIN" x="-5.08" y="22.86" addlevel="always"/>
+<gate name="_IOSELECT\" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
+<gate name="_A00" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
+<gate name="_A01" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
+<gate name="_A02" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
+<gate name="_A03" symbol="ATPIN" x="27.94" y="-27.94" addlevel="always"/>
+<gate name="_A04" symbol="ATPIN" x="27.94" y="-25.4" addlevel="always"/>
+<gate name="_A05" symbol="ATPIN" x="27.94" y="-22.86" addlevel="always"/>
+<gate name="_A06" symbol="ATPIN" x="27.94" y="-20.32" addlevel="always"/>
+<gate name="_A07" symbol="ATPIN" x="27.94" y="-17.78" addlevel="always"/>
+<gate name="_A08" symbol="ATPIN" x="27.94" y="-15.24" addlevel="always"/>
+<gate name="_A09" symbol="ATPIN" x="27.94" y="-12.7" addlevel="always"/>
+<gate name="_A10" symbol="ATPIN" x="27.94" y="-10.16" addlevel="always"/>
+<gate name="_A11" symbol="ATPIN" x="27.94" y="-7.62" addlevel="always"/>
+<gate name="_A12" symbol="ATPIN" x="27.94" y="-5.08" addlevel="always"/>
+<gate name="_A13" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
+<gate name="_A14" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
+<gate name="_A15" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
+<gate name="_RW" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
+<gate name="_NC@1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
+<gate name="_IOSTR\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
+<gate name="_RDY" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
+<gate name="_DMA\" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
+<gate name="_INT_OUT" symbol="ATPIN" x="27.94" y="17.78" addlevel="always"/>
+<gate name="_DMA_OUT" symbol="ATPIN" x="27.94" y="20.32" addlevel="always"/>
+<gate name="_+5V" symbol="ATPIN" x="27.94" y="22.86" addlevel="always"/>
+</gates>
+<devices>
+<device name="SLOT1-3" package="A2-50PIN-SL1-3">
+<connects>
+<connect gate="_+5V" pin="P" pad="25"/>
+<connect gate="_-12V@1" pin="P" pad="33"/>
+<connect gate="_-12V@2" pin="P" pad="50"/>
+<connect gate="_-5V" pin="P" pad="34"/>
+<connect gate="_00" pin="P" pad="40"/>
+<connect gate="_01" pin="P" pad="38"/>
+<connect gate="_7M" pin="P" pad="36"/>
+<connect gate="_A00" pin="P" pad="02"/>
+<connect gate="_A01" pin="P" pad="03"/>
+<connect gate="_A02" pin="P" pad="04"/>
+<connect gate="_A03" pin="P" pad="05"/>
+<connect gate="_A04" pin="P" pad="06"/>
+<connect gate="_A05" pin="P" pad="07"/>
+<connect gate="_A06" pin="P" pad="08"/>
+<connect gate="_A07" pin="P" pad="09"/>
+<connect gate="_A08" pin="P" pad="10"/>
+<connect gate="_A09" pin="P" pad="11"/>
+<connect gate="_A10" pin="P" pad="12"/>
+<connect gate="_A11" pin="P" pad="13"/>
+<connect gate="_A12" pin="P" pad="14"/>
+<connect gate="_A13" pin="P" pad="15"/>
+<connect gate="_A14" pin="P" pad="16"/>
+<connect gate="_A15" pin="P" pad="17"/>
+<connect gate="_D0" pin="P" pad="49"/>
+<connect gate="_D1" pin="P" pad="48"/>
+<connect gate="_D2" pin="P" pad="47"/>
+<connect gate="_D3" pin="P" pad="46"/>
+<connect gate="_D4" pin="P" pad="45"/>
+<connect gate="_D5" pin="P" pad="44"/>
+<connect gate="_D6" pin="P" pad="43"/>
+<connect gate="_D7" pin="P" pad="42"/>
+<connect gate="_DEVSELECT\" pin="P" pad="41"/>
+<connect gate="_DMA\" pin="P" pad="22"/>
+<connect gate="_DMA_IN" pin="P" pad="27"/>
+<connect gate="_DMA_OUT" pin="P" pad="24"/>
+<connect gate="_GND" pin="P" pad="26"/>
+<connect gate="_INH\" pin="P" pad="32"/>
+<connect gate="_INT_IN" pin="P" pad="28"/>
+<connect gate="_INT_OUT" pin="P" pad="23"/>
+<connect gate="_IOSELECT\" pin="P" pad="01"/>
+<connect gate="_IOSTR\" pin="P" pad="20"/>
+<connect gate="_IRQ\" pin="P" pad="30"/>
+<connect gate="_NC@1" pin="P" pad="19"/>
+<connect gate="_NC@2" pin="P" pad="35"/>
+<connect gate="_NMI\" pin="P" pad="29"/>
+<connect gate="_Q3" pin="P" pad="37"/>
+<connect gate="_RDY" pin="P" pad="21"/>
+<connect gate="_RES\" pin="P" pad="31"/>
+<connect gate="_RW" pin="P" pad="18"/>
+<connect gate="_USER1" pin="P" pad="39"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="SLOT4-7" package="A2-50PIN-SL4-7">
+<connects>
+<connect gate="_+5V" pin="P" pad="25"/>
+<connect gate="_-12V@1" pin="P" pad="33"/>
+<connect gate="_-12V@2" pin="P" pad="50"/>
+<connect gate="_-5V" pin="P" pad="34"/>
+<connect gate="_00" pin="P" pad="40"/>
+<connect gate="_01" pin="P" pad="38"/>
+<connect gate="_7M" pin="P" pad="36"/>
+<connect gate="_A00" pin="P" pad="02"/>
+<connect gate="_A01" pin="P" pad="03"/>
+<connect gate="_A02" pin="P" pad="04"/>
+<connect gate="_A03" pin="P" pad="05"/>
+<connect gate="_A04" pin="P" pad="06"/>
+<connect gate="_A05" pin="P" pad="07"/>
+<connect gate="_A06" pin="P" pad="08"/>
+<connect gate="_A07" pin="P" pad="09"/>
+<connect gate="_A08" pin="P" pad="10"/>
+<connect gate="_A09" pin="P" pad="11"/>
+<connect gate="_A10" pin="P" pad="12"/>
+<connect gate="_A11" pin="P" pad="13"/>
+<connect gate="_A12" pin="P" pad="14"/>
+<connect gate="_A13" pin="P" pad="15"/>
+<connect gate="_A14" pin="P" pad="16"/>
+<connect gate="_A15" pin="P" pad="17"/>
+<connect gate="_D0" pin="P" pad="49"/>
+<connect gate="_D1" pin="P" pad="48"/>
+<connect gate="_D2" pin="P" pad="47"/>
+<connect gate="_D3" pin="P" pad="46"/>
+<connect gate="_D4" pin="P" pad="45"/>
+<connect gate="_D5" pin="P" pad="44"/>
+<connect gate="_D6" pin="P" pad="43"/>
+<connect gate="_D7" pin="P" pad="42"/>
+<connect gate="_DEVSELECT\" pin="P" pad="41"/>
+<connect gate="_DMA\" pin="P" pad="22"/>
+<connect gate="_DMA_IN" pin="P" pad="27"/>
+<connect gate="_DMA_OUT" pin="P" pad="24"/>
+<connect gate="_GND" pin="P" pad="26"/>
+<connect gate="_INH\" pin="P" pad="32"/>
+<connect gate="_INT_IN" pin="P" pad="28"/>
+<connect gate="_INT_OUT" pin="P" pad="23"/>
+<connect gate="_IOSELECT\" pin="P" pad="01"/>
+<connect gate="_IOSTR\" pin="P" pad="20"/>
+<connect gate="_IRQ\" pin="P" pad="30"/>
+<connect gate="_NC@1" pin="P" pad="19"/>
+<connect gate="_NC@2" pin="P" pad="35"/>
+<connect gate="_NMI\" pin="P" pad="29"/>
+<connect gate="_Q3" pin="P" pad="37"/>
+<connect gate="_RDY" pin="P" pad="21"/>
+<connect gate="_RES\" pin="P" pad="31"/>
+<connect gate="_RW" pin="P" pad="18"/>
+<connect gate="_USER1" pin="P" pad="39"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="A2GSRAM-44PIN" prefix="ST" uservalue="yes">
+<description>&lt;B&gt;Apple IIgs Memory Expansion Slot 44-pin&lt;/B&gt;
+&lt;br /&gt;
+This is the 44-pin board dimensions for an Apple IIgs Memory Expansion Card
+&lt;br /&gt;
+Pins are laid out as seen from the top of the slot. Pin 1 is towards the front of the case/keyboard</description>
+<gates>
+<gate name="_GND@5" symbol="ATPIN" x="-5.08" y="-38.1" addlevel="always"/>
+<gate name="_+5V@5" symbol="ATPIN" x="-5.08" y="-35.56" addlevel="always"/>
+<gate name="_A15" symbol="ATPIN" x="-5.08" y="-33.02" addlevel="always"/>
+<gate name="_A14" symbol="ATPIN" x="-5.08" y="-30.48" addlevel="always"/>
+<gate name="_A13" symbol="ATPIN" x="-5.08" y="-27.94" addlevel="always"/>
+<gate name="_A12" symbol="ATPIN" x="-5.08" y="-25.4" addlevel="always"/>
+<gate name="_A11" symbol="ATPIN" x="-5.08" y="-22.86" addlevel="always"/>
+<gate name="_A10" symbol="ATPIN" x="-5.08" y="-20.32" addlevel="always"/>
+<gate name="_D1" symbol="ATPIN" x="-5.08" y="-17.78" addlevel="always"/>
+<gate name="_CRAS\" symbol="ATPIN" x="-5.08" y="-15.24" addlevel="always"/>
+<gate name="_GND@4" symbol="ATPIN" x="-5.08" y="-12.7" addlevel="always"/>
+<gate name="_D3" symbol="ATPIN" x="-5.08" y="-10.16" addlevel="always"/>
+<gate name="_ABORT" symbol="ATPIN" x="-5.08" y="-7.62" addlevel="always"/>
+<gate name="_02" symbol="ATPIN" x="-5.08" y="-5.08" addlevel="always"/>
+<gate name="_D5" symbol="ATPIN" x="-5.08" y="-2.54" addlevel="always"/>
+<gate name="_D4" symbol="ATPIN" x="-5.08" y="0" addlevel="always"/>
+<gate name="_D6" symbol="ATPIN" x="-5.08" y="2.54" addlevel="always"/>
+<gate name="_MSIZE" symbol="ATPIN" x="-5.08" y="5.08" addlevel="always"/>
+<gate name="_CSEL\" symbol="ATPIN" x="-5.08" y="7.62" addlevel="always"/>
+<gate name="_GND@3" symbol="ATPIN" x="-5.08" y="10.16" addlevel="always"/>
+<gate name="_+5V@4" symbol="ATPIN" x="-5.08" y="12.7" addlevel="always"/>
+<gate name="_D0" symbol="ATPIN" x="-5.08" y="15.24" addlevel="always"/>
+<gate name="_GND@1" symbol="ATPIN" x="27.94" y="-38.1" addlevel="always"/>
+<gate name="_+5V@1" symbol="ATPIN" x="27.94" y="-35.56" addlevel="always"/>
+<gate name="_FRA9" symbol="ATPIN" x="27.94" y="-33.02" addlevel="always"/>
+<gate name="_FRA8" symbol="ATPIN" x="27.94" y="-30.48" addlevel="always"/>
+<gate name="_D2" symbol="ATPIN" x="27.94" y="-27.94" addlevel="always"/>
+<gate name="_FRA6" symbol="ATPIN" x="27.94" y="-25.4" addlevel="always"/>
+<gate name="_FRA3" symbol="ATPIN" x="27.94" y="-22.86" addlevel="always"/>
+<gate name="_FRA4" symbol="ATPIN" x="27.94" y="-20.32" addlevel="always"/>
+<gate name="_FRA5" symbol="ATPIN" x="27.94" y="-17.78" addlevel="always"/>
+<gate name="_FRA7" symbol="ATPIN" x="27.94" y="-15.24" addlevel="always"/>
+<gate name="_+5V@2" symbol="ATPIN" x="27.94" y="-12.7" addlevel="always"/>
+<gate name="_FR/W" symbol="ATPIN" x="27.94" y="-10.16" addlevel="always"/>
+<gate name="_FRA0" symbol="ATPIN" x="27.94" y="-7.62" addlevel="always"/>
+<gate name="_FRA2" symbol="ATPIN" x="27.94" y="-5.08" addlevel="always"/>
+<gate name="_FRA1" symbol="ATPIN" x="27.94" y="-2.54" addlevel="always"/>
+<gate name="_D7" symbol="ATPIN" x="27.94" y="0" addlevel="always"/>
+<gate name="_CCAS\" symbol="ATPIN" x="27.94" y="2.54" addlevel="always"/>
+<gate name="_CROW0" symbol="ATPIN" x="27.94" y="5.08" addlevel="always"/>
+<gate name="_CROW1" symbol="ATPIN" x="27.94" y="7.62" addlevel="always"/>
+<gate name="_CROMSEL\" symbol="ATPIN" x="27.94" y="10.16" addlevel="always"/>
+<gate name="_+5V@3" symbol="ATPIN" x="27.94" y="12.7" addlevel="always"/>
+<gate name="_GND@2" symbol="ATPIN" x="27.94" y="15.24" addlevel="always"/>
+</gates>
+<devices>
+<device name="IIGS-RAM" package="A2GS-44PIN-MEM">
+<connects>
+<connect gate="_+5V@1" pin="P" pad="02"/>
+<connect gate="_+5V@2" pin="P" pad="11"/>
+<connect gate="_+5V@3" pin="P" pad="21"/>
+<connect gate="_+5V@4" pin="P" pad="24"/>
+<connect gate="_+5V@5" pin="P" pad="43"/>
+<connect gate="_02" pin="P" pad="31"/>
+<connect gate="_A10" pin="P" pad="37"/>
+<connect gate="_A11" pin="P" pad="38"/>
+<connect gate="_A12" pin="P" pad="39"/>
+<connect gate="_A13" pin="P" pad="40"/>
+<connect gate="_A14" pin="P" pad="41"/>
+<connect gate="_A15" pin="P" pad="42"/>
+<connect gate="_ABORT" pin="P" pad="32"/>
+<connect gate="_CCAS\" pin="P" pad="17"/>
+<connect gate="_CRAS\" pin="P" pad="35"/>
+<connect gate="_CROMSEL\" pin="P" pad="20"/>
+<connect gate="_CROW0" pin="P" pad="18"/>
+<connect gate="_CROW1" pin="P" pad="19"/>
+<connect gate="_CSEL\" pin="P" pad="26"/>
+<connect gate="_D0" pin="P" pad="25"/>
+<connect gate="_D1" pin="P" pad="36"/>
+<connect gate="_D2" pin="P" pad="05"/>
+<connect gate="_D3" pin="P" pad="33"/>
+<connect gate="_D4" pin="P" pad="29"/>
+<connect gate="_D5" pin="P" pad="30"/>
+<connect gate="_D6" pin="P" pad="28"/>
+<connect gate="_D7" pin="P" pad="16"/>
+<connect gate="_FR/W" pin="P" pad="12"/>
+<connect gate="_FRA0" pin="P" pad="13"/>
+<connect gate="_FRA1" pin="P" pad="15"/>
+<connect gate="_FRA2" pin="P" pad="14"/>
+<connect gate="_FRA3" pin="P" pad="07"/>
+<connect gate="_FRA4" pin="P" pad="08"/>
+<connect gate="_FRA5" pin="P" pad="09"/>
+<connect gate="_FRA6" pin="P" pad="06"/>
+<connect gate="_FRA7" pin="P" pad="10"/>
+<connect gate="_FRA8" pin="P" pad="04"/>
+<connect gate="_FRA9" pin="P" pad="03"/>
+<connect gate="_GND@1" pin="P" pad="01"/>
+<connect gate="_GND@2" pin="P" pad="22"/>
+<connect gate="_GND@3" pin="P" pad="23"/>
+<connect gate="_GND@4" pin="P" pad="34"/>
+<connect gate="_GND@5" pin="P" pad="44"/>
+<connect gate="_MSIZE" pin="P" pad="27"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>
diff --git a/Hardware/pda.lbr b/Hardware/pda.lbr
new file mode 100644
index 0000000..46c59ca
--- /dev/null
+++ b/Hardware/pda.lbr
@@ -0,0 +1,2930 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.1.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.05" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
+<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="53" name="tGND_GNDA" color="7" fill="9" visible="no" active="no"/>
+<layer number="54" name="bGND_GNDA" color="1" fill="9" visible="no" active="no"/>
+<layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/>
+<layer number="57" name="tCAD" color="7" fill="1" visible="no" active="no"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="99" name="SpiceOrder" color="7" fill="1" visible="no" active="no"/>
+<layer number="100" name="Muster" color="7" fill="1" visible="no" active="no"/>
+<layer number="101" name="Patch_Top" color="12" fill="4" visible="yes" active="yes"/>
+<layer number="102" name="Vscore" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="103" name="tMap" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="104" name="Name" color="16" fill="1" visible="yes" active="yes"/>
+<layer number="105" name="tPlate" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="106" name="bPlate" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="107" name="Crop" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="108" name="tplace-old" color="10" fill="1" visible="yes" active="yes"/>
+<layer number="109" name="ref-old" color="11" fill="1" visible="yes" active="yes"/>
+<layer number="110" name="fp0" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="111" name="LPC17xx" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="112" name="tSilk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="113" name="IDFDebug" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="116" name="Patch_BOT" color="9" fill="4" visible="yes" active="yes"/>
+<layer number="121" name="_tsilk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="122" name="_bsilk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="123" name="tTestmark" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="124" name="bTestmark" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="125" name="_tNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="126" name="_bNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="127" name="_tValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="128" name="_bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="131" name="tAdjust" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="132" name="bAdjust" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="144" name="Drill_legend" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="150" name="Notes" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="151" name="HeatSink" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="152" name="_bDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="153" name="FabDoc1" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="154" name="FabDoc2" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="155" name="FabDoc3" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="199" name="Contour" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="200" name="200bmp" color="1" fill="10" visible="yes" active="yes"/>
+<layer number="201" name="201bmp" color="2" fill="10" visible="yes" active="yes"/>
+<layer number="202" name="202bmp" color="3" fill="10" visible="yes" active="yes"/>
+<layer number="203" name="203bmp" color="4" fill="10" visible="yes" active="yes"/>
+<layer number="204" name="204bmp" color="5" fill="10" visible="yes" active="yes"/>
+<layer number="205" name="205bmp" color="6" fill="10" visible="yes" active="yes"/>
+<layer number="206" name="206bmp" color="7" fill="10" visible="yes" active="yes"/>
+<layer number="207" name="207bmp" color="8" fill="10" visible="yes" active="yes"/>
+<layer number="208" name="208bmp" color="9" fill="10" visible="yes" active="yes"/>
+<layer number="209" name="209bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="210" name="210bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="211" name="211bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="212" name="212bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="213" name="213bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="214" name="214bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="215" name="215bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="216" name="216bmp" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="217" name="217bmp" color="18" fill="1" visible="no" active="no"/>
+<layer number="218" name="218bmp" color="19" fill="1" visible="no" active="no"/>
+<layer number="219" name="219bmp" color="20" fill="1" visible="no" active="no"/>
+<layer number="220" name="220bmp" color="21" fill="1" visible="no" active="no"/>
+<layer number="221" name="221bmp" color="22" fill="1" visible="no" active="no"/>
+<layer number="222" name="222bmp" color="23" fill="1" visible="no" active="no"/>
+<layer number="223" name="223bmp" color="24" fill="1" visible="no" active="no"/>
+<layer number="224" name="224bmp" color="25" fill="1" visible="no" active="no"/>
+<layer number="248" name="Housing" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="249" name="Edge" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="250" name="Descript" color="3" fill="1" visible="no" active="no"/>
+<layer number="251" name="SMDround" color="12" fill="11" visible="no" active="no"/>
+<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/>
+</layers>
+<library>
+<packages>
+<package name="DIP40">
+<wire x1="-26.416" y1="-1.27" x2="-26.416" y2="-6.604" width="0.127" layer="21"/>
+<wire x1="-26.416" y1="1.27" x2="-26.416" y2="-1.27" width="0.127" layer="21" curve="-180"/>
+<wire x1="26.416" y1="-6.604" x2="26.416" y2="6.604" width="0.127" layer="21"/>
+<wire x1="-26.416" y1="6.604" x2="-26.416" y2="1.27" width="0.127" layer="21"/>
+<wire x1="-26.416" y1="6.604" x2="26.416" y2="6.604" width="0.127" layer="21"/>
+<wire x1="-26.416" y1="-6.604" x2="26.416" y2="-6.604" width="0.127" layer="21"/>
+<pad name="1" x="-24.13" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="2" x="-21.59" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="3" x="-19.05" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="4" x="-16.51" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="5" x="-13.97" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="6" x="-11.43" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="7" x="-8.89" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="8" x="-6.35" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="9" x="-3.81" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="10" x="-1.27" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="11" x="1.27" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="12" x="3.81" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="13" x="6.35" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="14" x="8.89" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="15" x="11.43" y="-7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
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+<pad name="35" x="-11.43" y="7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="36" x="-13.97" y="7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
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+<pad name="38" x="-19.05" y="7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="39" x="-21.59" y="7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<pad name="40" x="-24.13" y="7.62" drill="0.6096" diameter="1.27" shape="long" rot="R90"/>
+<text x="-21.59" y="0.635" size="1.778" layer="25" ratio="10">&gt;NAME</text>
+<text x="-23.495" y="-6.0198" size="1.27" layer="21" ratio="10" rot="R90">1</text>
+<text x="-23.495" y="4.1402" size="1.27" layer="21" ratio="10" rot="R90">40</text>
+<text x="24.7396" y="-6.0198" size="1.27" layer="21" ratio="10" rot="R90">20</text>
+<text x="24.765" y="4.1402" size="1.27" layer="21" ratio="10" rot="R90">21</text>
+<text x="-21.59" y="-2.2352" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="DIP28-WIDE">
+<wire x1="-18.542" y1="1.27" x2="-18.542" y2="-1.27" width="0.1524" layer="21" curve="-180"/>
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+<pad name="4" x="-8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
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+<pad name="16" x="13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
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+<connect gate="G$1" pin="D4" pad="29"/>
+<connect gate="G$1" pin="D5" pad="28"/>
+<connect gate="G$1" pin="D6" pad="27"/>
+<connect gate="G$1" pin="D7" pad="26"/>
+<connect gate="G$1" pin="IRQB" pad="4"/>
+<connect gate="G$1" pin="MLB" pad="5"/>
+<connect gate="G$1" pin="NC" pad="35"/>
+<connect gate="G$1" pin="NMIB" pad="6"/>
+<connect gate="G$1" pin="PHI1O" pad="3"/>
+<connect gate="G$1" pin="PHI2" pad="37"/>
+<connect gate="G$1" pin="PHI2O" pad="39"/>
+<connect gate="G$1" pin="RDY" pad="2"/>
+<connect gate="G$1" pin="RESB" pad="40"/>
+<connect gate="G$1" pin="RWB" pad="34"/>
+<connect gate="G$1" pin="SOB" pad="38"/>
+<connect gate="G$1" pin="SYNC" pad="7"/>
+<connect gate="G$1" pin="VDD" pad="8"/>
+<connect gate="G$1" pin="VPB" pad="1"/>
+<connect gate="G$1" pin="VSS" pad="21"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="PLCC44" package="PLCC44-SOCKET">
+<connects>
+<connect gate="G$1" pin="A0" pad="10"/>
+<connect gate="G$1" pin="A1" pad="11"/>
+<connect gate="G$1" pin="A10" pad="21"/>
+<connect gate="G$1" pin="A11" pad="22"/>
+<connect gate="G$1" pin="A12" pad="25"/>
+<connect gate="G$1" pin="A13" pad="26"/>
+<connect gate="G$1" pin="A14" pad="27"/>
+<connect gate="G$1" pin="A15" pad="28"/>
+<connect gate="G$1" pin="A2" pad="13"/>
+<connect gate="G$1" pin="A3" pad="14"/>
+<connect gate="G$1" pin="A4" pad="15"/>
+<connect gate="G$1" pin="A5" pad="16"/>
+<connect gate="G$1" pin="A6" pad="17"/>
+<connect gate="G$1" pin="A7" pad="18"/>
+<connect gate="G$1" pin="A8" pad="19"/>
+<connect gate="G$1" pin="A9" pad="20"/>
+<connect gate="G$1" pin="BE" pad="40"/>
+<connect gate="G$1" pin="D0" pad="36"/>
+<connect gate="G$1" pin="D1" pad="35"/>
+<connect gate="G$1" pin="D2" pad="34"/>
+<connect gate="G$1" pin="D3" pad="33"/>
+<connect gate="G$1" pin="D4" pad="32"/>
+<connect gate="G$1" pin="D5" pad="31"/>
+<connect gate="G$1" pin="D6" pad="30"/>
+<connect gate="G$1" pin="D7" pad="29"/>
+<connect gate="G$1" pin="IRQB" pad="5"/>
+<connect gate="G$1" pin="MLB" pad="6"/>
+<connect gate="G$1" pin="NC" pad="12 39"/>
+<connect gate="G$1" pin="NMIB" pad="7"/>
+<connect gate="G$1" pin="PHI1O" pad="4"/>
+<connect gate="G$1" pin="PHI2" pad="41"/>
+<connect gate="G$1" pin="PHI2O" pad="43"/>
+<connect gate="G$1" pin="RDY" pad="3"/>
+<connect gate="G$1" pin="RESB" pad="44"/>
+<connect gate="G$1" pin="RWB" pad="38"/>
+<connect gate="G$1" pin="SOB" pad="42"/>
+<connect gate="G$1" pin="SYNC" pad="8"/>
+<connect gate="G$1" pin="VDD" pad="9 37"/>
+<connect gate="G$1" pin="VPB" pad="2"/>
+<connect gate="G$1" pin="VSS" pad="1 23 24"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="W65C22" prefix="U" uservalue="yes">
+<description>The W65C22 (W65C22N and W65C22S) Versatile Interface Adapter (VIA) is a
+flexible I/O device for use with the 65xx series microprocessor family. The
+W65C22 includes functions for programmed control of two peripheral ports (Ports
+A and B). Two program controlled 8-bit bidirectional peripheral I/O ports allow
+direct interfacing between the microprocessor and selected peripheral units.
+Each port has input data latching capability. Two programmable Data Direction
+Registers (A and B) allow selection of data direction (input or output) on an
+individual line basis. Also provided are two programmable 16-bit Interval
+Timer/Counters with latches. Timer 1 may be operated in a One-Shot Interrupt
+Mode with interrupts on each count to zero, or in a Free-Run Mode with a
+continuous series of evenly spaced interrupts. Timer 2 functions as both an
+interval and pulse counter. Serial Data transfers are provided by a serial to
+parallel/parallel to serial shift register. Application versatility is further
+increased by various control registers, including an Interrupt Flag Register,
+an Interrupt Enable Register and two Function Control Registers.</description>
+<gates>
+<gate name="G$1" symbol="W65C22" x="0" y="0"/>
+</gates>
+<devices>
+<device name="DIP40" package="DIP40">
+<connects>
+<connect gate="G$1" pin="CA1" pad="40"/>
+<connect gate="G$1" pin="CA2" pad="39"/>
+<connect gate="G$1" pin="CB1" pad="18"/>
+<connect gate="G$1" pin="CB2" pad="19"/>
+<connect gate="G$1" pin="CS1" pad="24"/>
+<connect gate="G$1" pin="CS2B" pad="23"/>
+<connect gate="G$1" pin="D0" pad="33"/>
+<connect gate="G$1" pin="D1" pad="32"/>
+<connect gate="G$1" pin="D2" pad="31"/>
+<connect gate="G$1" pin="D3" pad="30"/>
+<connect gate="G$1" pin="D4" pad="29"/>
+<connect gate="G$1" pin="D5" pad="28"/>
+<connect gate="G$1" pin="D6" pad="27"/>
+<connect gate="G$1" pin="D7" pad="26"/>
+<connect gate="G$1" pin="IRQB" pad="21"/>
+<connect gate="G$1" pin="PA0" pad="2"/>
+<connect gate="G$1" pin="PA1" pad="3"/>
+<connect gate="G$1" pin="PA2" pad="4"/>
+<connect gate="G$1" pin="PA3" pad="5"/>
+<connect gate="G$1" pin="PA4" pad="6"/>
+<connect gate="G$1" pin="PA5" pad="7"/>
+<connect gate="G$1" pin="PA6" pad="8"/>
+<connect gate="G$1" pin="PA7" pad="9"/>
+<connect gate="G$1" pin="PB0" pad="10"/>
+<connect gate="G$1" pin="PB1" pad="11"/>
+<connect gate="G$1" pin="PB2" pad="12"/>
+<connect gate="G$1" pin="PB3" pad="13"/>
+<connect gate="G$1" pin="PB4" pad="14"/>
+<connect gate="G$1" pin="PB5" pad="15"/>
+<connect gate="G$1" pin="PB6" pad="16"/>
+<connect gate="G$1" pin="PB7" pad="17"/>
+<connect gate="G$1" pin="PHI2" pad="25"/>
+<connect gate="G$1" pin="RESB" pad="34"/>
+<connect gate="G$1" pin="RS0" pad="38"/>
+<connect gate="G$1" pin="RS1" pad="37"/>
+<connect gate="G$1" pin="RS2" pad="36"/>
+<connect gate="G$1" pin="RS3" pad="35"/>
+<connect gate="G$1" pin="RWB" pad="22"/>
+<connect gate="G$1" pin="VDD" pad="20"/>
+<connect gate="G$1" pin="VSS" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="PLCC44-SOCKET" package="PLCC44-SOCKET">
+<connects>
+<connect gate="G$1" pin="CA1" pad="44"/>
+<connect gate="G$1" pin="CA2" pad="43"/>
+<connect gate="G$1" pin="CB1" pad="19"/>
+<connect gate="G$1" pin="CB2" pad="20"/>
+<connect gate="G$1" pin="CS1" pad="26"/>
+<connect gate="G$1" pin="CS2B" pad="25"/>
+<connect gate="G$1" pin="D0" pad="36"/>
+<connect gate="G$1" pin="D1" pad="35"/>
+<connect gate="G$1" pin="D2" pad="34"/>
+<connect gate="G$1" pin="D3" pad="32"/>
+<connect gate="G$1" pin="D4" pad="31"/>
+<connect gate="G$1" pin="D5" pad="30"/>
+<connect gate="G$1" pin="D6" pad="29"/>
+<connect gate="G$1" pin="D7" pad="28"/>
+<connect gate="G$1" pin="IRQB" pad="23"/>
+<connect gate="G$1" pin="PA0" pad="2"/>
+<connect gate="G$1" pin="PA1" pad="3"/>
+<connect gate="G$1" pin="PA2" pad="4"/>
+<connect gate="G$1" pin="PA3" pad="5"/>
+<connect gate="G$1" pin="PA4" pad="6"/>
+<connect gate="G$1" pin="PA5" pad="7"/>
+<connect gate="G$1" pin="PA6" pad="8"/>
+<connect gate="G$1" pin="PA7" pad="9"/>
+<connect gate="G$1" pin="PB0" pad="10"/>
+<connect gate="G$1" pin="PB1" pad="12"/>
+<connect gate="G$1" pin="PB2" pad="13"/>
+<connect gate="G$1" pin="PB3" pad="14"/>
+<connect gate="G$1" pin="PB4" pad="15"/>
+<connect gate="G$1" pin="PB5" pad="16"/>
+<connect gate="G$1" pin="PB6" pad="17"/>
+<connect gate="G$1" pin="PB7" pad="18"/>
+<connect gate="G$1" pin="PHI2" pad="27"/>
+<connect gate="G$1" pin="RESB" pad="37"/>
+<connect gate="G$1" pin="RS0" pad="42"/>
+<connect gate="G$1" pin="RS1" pad="41"/>
+<connect gate="G$1" pin="RS2" pad="40"/>
+<connect gate="G$1" pin="RS3" pad="39"/>
+<connect gate="G$1" pin="RWB" pad="24"/>
+<connect gate="G$1" pin="VDD" pad="21"/>
+<connect gate="G$1" pin="VSS" pad="1"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="UM61256AK-12" prefix="U" uservalue="yes">
+<description>5V 32K x 8 CMOS 12ns SRAM</description>
+<gates>
+<gate name="G$1" symbol="61256" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="DIL28-3">
+<connects>
+<connect gate="G$1" pin="!CE" pad="20"/>
+<connect gate="G$1" pin="!OE" pad="22"/>
+<connect gate="G$1" pin="!WE" pad="27"/>
+<connect gate="G$1" pin="A0" pad="10"/>
+<connect gate="G$1" pin="A1" pad="9"/>
+<connect gate="G$1" pin="A10" pad="21"/>
+<connect gate="G$1" pin="A11" pad="23"/>
+<connect gate="G$1" pin="A12" pad="2"/>
+<connect gate="G$1" pin="A13" pad="26"/>
+<connect gate="G$1" pin="A14" pad="1"/>
+<connect gate="G$1" pin="A2" pad="8"/>
+<connect gate="G$1" pin="A3" pad="7"/>
+<connect gate="G$1" pin="A4" pad="6"/>
+<connect gate="G$1" pin="A5" pad="5"/>
+<connect gate="G$1" pin="A6" pad="4"/>
+<connect gate="G$1" pin="A7" pad="3"/>
+<connect gate="G$1" pin="A8" pad="25"/>
+<connect gate="G$1" pin="A9" pad="24"/>
+<connect gate="G$1" pin="GND" pad="14"/>
+<connect gate="G$1" pin="I/O0" pad="11"/>
+<connect gate="G$1" pin="I/O1" pad="12"/>
+<connect gate="G$1" pin="I/O2" pad="13"/>
+<connect gate="G$1" pin="I/O3" pad="15"/>
+<connect gate="G$1" pin="I/O4" pad="16"/>
+<connect gate="G$1" pin="I/O5" pad="17"/>
+<connect gate="G$1" pin="I/O6" pad="18"/>
+<connect gate="G$1" pin="I/O7" pad="19"/>
+<connect gate="G$1" pin="VCC" pad="28"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="28C64" prefix="U" uservalue="yes">
+<description>5V 8K x 8 CMOS EEPROM</description>
+<gates>
+<gate name="G$1" symbol="28C64" x="0" y="0"/>
+</gates>
+<devices>
+<device name="DIP28-6-WIDE" package="DIP28-WIDE">
+<connects>
+<connect gate="G$1" pin="!CE" pad="20"/>
+<connect gate="G$1" pin="!OE" pad="22"/>
+<connect gate="G$1" pin="!WE" pad="27"/>
+<connect gate="G$1" pin="A0" pad="10"/>
+<connect gate="G$1" pin="A1" pad="9"/>
+<connect gate="G$1" pin="A10" pad="21"/>
+<connect gate="G$1" pin="A11" pad="23"/>
+<connect gate="G$1" pin="A12" pad="2"/>
+<connect gate="G$1" pin="A2" pad="8"/>
+<connect gate="G$1" pin="A3" pad="7"/>
+<connect gate="G$1" pin="A4" pad="6"/>
+<connect gate="G$1" pin="A5" pad="5"/>
+<connect gate="G$1" pin="A6" pad="4"/>
+<connect gate="G$1" pin="A7" pad="3"/>
+<connect gate="G$1" pin="A8" pad="25"/>
+<connect gate="G$1" pin="A9" pad="24"/>
+<connect gate="G$1" pin="D0" pad="11"/>
+<connect gate="G$1" pin="D1" pad="12"/>
+<connect gate="G$1" pin="D2" pad="13"/>
+<connect gate="G$1" pin="D3" pad="15"/>
+<connect gate="G$1" pin="D4" pad="16"/>
+<connect gate="G$1" pin="D5" pad="17"/>
+<connect gate="G$1" pin="D6" pad="18"/>
+<connect gate="G$1" pin="D7" pad="19"/>
+<connect gate="G$1" pin="GND" pad="14"/>
+<connect gate="G$1" pin="NC@1" pad="1"/>
+<connect gate="G$1" pin="NC@2" pad="26"/>
+<connect gate="G$1" pin="VCC" pad="28"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="ZIF28-6-WIDE" package="ZIF28-6-WIDE">
+<connects>
+<connect gate="G$1" pin="!CE" pad="20"/>
+<connect gate="G$1" pin="!OE" pad="22"/>
+<connect gate="G$1" pin="!WE" pad="27"/>
+<connect gate="G$1" pin="A0" pad="10"/>
+<connect gate="G$1" pin="A1" pad="9"/>
+<connect gate="G$1" pin="A10" pad="21"/>
+<connect gate="G$1" pin="A11" pad="23"/>
+<connect gate="G$1" pin="A12" pad="2"/>
+<connect gate="G$1" pin="A2" pad="8"/>
+<connect gate="G$1" pin="A3" pad="7"/>
+<connect gate="G$1" pin="A4" pad="6"/>
+<connect gate="G$1" pin="A5" pad="5"/>
+<connect gate="G$1" pin="A6" pad="4"/>
+<connect gate="G$1" pin="A7" pad="3"/>
+<connect gate="G$1" pin="A8" pad="25"/>
+<connect gate="G$1" pin="A9" pad="24"/>
+<connect gate="G$1" pin="D0" pad="11"/>
+<connect gate="G$1" pin="D1" pad="12"/>
+<connect gate="G$1" pin="D2" pad="13"/>
+<connect gate="G$1" pin="D3" pad="15"/>
+<connect gate="G$1" pin="D4" pad="16"/>
+<connect gate="G$1" pin="D5" pad="17"/>
+<connect gate="G$1" pin="D6" pad="18"/>
+<connect gate="G$1" pin="D7" pad="19"/>
+<connect gate="G$1" pin="GND" pad="14"/>
+<connect gate="G$1" pin="NC@1" pad="1"/>
+<connect gate="G$1" pin="NC@2" pad="26"/>
+<connect gate="G$1" pin="VCC" pad="28"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="28C256" prefix="U">
+<gates>
+<gate name="G$1" symbol="28C256" x="0" y="0"/>
+</gates>
+<devices>
+<device name="-ZIF" package="ZIF28-6-WIDE">
+<connects>
+<connect gate="G$1" pin="!CE" pad="20"/>
+<connect gate="G$1" pin="!OE" pad="22"/>
+<connect gate="G$1" pin="!WE" pad="27"/>
+<connect gate="G$1" pin="A0" pad="10"/>
+<connect gate="G$1" pin="A1" pad="9"/>
+<connect gate="G$1" pin="A10" pad="21"/>
+<connect gate="G$1" pin="A11" pad="23"/>
+<connect gate="G$1" pin="A12" pad="2"/>
+<connect gate="G$1" pin="A13" pad="26"/>
+<connect gate="G$1" pin="A14" pad="1"/>
+<connect gate="G$1" pin="A2" pad="8"/>
+<connect gate="G$1" pin="A3" pad="7"/>
+<connect gate="G$1" pin="A4" pad="6"/>
+<connect gate="G$1" pin="A5" pad="5"/>
+<connect gate="G$1" pin="A6" pad="4"/>
+<connect gate="G$1" pin="A7" pad="3"/>
+<connect gate="G$1" pin="A8" pad="25"/>
+<connect gate="G$1" pin="A9" pad="24"/>
+<connect gate="G$1" pin="D0" pad="11"/>
+<connect gate="G$1" pin="D1" pad="12"/>
+<connect gate="G$1" pin="D2" pad="13"/>
+<connect gate="G$1" pin="D3" pad="15"/>
+<connect gate="G$1" pin="D4" pad="16"/>
+<connect gate="G$1" pin="D5" pad="17"/>
+<connect gate="G$1" pin="D6" pad="18"/>
+<connect gate="G$1" pin="D7" pad="19"/>
+<connect gate="G$1" pin="GND" pad="14"/>
+<connect gate="G$1" pin="VCC" pad="28"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="JMP-1X2" prefix="JP" uservalue="yes">
+<description>&lt;b&gt;JUMPER&lt;/b&gt;</description>
+<gates>
+<gate name="A" symbol="JMP-1X2" x="0" y="0"/>
+</gates>
+<devices>
+<device name="TH" package="JMP-1X2">
+<connects>
+<connect gate="A" pin="1" pad="1"/>
+<connect gate="A" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="JP2E" prefix="JP" uservalue="yes">
+<description>&lt;b&gt;JUMPER&lt;/b&gt;</description>
+<gates>
+<gate name="1" symbol="JP3E" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="JP2">
+<connects>
+<connect gate="1" pin="1" pad="1"/>
+<connect gate="1" pin="2" pad="2"/>
+<connect gate="1" pin="3" pad="3"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="XO-" prefix="QG" uservalue="yes">
+<description>&lt;b&gt;CRYSTAL&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="QG3" x="0" y="0"/>
+</gates>
+<devices>
+<device name="8" package="DIL08S">
+<connects>
+<connect gate="G$1" pin="GND" pad="4"/>
+<connect gate="G$1" pin="OUT" pad="5"/>
+<connect gate="G$1" pin="TS" pad="1"/>
+<connect gate="G$1" pin="VCC" pad="8"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+<device name="14" package="DIL14S">
+<connects>
+<connect gate="G$1" pin="GND" pad="7"/>
+<connect gate="G$1" pin="OUT" pad="8"/>
+<connect gate="G$1" pin="TS" pad="1"/>
+<connect gate="G$1" pin="VCC" pad="14"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="PINHD-2X20" prefix="JP" uservalue="yes">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<gates>
+<gate name="A" symbol="PINH2X20" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="2X20">
+<connects>
+<connect gate="A" pin="1" pad="1"/>
+<connect gate="A" pin="10" pad="10"/>
+<connect gate="A" pin="11" pad="11"/>
+<connect gate="A" pin="12" pad="12"/>
+<connect gate="A" pin="13" pad="13"/>
+<connect gate="A" pin="14" pad="14"/>
+<connect gate="A" pin="15" pad="15"/>
+<connect gate="A" pin="16" pad="16"/>
+<connect gate="A" pin="17" pad="17"/>
+<connect gate="A" pin="18" pad="18"/>
+<connect gate="A" pin="19" pad="19"/>
+<connect gate="A" pin="2" pad="2"/>
+<connect gate="A" pin="20" pad="20"/>
+<connect gate="A" pin="21" pad="21"/>
+<connect gate="A" pin="22" pad="22"/>
+<connect gate="A" pin="23" pad="23"/>
+<connect gate="A" pin="24" pad="24"/>
+<connect gate="A" pin="25" pad="25"/>
+<connect gate="A" pin="26" pad="26"/>
+<connect gate="A" pin="27" pad="27"/>
+<connect gate="A" pin="28" pad="28"/>
+<connect gate="A" pin="29" pad="29"/>
+<connect gate="A" pin="3" pad="3"/>
+<connect gate="A" pin="30" pad="30"/>
+<connect gate="A" pin="31" pad="31"/>
+<connect gate="A" pin="32" pad="32"/>
+<connect gate="A" pin="33" pad="33"/>
+<connect gate="A" pin="34" pad="34"/>
+<connect gate="A" pin="35" pad="35"/>
+<connect gate="A" pin="36" pad="36"/>
+<connect gate="A" pin="37" pad="37"/>
+<connect gate="A" pin="38" pad="38"/>
+<connect gate="A" pin="39" pad="39"/>
+<connect gate="A" pin="4" pad="4"/>
+<connect gate="A" pin="40" pad="40"/>
+<connect gate="A" pin="5" pad="5"/>
+<connect gate="A" pin="6" pad="6"/>
+<connect gate="A" pin="7" pad="7"/>
+<connect gate="A" pin="8" pad="8"/>
+<connect gate="A" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-BIG" package="2X20-BIG">
+<connects>
+<connect gate="A" pin="1" pad="1"/>
+<connect gate="A" pin="10" pad="10"/>
+<connect gate="A" pin="11" pad="11"/>
+<connect gate="A" pin="12" pad="12"/>
+<connect gate="A" pin="13" pad="13"/>
+<connect gate="A" pin="14" pad="14"/>
+<connect gate="A" pin="15" pad="15"/>
+<connect gate="A" pin="16" pad="16"/>
+<connect gate="A" pin="17" pad="17"/>
+<connect gate="A" pin="18" pad="18"/>
+<connect gate="A" pin="19" pad="19"/>
+<connect gate="A" pin="2" pad="2"/>
+<connect gate="A" pin="20" pad="20"/>
+<connect gate="A" pin="21" pad="21"/>
+<connect gate="A" pin="22" pad="22"/>
+<connect gate="A" pin="23" pad="23"/>
+<connect gate="A" pin="24" pad="24"/>
+<connect gate="A" pin="25" pad="25"/>
+<connect gate="A" pin="26" pad="26"/>
+<connect gate="A" pin="27" pad="27"/>
+<connect gate="A" pin="28" pad="28"/>
+<connect gate="A" pin="29" pad="29"/>
+<connect gate="A" pin="3" pad="3"/>
+<connect gate="A" pin="30" pad="30"/>
+<connect gate="A" pin="31" pad="31"/>
+<connect gate="A" pin="32" pad="32"/>
+<connect gate="A" pin="33" pad="33"/>
+<connect gate="A" pin="34" pad="34"/>
+<connect gate="A" pin="35" pad="35"/>
+<connect gate="A" pin="36" pad="36"/>
+<connect gate="A" pin="37" pad="37"/>
+<connect gate="A" pin="38" pad="38"/>
+<connect gate="A" pin="39" pad="39"/>
+<connect gate="A" pin="4" pad="4"/>
+<connect gate="A" pin="40" pad="40"/>
+<connect gate="A" pin="5" pad="5"/>
+<connect gate="A" pin="6" pad="6"/>
+<connect gate="A" pin="7" pad="7"/>
+<connect gate="A" pin="8" pad="8"/>
+<connect gate="A" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="M12" prefix="JP">
+<description>&lt;b&gt;Header 12&lt;/b&gt;
+Standard 12-pin 0.1" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115).</description>
+<gates>
+<gate name="G$1" symbol="M12" x="0" y="0"/>
+</gates>
+<devices>
+<device name="PTH" package="1X12">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="11" pad="11"/>
+<connect gate="G$1" pin="12" pad="12"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="1X12_NO_SILK_KIT" package="1X12_NO_SILK_KIT">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="10" pad="10"/>
+<connect gate="G$1" pin="11" pad="11"/>
+<connect gate="G$1" pin="12" pad="12"/>
+<connect gate="G$1" pin="2" pad="2"/>
+<connect gate="G$1" pin="3" pad="3"/>
+<connect gate="G$1" pin="4" pad="4"/>
+<connect gate="G$1" pin="5" pad="5"/>
+<connect gate="G$1" pin="6" pad="6"/>
+<connect gate="G$1" pin="7" pad="7"/>
+<connect gate="G$1" pin="8" pad="8"/>
+<connect gate="G$1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</drawing>
+</eagle>
\ No newline at end of file
diff --git a/SPI6502B.cel b/VHDL/SPI6502B.cel
similarity index 100%
rename from SPI6502B.cel
rename to VHDL/SPI6502B.cel
diff --git a/SPI6502B.lfp b/VHDL/SPI6502B.lfp
similarity index 100%
rename from SPI6502B.lfp
rename to VHDL/SPI6502B.lfp
diff --git a/SPI6502B.ucf b/VHDL/SPI6502B.ucf
similarity index 100%
rename from SPI6502B.ucf
rename to VHDL/SPI6502B.ucf
diff --git a/SPI6502B.ucf.untf b/VHDL/SPI6502B.ucf.untf
similarity index 100%
rename from SPI6502B.ucf.untf
rename to VHDL/SPI6502B.ucf.untf
diff --git a/SPI6502B1.1.vhd b/VHDL/SPI6502B1.1.vhd
similarity index 100%
rename from SPI6502B1.1.vhd
rename to VHDL/SPI6502B1.1.vhd
diff --git a/_pace.ucf b/VHDL/_pace.ucf
similarity index 100%
rename from _pace.ucf
rename to VHDL/_pace.ucf
diff --git a/spi65.cdf b/VHDL/spi65.cdf
similarity index 100%
rename from spi65.cdf
rename to VHDL/spi65.cdf
diff --git a/spi65.dhp b/VHDL/spi65.dhp
similarity index 100%
rename from spi65.dhp
rename to VHDL/spi65.dhp
diff --git a/spi65.npl b/VHDL/spi65.npl
similarity index 100%
rename from spi65.npl
rename to VHDL/spi65.npl
diff --git a/spi6502b._hrpt b/VHDL/spi6502b._hrpt
similarity index 100%
rename from spi6502b._hrpt
rename to VHDL/spi6502b._hrpt
diff --git a/spi6502b.gyd b/VHDL/spi6502b.gyd
similarity index 100%
rename from spi6502b.gyd
rename to VHDL/spi6502b.gyd
diff --git a/spi6502b.imp b/VHDL/spi6502b.imp
similarity index 100%
rename from spi6502b.imp
rename to VHDL/spi6502b.imp
diff --git a/spi6502b.jed b/VHDL/spi6502b.jed
similarity index 100%
rename from spi6502b.jed
rename to VHDL/spi6502b.jed
diff --git a/spi6502b.mfd b/VHDL/spi6502b.mfd
similarity index 100%
rename from spi6502b.mfd
rename to VHDL/spi6502b.mfd
diff --git a/spi6502b.pnx b/VHDL/spi6502b.pnx
similarity index 100%
rename from spi6502b.pnx
rename to VHDL/spi6502b.pnx
diff --git a/spi6502b.rpt b/VHDL/spi6502b.rpt
similarity index 100%
rename from spi6502b.rpt
rename to VHDL/spi6502b.rpt
diff --git a/spi6502b.vm6 b/VHDL/spi6502b.vm6
similarity index 100%
rename from spi6502b.vm6
rename to VHDL/spi6502b.vm6
diff --git a/spi6502b.xml b/VHDL/spi6502b.xml
similarity index 100%
rename from spi6502b.xml
rename to VHDL/spi6502b.xml
diff --git a/spi6502b_build.xml b/VHDL/spi6502b_build.xml
similarity index 100%
rename from spi6502b_build.xml
rename to VHDL/spi6502b_build.xml
diff --git a/tmperr.err b/VHDL/tmperr.err
similarity index 100%
rename from tmperr.err
rename to VHDL/tmperr.err
diff --git a/userlang.tpl b/VHDL/userlang.tpl
similarity index 100%
rename from userlang.tpl
rename to VHDL/userlang.tpl
diff --git a/_ngo/netlist.lst b/_ngo/netlist.lst
deleted file mode 100644
index 20f8fc8..0000000
--- a/_ngo/netlist.lst
+++ /dev/null
@@ -1,2 +0,0 @@
-C:\sources\AppleIISd\spi6502b.ngc 1494085672
-OK
diff --git a/spi6502b.bld b/spi6502b.bld
deleted file mode 100644
index 0c7736a..0000000
--- a/spi6502b.bld
+++ /dev/null
@@ -1,23 +0,0 @@
-Release  - ngdbuild G.38
-Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
-
-Command Line: ngdbuild -dd _ngo -uc SPI6502B.ucf -p xc9500xl spi6502b.ngc
-spi6502b.ngd 
-
-Reading NGO file "C:/sources/AppleIISd/spi6502b.ngc" ...
-Reading component libraries for design expansion...
-
-Annotating constraints to design from file "SPI6502B.ucf" ...
-
-Checking timing specifications ...
-Checking expanded design ...
-
-NGDBUILD Design Results Summary:
-  Number of errors:     0
-  Number of warnings:   0
-
-Total memory usage is 59352 kilobytes
-
-Writing NGD file "spi6502b.ngd" ...
-
-Writing NGDBUILD log file "spi6502b.bld"...
diff --git a/spi6502b.ngc b/spi6502b.ngc
deleted file mode 100644
index 6cd68ec..0000000
--- a/spi6502b.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.2e
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\ No newline at end of file
diff --git a/spi6502b.ngd b/spi6502b.ngd
deleted file mode 100644
index 075820f..0000000
--- a/spi6502b.ngd
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
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\ No newline at end of file
diff --git a/spi6502b.ngr b/spi6502b.ngr
deleted file mode 100644
index 479932a..0000000
--- a/spi6502b.ngr
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
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4112;=87c?85;28yv47=3:1>v3=2584a>;58109<85rs3ca>5<es4h:6:=4=327>=7<5;:96?om;<3ea?4fj27:jl4=ac9>5c3=:hh01<h>:3ca?87bk38jn63>e681eg=:9j314n522`4950e<,8==6?on;o341?6<uz8o<7>53z?2eg<5l916>nh514589ge=>j1/=:852e58j4122>1v?j9:18087fj38o:63=cg821c=:jj0>j6*>7781`2=i9>?1=6s|21;94?4|5;:h6?>6;<0;a?1b3ty:o94?:3y>6f`==<16nn4>6g9'520=9j<0b<9::39~w7e52908w0<<f;0`6>;5kj0?h63=cc8213=#9><1>n;4n056>6=z{;2:6=4={<01`?4?9273579j;%342?4?82d:;84?;|q14a<72;q6><>521f897>?21:0q~?l3;296~;5ko0>863mc;35a>"6??0:o;5a16797>{t:m;1<7=t=0ca>7b6348hj7?:8:?ag?0c3-;<:7<k7:l230<13ty9h54?:2y>5dd=:m201?mi:042?8dd2?;0(<99:3f4?k70=3:0q~<>1;296~;59=09=<521c09<5=z{;<:6=4:{_055>;6lj09:<521e:9637<58n?6?8>;<3`b?1a3-;<:7<92:l230<63ty:o?4?:3y>6f`==:16nn4>6e9'520=9j<0b<9::59~w4ba2909w0l>:04a?87>032;7)?86;3f4>h6?<0:7p}=7g83>7}:::81>:h4=9:93`=#9><1>5>4n056>4=z{;k36=4m{<`2>26<5;:?6:h4=321>7g?34;mi7<n8:?2bd<5i116=k;52`:894`62;k370?jc;0b<>;6m>09m5521b;9<5=::h<1=864$055>7gf3g;<97<4}r3`5?6=:r79ok4:1:?ag?71j2.:;;4>c79m523==2wx>:m50;0x97232;=h706::6g8 4112;2;7c?85;68yv4f?3:19v3l3;7b?8d62?l01<m6:6d894?c21:01?o9:074?!70>38jm6`>7480?xu5i00;6ou2b0845>;58=03<63=0381e<=:9oo1>l74=0db>7g>34;m97<n9:?2b4<5i016=hm52`;894c02;k270?l9;:2?84f>3;>m6*>7781ed=i9>?1=6s|1b294?4|5;im69h4=ca953?<,8==6<m9;o341?0<uz;oi7>52z?a5?71127:5;470:&233<6m91e=:;52:p62c=838p1?=8:35f?8>02>o0(<99:3:3?k70=380q~?l5;296~;5ko0>:63mc;344>"6??0:o;5a16795>{t9kl1<7<t=3ae>1c<5ki1=;64$055>4e13g;<9794}r04f?6=:r798l4=7c9><1<0m2.:;;4=819m523==2wx=h?50;0x9g7=9?n01<7m:928 41128o;7c?85;28yv45;3:1>v3=25820f=:j;0:;55rs0`f>5<5s4hi6<8m;<044?363-;<:7?md:l230<73ty:hi4?:3y>f4<6>116=4:5819'520=9l:0b<9::29~w71c2909w0<<f;04`>;?>3=n7)?86;0;4>h6?<087p}=b283><}::mn18:52267902=::k:18:522c7902=::>218:52265902=::<i18:5224f902=::k>1=9m4}r0a5?6=jr79hi4;5:?130<3=279n=4;5:?1f0<3=279;54;5:?132<3=279ho4;5:?1`f<3=2799n4;5:?11a<3=279n?4>4b9~yx{zHIIp5975f`;743>6uIJIw=sO@Qy~DE
\ No newline at end of file
diff --git a/spi6502b.prj b/spi6502b.prj
deleted file mode 100644
index dcf3158..0000000
--- a/spi6502b.prj
+++ /dev/null
@@ -1 +0,0 @@
-vhdl work SPI6502B1.1.vhd
diff --git a/spi6502b.syr b/spi6502b.syr
deleted file mode 100644
index 86a74ef..0000000
--- a/spi6502b.syr
+++ /dev/null
@@ -1,213 +0,0 @@
-Release 6.3.03i - xst G.38
-Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
---> Parameter TMPDIR set to __projnav
-CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
- 
---> Parameter xsthdpdir set to ./xst
-CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
- 
---> Reading design: spi6502b.prj
-
-TABLE OF CONTENTS
-  1) Synthesis Options Summary
-  2) HDL Compilation
-  3) HDL Analysis
-  4) HDL Synthesis
-  5) Advanced HDL Synthesis
-     5.1) HDL Synthesis Report
-  6) Low Level Synthesis
-  7) Final Report
-
-=========================================================================
-*                      Synthesis Options Summary                        *
-=========================================================================
----- Source Parameters
-Input File Name                    : spi6502b.prj
-Input Format                       : mixed
-Ignore Synthesis Constraint File   : NO
-Verilog Include Directory          : 
-
----- Target Parameters
-Output File Name                   : spi6502b
-Output Format                      : NGC
-Target Device                      : xc9500xl
-
----- Source Options
-Top Module Name                    : spi6502b
-Automatic FSM Extraction           : YES
-FSM Encoding Algorithm             : Auto
-Mux Extraction                     : YES
-Resource Sharing                   : YES
-
----- Target Options
-Add IO Buffers                     : YES
-Equivalent register Removal        : YES
-MACRO Preserve                     : YES
-XOR Preserve                       : YES
-
----- General Options
-Optimization Goal                  : Speed
-Optimization Effort                : 1
-Keep Hierarchy                     : YES
-RTL Output                         : Yes
-Hierarchy Separator                : _
-Bus Delimiter                      : <>
-Case Specifier                     : maintain
-
----- Other Options
-lso                                : spi6502b.lso
-verilog2001                        : YES
-Clock Enable                       : YES
-wysiwyg                            : NO
-
-=========================================================================
-
-
-=========================================================================
-*                          HDL Compilation                              *
-=========================================================================
-Compiling vhdl file C:/sources/AppleIISd/SPI6502B1.1.vhd in Library work.
-Entity <spi6502b> (Architecture <behavioral>) compiled.
-
-=========================================================================
-*                            HDL Analysis                               *
-=========================================================================
-Analyzing Entity <spi6502b> (Architecture <behavioral>).
-INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 203: Mux is complete : default of case is discarded
-INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 316: Mux is complete : default of case is discarded
-Entity <spi6502b> analyzed. Unit <spi6502b> generated.
-
-
-=========================================================================
-*                           HDL Synthesis                               *
-=========================================================================
-
-Synthesizing Unit <spi6502b>.
-    Related source file is C:/sources/AppleIISd/SPI6502B1.1.vhd.
-    Found 8-bit tristate buffer for signal <cpu_d>.
-    Found 1-bit tristate buffer for signal <cpu_Nirq>.
-    Found 1-bit tristate buffer for signal <spi_mosi>.
-    Found 1-bit xor3 for signal <$n0040> created at line 206.
-    Found 4-bit adder for signal <$n0047> created at line 160.
-    Found 1-bit register for signal <cpha>.
-    Found 1-bit register for signal <cpol>.
-    Found 3-bit down counter for signal <divcnt>.
-    Found 3-bit register for signal <divisor>.
-    Found 1-bit register for signal <ece>.
-    Found 1-bit register for signal <frx>.
-    Found 1-bit register for signal <ier>.
-    Found 1-bit register for signal <int_mosi>.
-    Found 1-bit register for signal <int_sclk>.
-    Found 4-bit register for signal <shiftcnt>.
-    Found 1-bit register for signal <shiftdone>.
-    Found 1-bit register for signal <shifting2>.
-    Found 1-bit register for signal <slaveinten>.
-    Found 1-bit register for signal <slavesel>.
-    Found 8-bit register for signal <spidatain>.
-    Found 8-bit register for signal <spidataout>.
-    Found 1-bit register for signal <start_shifting>.
-    Found 1-bit register for signal <tc>.
-    Found 1-bit register for signal <tmo>.
-    Found 24 1-bit 2-to-1 multiplexers.
-    Summary:
-	inferred   1 Counter(s).
-	inferred  20 D-type flip-flop(s).
-	inferred   1 Adder/Subtracter(s).
-	inferred  10 Tristate(s).
-Unit <spi6502b> synthesized.
-
-
-=========================================================================
-*                       Advanced HDL Synthesis                          *
-=========================================================================
-
-Advanced RAM inference ...
-Advanced multiplier inference ...
-Advanced Registered AddSub inference ...
-Dynamic shift register inference ...
-
-=========================================================================
-HDL Synthesis Report
-
-Macro Statistics
-# Adders/Subtractors               : 1
- 4-bit adder                       : 1
-# Registers                        : 25
- 1-bit register                    : 22
- 8-bit register                    : 1
- 3-bit register                    : 1
- 4-bit register                    : 1
-# Multiplexers                     : 12
- 2-to-1 multiplexer                : 12
-# Tristates                        : 3
- 1-bit tristate buffer             : 2
- 8-bit tristate buffer             : 1
-# Xors                             : 1
- 1-bit xor3                        : 1
-
-=========================================================================
-
-=========================================================================
-*                         Low Level Synthesis                           *
-=========================================================================
-
-Optimizing unit <spi6502b> ...
-
-=========================================================================
-*                            Final Report                               *
-=========================================================================
-Final Results
-RTL Top Level Output File Name     : spi6502b.ngr
-Top Level Output File Name         : spi6502b
-Output Format                      : NGC
-Optimization Goal                  : Speed
-Keep Hierarchy                     : YES
-Target Technology                  : xc9500xl
-Macro Preserve                     : YES
-XOR Preserve                       : YES
-Clock Enable                       : YES
-wysiwyg                            : NO
-
-Design Statistics
-# IOs                              : 23
-
-Macro Statistics :
-# Registers                        : 60
-#      1-bit register              : 60
-# Tristates                        : 3
-#      1-bit tristate buffer       : 2
-#      8-bit tristate buffer       : 1
-# Xors                             : 5
-#      1-bit xor2                  : 5
-
-Cell Usage :
-# BELS                             : 252
-#      AND2                        : 119
-#      AND3                        : 5
-#      AND4                        : 1
-#      GND                         : 1
-#      INV                         : 77
-#      OR2                         : 42
-#      OR3                         : 1
-#      VCC                         : 1
-#      XOR2                        : 5
-# FlipFlops/Latches                : 37
-#      FD                          : 1
-#      FDC                         : 5
-#      FDCE                        : 27
-#      FDCP                        : 1
-#      FDP                         : 1
-#      FDPE                        : 2
-# IO Buffers                       : 23
-#      IBUF                        : 10
-#      IOBUFE                      : 8
-#      OBUF                        : 3
-#      OBUFE                       : 2
-=========================================================================
-CPU : 0.65 / 1.07 s | Elapsed : 0.00 / 1.00 s
- 
---> 
-
-Total memory usage is 68376 kilobytes
-
-
diff --git a/spi6502b_pad.csv b/spi6502b_pad.csv
deleted file mode 100644
index 84e7d04..0000000
--- a/spi6502b_pad.csv
+++ /dev/null
@@ -1,73 +0,0 @@
-Release 6.1i - Fit G.38
-Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
-
- 5- 6-2017  5:47PM
-
-NOTE: This file is designed to be imported into a spreadsheet program
-such as Microsoft Excel for viewing, printing and sorting. The comma ','
-character is used as the data field separator.
-This file is also designed to support parsing.
-
-Input file:  spi6502b.ngd
-output file: spi6502b_pad.csv
-Part type:   xc9572xl
-Speed grade: -10
-Package:     pc44
-
-Pinout by Pin Number:
-
------,-----,-----,-----,-----,-----,-----,-----,-----,-----,
-Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,{blank},Slew Rate,Termination,{blank},Voltage,Constraint,
-P1,TIE,,I/O,,,,,,,,,,
-P2,cpu_d<0>,I/O,I/O,BIDIR,,,,,,,,,
-P3,cpu_d<1>,I/O,I/O,BIDIR,,,,,,,,,
-P4,cpu_d<2>,I/O,I/O,BIDIR,,,,,,,,,
-P5,cpu_Nphi2,I,I/O/GCK1,INPUT,,,,,,,,,
-P6,extclk,I,I/O/GCK2,INPUT,,,,,,,,,
-P7,cpu_rnw,I,I/O/GCK3,INPUT,,,,,,,,,
-P8,cpu_d<3>,I/O,I/O,BIDIR,,,,,,,,,
-P9,cpu_d<4>,I/O,I/O,BIDIR,,,,,,,,,
-P10,GND,,GND,,,,,,,,,,
-P11,cpu_d<5>,I/O,I/O,BIDIR,,,,,,,,,
-P12,cpu_d<6>,I/O,I/O,BIDIR,,,,,,,,,
-P13,cpu_d<7>,I/O,I/O,BIDIR,,,,,,,,,
-P14,cpu_Nirq,O,I/O,OUTPUT,,,,,,,,,
-P15,TDI,,TDI,,,,,,,,,,
-P16,TMS,,TMS,,,,,,,,,,
-P17,TCK,,TCK,,,,,,,,,,
-P18,Ncs2,I,I/O,INPUT,,,,,,,,,
-P19,cpu_Nres,I,I/O,INPUT,,,,,,,,,
-P20,cs1,I,I/O,INPUT,,,,,,,,,
-P21,VCC,,VCCINT,,,,,,,,,,
-P22,cpu_a<0>,I,I/O,INPUT,,,,,,,,,
-P23,GND,,GND,,,,,,,,,,
-P24,cpu_a<1>,I,I/O,INPUT,,,,,,,,,
-P25,TIE,,I/O,,,,,,,,,,
-P26,TIE,,I/O,,,,,,,,,,
-P27,TIE,,I/O,,,,,,,,,,
-P28,spi_Nsel,O,I/O,OUTPUT,,,,,,,,,
-P29,led,O,I/O,OUTPUT,,,,,,,,,
-P30,TDO,,TDO,,,,,,,,,,
-P31,GND,,GND,,,,,,,,,,
-P32,VCC,,VCCIO,,,,,,,,,,
-P33,TIE,,I/O,,,,,,,,,,
-P34,spi_sclk,O,I/O,OUTPUT,,,,,,,,,
-P35,spi_mosi,O,I/O,OUTPUT,,,,,,,,,
-P36,TIE,,I/O,,,,,,,,,,
-P37,TIE,,I/O,,,,,,,,,,
-P38,TIE,,I/O,,,,,,,,,,
-P39,TIE,,I/O/GSR,,,,,,,,,,
-P40,TIE,,I/O/GTS2,,,,,,,,,,
-P41,VCC,,VCCINT,,,,,,,,,,
-P42,spi_int,I,I/O/GTS1,INPUT,,,,,,,,,
-P43,TIE,,I/O,,,,,,,,,,
-P44,spi_miso,I,I/O,INPUT,,,,,,,,,
-
-To preserve the pinout above for future design iterations in
-Project Navigator simply execute the (Lock Pins) process
-located under the (Implement Design) process in a toolbox named
-(Optional Implementation Tools) or invoke PIN2UCF from the
-command line. The location constraints will be written into your
-specified UCF file
-
-