Apple-2-HW/AppleIISd
1
0
Fork 1
mirror of https://github.com/freitz85/AppleIISd.git synced 2024-06-09 22:29:43 +00:00
Code Issues Projects Releases Wiki Activity

SDHC flag added to CPLD

Browse Source
This commit is contained in:
freitz85 2017-11-25 19:42:33 +01:00
parent 6517f86ce3
commit 505fe10434
2 changed files with 418 additions and 412 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

816
VHDL/AppleIISd.jed
View File

File diff suppressed because it is too large Load Diff

14
VHDL/SpiController.vhd
View File

@ -38,6 +38,7 @@ architecture Behavioral of SpiController is
-- internal state -- internal state
signal spidatain: std_logic_vector (7 downto 0); signal spidatain: std_logic_vector (7 downto 0);
signal spidataout: std_logic_vector (7 downto 0); signal spidataout: std_logic_vector (7 downto 0);
signal sdhc: std_logic; -- is SDHC card
signal inited: std_logic; -- card initialized signal inited: std_logic; -- card initialized
-- spi register flags -- spi register flags
@ -207,7 +208,7 @@ begin
-- cpu register section -- cpu register section
-- cpu read -- cpu read
cpu_read: process(addr, spidatain, tc, bsy, frx, cpu_read: process(addr, spidatain, tc, bsy, frx,
ece, divisor, slavesel, wp, card, inited) ece, divisor, slavesel, wp, card, sdhc, inited)
begin begin
case addr is case addr is
when "00" => -- read SPI data in when "00" => -- read SPI data in
@ -226,7 +227,8 @@ begin
data_out(7 downto 3) <= (others => '0'); data_out(7 downto 3) <= (others => '0');
when "11" => -- read slave select / slave interrupt state when "11" => -- read slave select / slave interrupt state
data_out(0) <= slavesel; data_out(0) <= slavesel;
data_out(4 downto 1) <= (others => '0'); data_out(3 downto 1) <= (others => '0');
data_out(4) <= sdhc;
data_out(5) <= wp; data_out(5) <= wp;
data_out(6) <= card; data_out(6) <= card;
data_out(7) <= inited; data_out(7) <= inited;
@ -236,7 +238,7 @@ begin
end process; end process;
-- cpu write -- cpu write
cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card, inited) cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card)
begin begin
if (nreset = '0') then if (nreset = '0') then
ece <= '0'; ece <= '0';
@ -244,8 +246,10 @@ begin
slavesel <= '1'; slavesel <= '1';
divisor <= (others => '0'); divisor <= (others => '0');
spidataout <= (others => '1'); spidataout <= (others => '1');
sdhc <= '0';
inited <= '0'; inited <= '0';
elsif (card = '1') then elsif (card = '1') then
sdhc <= '0';
inited <= '0'; inited <= '0';
elsif (rising_edge(ndev_sel) and is_read = '0') then elsif (rising_edge(ndev_sel) and is_read = '0') then
case addr is case addr is
@ -259,7 +263,9 @@ begin
divisor <= data_in(DIV_WIDTH-1 downto 0); divisor <= data_in(DIV_WIDTH-1 downto 0);
when "11" => -- write slave select / slave interrupt enable when "11" => -- write slave select / slave interrupt enable
slavesel <= data_in(0); slavesel <= data_in(0);
-- no bit 1 - 6 -- no bit 1 - 3
sdhc <= data_in(4);
-- no bit 5 - 6
inited <= data_in(7); inited <= data_in(7);
when others => when others =>
end case; end case;