Apple-2-HW
/
AppleIISd
mirror of https://github.com/freitz85/AppleIISd.git
1
0
Fork 1
Code Issues Projects Releases Wiki Activity

Added waiting for card ready.

This commit is contained in:
vladimir 2018-10-09 22:44:29 -05:00
parent b9db1b5756
commit 6e030bf3e5
6 changed files with 97 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

BIN
AppleIISd.bin
View File

Binary file not shown.

0
Images/Bus1.gif Executable file → Normal file
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 13 KiB

After

Width:  |  Height:  |  Size: 13 KiB

0
Images/Bus2.gif Executable file → Normal file
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 12 KiB

After

Width:  |  Height:  |  Size: 12 KiB

26
src/AppleIISd.s
View File

@ -13,9 +13,11 @@
.import PRODOS
.import SMARTPORT
.import WRDATA
.import GETR1
.import GETR3
.import SDCMD
.import SDCMD0
.import CARDDET
.import READ
@ -238,9 +240,7 @@ INIT: LDA #$03 ; set SPI mode 3
LDY #10
LDA #DUMMY
@LOOP: STA DATA,X
@WAIT: BIT CTRL,X
BPL @WAIT
@LOOP: JSR WRDATA
DEY
BNE @LOOP ; do 10 times
LDA SS,X
@ -251,7 +251,7 @@ INIT: LDA #$03 ; set SPI mode 3
STA CMDLO
LDA #>CMD0
STA CMDHI
JSR SDCMD
JSR SDCMD0
JSR GETR1 ; get response
CMP #$01
BNE @ERROR1 ; error!
@ -261,6 +261,7 @@ INIT: LDA #$03 ; set SPI mode 3
LDA #>CMD8
STA CMDHI
JSR SDCMD
BCS @ERROR1
JSR GETR3 ; R7 is also 1+4 bytes
CMP #$01
BNE @SDV1 ; may be SD Ver. 1
@ -275,12 +276,14 @@ INIT: LDA #$03 ; set SPI mode 3
LDA #>CMD55
STA CMDHI
JSR SDCMD
BCS @ERROR1
JSR GETR1
LDA #<ACMD4140 ; enable SDHC support
STA CMDLO
LDA #>ACMD4140
STA CMDHI
JSR SDCMD
BCS @ERROR1
JSR GETR1
CMP #$01
BEQ @SDV2 ; wait for ready
@ -292,7 +295,8 @@ INIT: LDA #$03 ; set SPI mode 3
STA CMDLO
LDA #>CMD58
STA CMDHI
JSR SDCMD
JSR SDCMD
BCS @ERROR1
JSR GETR3
CMP #0
BNE @ERROR1 ; error!
@ -313,11 +317,13 @@ INIT: LDA #$03 ; set SPI mode 3
LDA #>CMD55
STA CMDHI
JSR SDCMD ; ignore response
BCS @ERROR1
LDA #<ACMD410
STA CMDLO
LDA #>ACMD410
STA CMDHI
JSR SDCMD
BCS @ERROR1
JSR GETR1
CMP #$01
BEQ @SDV1 ; wait for ready
@ -331,6 +337,7 @@ INIT: LDA #$03 ; set SPI mode 3
LDA #>CMD1
STA CMDHI
@LOOP1: JSR SDCMD
BCS @IOERROR
JSR GETR1
CMP #$01
BEQ @LOOP1 ; wait for ready
@ -343,6 +350,7 @@ INIT: LDA #$03 ; set SPI mode 3
LDA #>CMD16
STA CMDHI
JSR SDCMD
BCS @IOERROR
JSR GETR1
CMP #0
BNE @IOERROR ; error!
@ -350,9 +358,9 @@ INIT: LDA #$03 ; set SPI mode 3
@END: LDA SS,X
ORA #INITED ; initialized
STA SS,X
LDA CTRL,X
ORA #ECE ; enable 7MHz
STA CTRL,X
;LDA CTRL,X
;ORA #ECE ; enable 7MHz
;STA CTRL,X
CLC ; all ok
LDY #NO_ERR
BCC @END1
@ -368,7 +376,7 @@ INIT: LDA #$03 ; set SPI mode 3
RTS
TEXT: .asciiz " Apple][Sd v1.2.1 (c)2018 Florian Reitz "
TEXT: .asciiz " Apple][Sd v1.2.2 (c)2018 Florian Reitz "
CMD0: .byt $40, $00, $00
.byt $00, $00, $95

92
src/Helper.s
View File

@ -11,8 +11,10 @@
;
;*******************************
.export WRDATA
.export COMMAND
.export SDCMD
.export SDCMD0
.export GETBLOCK
.export CARDDET
.export WRPROT
@ -22,24 +24,56 @@
.include "AppleIISd.inc"
.segment "EXTROM"
WRDATA: STA DATA,X
@WAIT: BIT CTRL,X
BPL @WAIT
RTS
;********************************
; Wait for card ready
; C set on timeout
;********************************
WREADY:
PHA
LDA #$FE
@LOOP: PHA ; counter
LDA #DUMMY
JSR WRDATA
LDA DATA,X
CMP #$FF
BNE @AGAIN
PLA
PLA
CLC
RTS
@AGAIN: PLA
CMP #$FF
BEQ @TOUT
SBC #0 ; dec a
JMP @LOOP
@TOUT: PLA
SEC
RTS
;*******************************
;
; Send SD command
; Call with command in CMDHI and CMDLO
; Returns iwth carry set on timeout
;
;*******************************
SDCMD: PHY
SDCMD: JSR WREADY
BCC SDCMD0
RTS
SDCMD0: PHY
LDY #0
@LOOP: LDA (CMDLO),Y
STA DATA,X
@WAIT: BIT CTRL,X ; TC is in N
BPL @WAIT
JSR WRDATA
INY
CPY #6
BCC @LOOP
PLY
CLC
RTS
@ -50,16 +84,22 @@ SDCMD: PHY
;
;*******************************
GETR1: LDA #DUMMY
STA DATA,X
@WAIT: BIT CTRL,X
BPL @WAIT
GETR1: PHY
LDY #10
@AGAIN: LDA #DUMMY
JSR WRDATA
LDA DATA,X ; get response
BMI GETR1 ; wait for MSB=0
PHA
BIT #$80
BEQ @CONT ; wait for MSB=0
DEY
BNE @AGAIN
PLY
RTS
@CONT: PHA
LDA #DUMMY
STA DATA,X ; send another dummy
JSR WRDATA ; send another dummy
PLA ; restore R1
PLY
RTS
;*******************************
@ -74,12 +114,10 @@ GETR3: JSR GETR1 ; get R1 first
PHA ; save R1
PHY ; save Y
LDY #04 ; load counter
JMP @WAIT ; first byte is already there
JMP @LOAD ; first byte is already there
@LOOP: LDA #DUMMY ; send dummy
STA DATA,X
@WAIT: BIT CTRL,X
BPL @WAIT
LDA DATA,X
JSR WRDATA
@LOAD: LDA DATA,X
PHA
DEY
BNE @LOOP ; do 4 times
@ -94,7 +132,7 @@ GETR3: JSR GETR1 ; get R1 first
STA R30,Y ; R30 is MSB
PLY ; restore Y
LDA #DUMMY
STA DATA,X ; send another dummy
JSR WRDATA ; send another dummy
PLA ; restore R1
RTS
@ -156,19 +194,23 @@ GETBLOCK: PHX ; save X
;
;*******************************
COMMAND: PHY ; save Y
COMMAND:
JSR WREADY
BCC @CONT
RTS
@CONT: PHY ; save Y
LDY SLOT
STA DATA,X ; send command
JSR WRDATA ; send command
LDA R30,Y ; get arg from R30 on
STA DATA,X
JSR WRDATA
LDA R31,Y
STA DATA,X
JSR WRDATA
LDA R32,Y
STA DATA,X
JSR WRDATA
LDA R33,Y
STA DATA,X
JSR WRDATA
LDA #DUMMY
STA DATA,X ; dummy crc
JSR WRDATA ; dummy crc
JSR GETR1
PLY ; restore Y
RTS

25
src/ProDOS.s
View File

@ -16,6 +16,7 @@
.export READ
.export WRITE
.import WRDATA
.import COMMAND
.import SDCMD
.import GETBLOCK
@ -108,16 +109,16 @@ READ: JSR GETBLOCK ; calc block address
BNE @ERROR ; check for error
@GETTOK: LDA #DUMMY ; get data token
STA DATA,X
JSR WRDATA
LDA DATA,X ; get response
CMP #$FE
BNE @GETTOK ; wait for $FE
LDA CTRL,X ; enable FRX
ORA #FRX
ORA #FRX+ECE
STA CTRL,X
LDA #DUMMY
STA DATA,X
JSR WRDATA
LDY #0
@LOOP1: LDA DATA,X ; read data from card
@ -136,7 +137,7 @@ READ: JSR GETBLOCK ; calc block address
LDA DATA,X ; read a dummy byte
LDA CTRL,X ; disable FRX
AND #<~FRX
AND #<~(FRX+ECE)
STA CTRL,X
CLC ; no error
LDA #NO_ERR
@ -184,27 +185,27 @@ WRITE: JSR WRPROT
BNE @IOERROR ; check for error
LDA #DUMMY
STA DATA,X ; send dummy
JSR WRDATA ; send dummy
LDA #$FE
STA DATA,X ; send data token
JSR WRDATA ; send data token
LDY #0
@LOOP1: LDA (BUFFER),Y
STA DATA,X
JSR WRDATA
INY
BNE @LOOP1
INC BUFFER+1
@LOOP2: LDA (BUFFER),Y
STA DATA,X
JSR WRDATA
INY
BNE @LOOP2
DEC BUFFER+1
@CRC: LDA #DUMMY
STA DATA,X ; send 2 dummy crc bytes
STA DATA,X
JSR WRDATA ; send 2 dummy crc bytes
JSR WRDATA
STA DATA,X ; get data response
JSR WRDATA ; get data response
LDA DATA,X
AND #$1F
CMP #$05
@ -215,7 +216,7 @@ WRITE: JSR WRPROT
@DONE: PHP
PHA
@WAIT: LDA #DUMMY
STA DATA,X ; wait for write cycle
JSR WRDATA ; wait for write cycle
LDA DATA,X ; to complete
BEQ @WAIT