diff --git a/VHDL/AddressDecoder_Test.vhd b/VHDL/AddressDecoder_Test.vhd
index d2033e9..5cbc589 100644
--- a/VHDL/AddressDecoder_Test.vhd
+++ b/VHDL/AddressDecoder_Test.vhd
@@ -68,7 +68,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
    signal CLK : std_logic := '0';
    signal PHI0 : std_logic := '1';
 
- 	--Outputs
+    --Outputs
    signal B : std_logic_vector(10 downto 8);
    signal DATA_EN : std_logic;
    signal NG : std_logic;
@@ -80,7 +80,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
  
 BEGIN
  
-	-- Instantiate the Unit Under Test (UUT)
+   -- Instantiate the Unit Under Test (UUT)
    uut: AddressDecoder PORT MAP (
           A => A,
           B => B,
@@ -100,10 +100,10 @@ BEGIN
    -- Clock process definitions
    CLK_process :process
    begin
-		CLK <= '0';
-		wait for CLK_period/2;
-		CLK <= '1';
-		wait for CLK_period/2;
+      CLK <= '0';
+      wait for CLK_period/2;
+      CLK <= '1';
+      wait for CLK_period/2;
    end process;
  
    PHI0_process :process(CLK)
@@ -120,7 +120,7 @@ BEGIN
 
    -- Stimulus process
    stim_proc: process
-   begin		
+   begin      
       -- hold reset state.
       wait for CLK_period * 10;
       NRESET <= '0';
@@ -128,8 +128,10 @@ BEGIN
       NRESET <= '1';
       wait for CLK_period * 10;
 
-      -- insert stimulus here 
       -- C0nX access
+      -- NG must be '0"
+      -- NOE must be '1'
+      -- NWE must be '1'
       A <= "0000";  -- must become "000"
       wait until rising_edge(PHI0);
       NDEV_SEL <= '0';
@@ -137,7 +139,10 @@ BEGIN
       NDEV_SEL <= '1';
       wait until rising_edge(PHI0);
       
-      -- CnXX access
+      -- CnXX access, select
+      -- NG must be '0'
+      -- NOE must be '0'
+      -- NWE must be '1'
       A <= "0100";  -- must become "000"     
       wait until rising_edge(PHI0);
       NIO_SEL <= '0';
@@ -146,14 +151,20 @@ BEGIN
       wait until rising_edge(PHI0);
       
       -- C8xx access, selected
+      -- NG must be '0'
+      -- NOE must be '0'
+      -- NWE must be '1'
       A <= "1000";  -- must become "001"      
       wait until rising_edge(PHI0);
       NIO_STB <= '0';
       wait until falling_edge(PHI0);
       NIO_STB <= '1';
       wait until rising_edge(PHI0);
-
-      -- C8xx write access, selected
+      
+      -- C8xx write access, selected
+      -- NG must be '0'
+      -- NOE must be '1'
+      -- NWE must be '0'
       RNW <= '0';
       wait until rising_edge(PHI0);
       NIO_STB <= '0';
@@ -162,6 +173,9 @@ BEGIN
       wait until rising_edge(PHI0);
       
       -- C9xx access, selected
+      -- NG must be '0'
+      -- NOE must be '0'
+      -- NWE must be '1'
       RNW <= '1';
       A <= "1001";  -- must become "010"      
       wait until rising_edge(PHI0);
@@ -169,8 +183,11 @@ BEGIN
       wait until falling_edge(PHI0);
       NIO_STB <= '1';
       wait until rising_edge(PHI0);
-
-      -- C9xx access write, selected
+      
+      -- C9xx access write, selected
+      -- NG must be '0'
+      -- NOE must be '1'
+      -- NWE must be '0'
       RNW <= '0';     
       wait until rising_edge(PHI0);
       NIO_STB <= '0';
@@ -179,6 +196,9 @@ BEGIN
       wait until rising_edge(PHI0);
       
       -- CPLD access
+      -- NG must be '0'
+      -- NOE must be '1'
+      -- NWE must be '1'
       RNW <= '1';
       A <= "0101";  -- must become "000"      
       wait until rising_edge(PHI0);
@@ -188,6 +208,9 @@ BEGIN
       wait until rising_edge(PHI0);
       
       -- CFFF access
+      -- NG must be '1'
+      -- NOE must be '1'
+      -- NWE must be '1'
       A <= "1111";  -- must become "111"      
       wait until rising_edge(PHI0);
       NIO_STB <= '0';
@@ -196,6 +219,9 @@ BEGIN
       wait until rising_edge(PHI0);
       
       -- C8xx access, unselected
+      -- NG must be '1'
+      -- NOE must be '1'
+      -- NWE must be '1'
       A <= "1000"; -- must become "001"      
       wait until rising_edge(PHI0);
       NIO_STB <= '0';
diff --git a/VHDL/AppleIISd.xise b/VHDL/AppleIISd.xise
index 445b320..1bb074a 100644
--- a/VHDL/AppleIISd.xise
+++ b/VHDL/AppleIISd.xise
@@ -16,35 +16,28 @@
 
   <files>
     <file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
     </file>
     <file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
     </file>
-    <file xil_pn:name="AddressDecoder_old.sch" xil_pn:type="FILE_SCHEMATIC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="AddressDecoder_old_Test.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="52"/>
-    </file>
   </files>
 
   <properties>
@@ -159,8 +152,8 @@
     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -170,7 +163,7 @@
     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -205,7 +198,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>