From 70def47cf2faa3a0fb90d02a8e38e6aee79e93b9 Mon Sep 17 00:00:00 2001 From: freitz85 Date: Sun, 15 Oct 2017 20:58:33 +0200 Subject: [PATCH] More VDHL tests added --- VHDL/AppleIISd.jed | 2 +- VHDL/AppleIISd.vhd | 4 ++- VHDL/AppleIISd_Test.vhd | 61 ++++++++++++++++++++++++++++++++++++++--- 3 files changed, 61 insertions(+), 6 deletions(-) diff --git a/VHDL/AppleIISd.jed b/VHDL/AppleIISd.jed index fb5987a..9fbfc57 100644 --- a/VHDL/AppleIISd.jed +++ b/VHDL/AppleIISd.jed @@ -1,5 +1,5 @@ Programmer Jedec Bit Map -Date Extracted: Fri Oct 13 23:00:44 2017 +Date Extracted: Sun Oct 15 20:52:38 2017 QF46656* QP44* diff --git a/VHDL/AppleIISd.vhd b/VHDL/AppleIISd.vhd index 9c4b7e8..e422c38 100644 --- a/VHDL/AppleIISd.vhd +++ b/VHDL/AppleIISd.vhd @@ -55,7 +55,8 @@ Port ( -- synthesis translate_off ; data_dbg : out std_logic_vector (7 downto 0); - add_dbg : out std_logic_vector (1 downto 0) + add_dbg : out std_logic_vector (1 downto 0); + data_en_dbg : out std_logic -- synthesis translate_on ); @@ -161,6 +162,7 @@ begin -- synthesis translate_off data_dbg <= data_in; add_dbg <= addr_low_int; + data_en_dbg <= data_en; -- synthesis translate_on data_latch: process(CLK) diff --git a/VHDL/AppleIISd_Test.vhd b/VHDL/AppleIISd_Test.vhd index 7b8f722..07b2303 100644 --- a/VHDL/AppleIISd_Test.vhd +++ b/VHDL/AppleIISd_Test.vhd @@ -63,7 +63,8 @@ ARCHITECTURE behavior OF AppleIISd_Test IS WP : IN std_logic; data_dbg : out std_logic_vector (7 downto 0); - add_dbg : out std_logic_vector (1 downto 0) + add_dbg : out std_logic_vector (1 downto 0); + data_en_dbg : out std_logic ); END COMPONENT; @@ -96,6 +97,7 @@ ARCHITECTURE behavior OF AppleIISd_Test IS signal data_dbg : std_logic_vector (7 downto 0); signal add_dbg : std_logic_vector (1 downto 0); + signal data_en_dbg : std_logic; -- Clock period definitions constant CLK_period : time := 142 ns; @@ -136,7 +138,8 @@ BEGIN WP => WP, data_dbg => data_dbg, - add_dbg => add_dbg + add_dbg => add_dbg, + data_en_dbg => data_en_dbg ); -- Clock process definitions @@ -197,7 +200,7 @@ BEGIN NDEV_SEL <= '0'; DATA <= (others => 'Z'); wait for DATA_valid; - DATA <= (others => '0'); + DATA <= X"AA"; wait until falling_edge(PHI0); NDEV_SEL <= '1'; wait for ADD_hold; @@ -236,7 +239,7 @@ BEGIN NDEV_SEL <= '0'; DATA <= (others => 'Z'); wait for DATA_valid; - DATA <= (others => '0'); + DATA <= X"AA"; wait until falling_edge(PHI0); NDEV_SEL <= '1'; wait for ADD_hold; @@ -245,6 +248,56 @@ BEGIN RNW <= '1'; DATA <= (others => 'Z'); + -- read eprom low + wait for 3 us; + wait until falling_edge(PHI0); + wait for ADD_valid; + ADD_LOW <= (others => '0'); + ADD_HIGH <= (others => '0'); + RNW <= '1'; + DATA <= (others => 'U'); + wait until rising_edge(PHI0); + NIO_SEL <= '0'; + DATA <= (others => 'Z'); + wait until falling_edge(PHI0); + NIO_SEL <= '1'; + wait for ADD_hold; + ADD_LOW <= (others => 'U'); + ADD_HIGH <= (others => 'U'); + + -- read $CFFF + wait until falling_edge(PHI0); + wait for ADD_valid; + ADD_LOW <= (others => '1'); + ADD_HIGH <= (others => '1'); + RNW <= '1'; + DATA <= (others => 'U'); + wait until rising_edge(PHI0); + NIO_STB <= '0'; + DATA <= (others => 'Z'); + wait until falling_edge(PHI0); + NIO_STB <= '1'; + wait for ADD_hold; + ADD_LOW <= (others => 'U'); + ADD_HIGH <= (others => 'U'); + + -- read eprom high + wait until falling_edge(PHI0); + wait for ADD_valid; + ADD_LOW <= (others => '0'); + ADD_HIGH <= "101"; + RNW <= '1'; + DATA <= (others => 'U'); + wait until rising_edge(PHI0); + NIO_SEL <= '0'; + DATA <= (others => 'Z'); + wait until falling_edge(PHI0); + NIO_SEL <= '1'; + wait for ADD_hold; + ADD_LOW <= (others => 'U'); + ADD_HIGH <= (others => 'U'); + + wait; end process;