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More VDHL tests added
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@ -1,5 +1,5 @@
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Programmer Jedec Bit Map
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Programmer Jedec Bit Map
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Date Extracted: Fri Oct 13 23:00:44 2017
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Date Extracted: Sun Oct 15 20:52:38 2017
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QF46656*
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QF46656*
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QP44*
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QP44*
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@ -55,7 +55,8 @@ Port (
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-- synthesis translate_off
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-- synthesis translate_off
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;
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;
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data_dbg : out std_logic_vector (7 downto 0);
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data_dbg : out std_logic_vector (7 downto 0);
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add_dbg : out std_logic_vector (1 downto 0)
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add_dbg : out std_logic_vector (1 downto 0);
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data_en_dbg : out std_logic
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-- synthesis translate_on
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-- synthesis translate_on
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);
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);
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@ -161,6 +162,7 @@ begin
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-- synthesis translate_off
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-- synthesis translate_off
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data_dbg <= data_in;
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data_dbg <= data_in;
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add_dbg <= addr_low_int;
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add_dbg <= addr_low_int;
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data_en_dbg <= data_en;
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-- synthesis translate_on
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-- synthesis translate_on
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data_latch: process(CLK)
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data_latch: process(CLK)
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@ -63,7 +63,8 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
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WP : IN std_logic;
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WP : IN std_logic;
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data_dbg : out std_logic_vector (7 downto 0);
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data_dbg : out std_logic_vector (7 downto 0);
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add_dbg : out std_logic_vector (1 downto 0)
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add_dbg : out std_logic_vector (1 downto 0);
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data_en_dbg : out std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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@ -96,6 +97,7 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
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signal data_dbg : std_logic_vector (7 downto 0);
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signal data_dbg : std_logic_vector (7 downto 0);
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signal add_dbg : std_logic_vector (1 downto 0);
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signal add_dbg : std_logic_vector (1 downto 0);
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signal data_en_dbg : std_logic;
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-- Clock period definitions
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-- Clock period definitions
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constant CLK_period : time := 142 ns;
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constant CLK_period : time := 142 ns;
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@ -136,7 +138,8 @@ BEGIN
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WP => WP,
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WP => WP,
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data_dbg => data_dbg,
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data_dbg => data_dbg,
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add_dbg => add_dbg
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add_dbg => add_dbg,
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data_en_dbg => data_en_dbg
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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@ -197,7 +200,7 @@ BEGIN
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NDEV_SEL <= '0';
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NDEV_SEL <= '0';
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DATA <= (others => 'Z');
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DATA <= (others => 'Z');
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wait for DATA_valid;
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wait for DATA_valid;
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DATA <= (others => '0');
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DATA <= X"AA";
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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NDEV_SEL <= '1';
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wait for ADD_hold;
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wait for ADD_hold;
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@ -236,7 +239,7 @@ BEGIN
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NDEV_SEL <= '0';
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NDEV_SEL <= '0';
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DATA <= (others => 'Z');
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DATA <= (others => 'Z');
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wait for DATA_valid;
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wait for DATA_valid;
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DATA <= (others => '0');
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DATA <= X"AA";
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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NDEV_SEL <= '1';
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wait for ADD_hold;
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wait for ADD_hold;
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@ -245,6 +248,56 @@ BEGIN
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RNW <= '1';
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RNW <= '1';
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DATA <= (others => 'Z');
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DATA <= (others => 'Z');
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-- read eprom low
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wait for 3 us;
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '0');
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ADD_HIGH <= (others => '0');
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RNW <= '1';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NIO_SEL <= '0';
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DATA <= (others => 'Z');
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wait until falling_edge(PHI0);
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NIO_SEL <= '1';
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wait for ADD_hold;
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ADD_LOW <= (others => 'U');
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ADD_HIGH <= (others => 'U');
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-- read $CFFF
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '1');
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ADD_HIGH <= (others => '1');
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RNW <= '1';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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DATA <= (others => 'Z');
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait for ADD_hold;
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ADD_LOW <= (others => 'U');
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ADD_HIGH <= (others => 'U');
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-- read eprom high
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '0');
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ADD_HIGH <= "101";
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RNW <= '1';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NIO_SEL <= '0';
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DATA <= (others => 'Z');
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wait until falling_edge(PHI0);
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NIO_SEL <= '1';
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wait for ADD_hold;
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ADD_LOW <= (others => 'U');
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ADD_HIGH <= (others => 'U');
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wait;
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wait;
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end process;
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end process;
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