Apple-2-HW/AppleIISd
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LED removed from AddressDecoder

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This commit is contained in:
Florian Reitz 2019-02-14 20:37:35 +01:00
parent 936a0c2b5a
commit 7a0480f05e
8 changed files with 1720 additions and 1771 deletions
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2
.gitignore vendored
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@ -213,3 +213,5 @@ Hardware/SD_A2\.b\$1
*.tspec
VHDL/_pace\.ucf

6
VHDL/AddressDecoder.vhd
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@ -42,8 +42,7 @@ entity AddressDecoder is
DATA_EN : out std_logic; -- to CPLD
NG : out std_logic; -- to bus transceiver
NOE : out std_logic; -- to EEPROM
NWE : out std_logic; -- to EEPROM
LED : out std_logic);
NWE : out std_logic); -- to EEPROM
end AddressDecoder;
architecture Behavioral of AddressDecoder is
@ -66,7 +65,6 @@ begin
-- $C0xx to $C7xx is mapped to EEPROM bank 0
-- $C8xx to $CExx is mapped to banks 1 to 7
LED <= ncs;
B(8) <= (a_int(11) and not a_int(8))
or (a_int(11) and a_int(10) and a_int(9));
B(9) <= (a_int(11) and not a_int(9) and a_int(8))
@ -111,6 +109,4 @@ begin
a_int <= A;
end if;
end process;
end Behavioral;

9
VHDL/AddressDecoder_Test.vhd
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@ -53,8 +53,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
DATA_EN : OUT std_logic;
NG : OUT std_logic;
NOE : OUT std_logic;
NWE : OUT std_logic;
LED : OUT std_logic
NWE : OUT std_logic
);
END COMPONENT;
@ -75,7 +74,6 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
signal NG : std_logic;
signal NOE : std_logic;
signal NWE : std_logic;
signal LED : std_logic;
-- Clock period definitions
constant CLK_period : time := 142 ns;
@ -96,8 +94,7 @@ BEGIN
DATA_EN => DATA_EN,
NG => NG,
NOE => NOE,
NWE => NWE,
LED => LED
NWE => NWE
);
-- Clock process definitions
@ -157,7 +154,7 @@ BEGIN
wait until rising_edge(PHI0);
-- C8xx write access, selected
RNW <= '0'
RNW <= '0';
wait until rising_edge(PHI0);
NIO_STB <= '0';
wait until falling_edge(PHI0);

3334
VHDL/AppleIISd.jed
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File diff suppressed because it is too large Load Diff

88
VHDL/AppleIISd.ucf
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@ -1,45 +1,43 @@
#PACE: Start of Constraints generated by PACE
NET "DATA<2>" BUFG = DATA_GATE ;
NET "DATA<3>" BUFG = DATA_GATE ;
NET "DATA<4>" BUFG = DATA_GATE ;
#PACE: Start of PACE I/O Pin Assignments
NET "ADD_HIGH<11>" LOC = "P44" ;
NET "ADD_HIGH<10>" LOC = "P38" ;
NET "ADD_HIGH<8>" LOC = "P36" ;
NET "ADD_HIGH<9>" LOC = "P37" ;
NET "ADD_LOW<0>" LOC = "P19" ;
NET "ADD_LOW<1>" LOC = "P18" ;
NET "B<10>" LOC = "P22" ;
NET "B<8>" LOC = "P26" ;
NET "B<9>" LOC = "P27" ;
NET "CARD" LOC = "P33" ;
NET "DATA<0>" LOC = "P3" ;
NET "DATA<1>" LOC = "P4" ;
NET "DATA<2>" LOC = "P5" ;
NET "DATA<3>" LOC = "P6" ;
NET "DATA<4>" LOC = "P7" ;
NET "DATA<5>" LOC = "P9" ;
NET "DATA<6>" LOC = "P11" ;
NET "DATA<7>" LOC = "P13" ;
NET "CLK" LOC = "P43" ;
NET "LED" LOC = "P29" ;
NET "NDEV_SEL" LOC = "P24" ;
NET "NG" LOC = "P12" ;
NET "NIO_SEL" LOC = "P14" ;
NET "NIO_STB" LOC = "P42" ;
NET "NOE" LOC = "P25" ;
NET "NWE" LOC = "P5" ;
NET "PHI0" LOC = "P8" ;
NET "NRESET" LOC = "P20" ;
NET "RNW" LOC = "P1" ;
NET "MISO" LOC = "P40" ;
NET "MOSI" LOC = "P35" ;
NET "NSEL" LOC = "P28" ;
NET "SCLK" LOC = "P34" ;
NET "WP" LOC = "P39" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "ADD_HIGH<10>" LOC = "P38" ;
NET "ADD_HIGH<11>" LOC = "P44" ;
NET "ADD_HIGH<8>" LOC = "P36" ;
NET "ADD_HIGH<9>" LOC = "P37" ;
NET "ADD_LOW<0>" LOC = "P19" ;
NET "ADD_LOW<1>" LOC = "P18" ;
NET "B<10>" LOC = "P22" ;
NET "B<8>" LOC = "P26" ;
NET "B<9>" LOC = "P27" ;
NET "CARD" LOC = "P33" ;
NET "CLK" LOC = "P43" ;
NET "DATA<0>" LOC = "P3" ;
NET "DATA<1>" LOC = "P4" ;
NET "DATA<2>" LOC = "P5" | BUFG = DATA_GATE ;
NET "DATA<3>" LOC = "P6" | BUFG = DATA_GATE ;
NET "DATA<4>" LOC = "P7" | BUFG = DATA_GATE ;
NET "DATA<5>" LOC = "P9" ;
NET "DATA<6>" LOC = "P11" ;
NET "DATA<7>" LOC = "P13" ;
NET "LED" LOC = "P29" ;
NET "MISO" LOC = "P40" ;
NET "MOSI" LOC = "P35" ;
NET "NDEV_SEL" LOC = "P24" ;
NET "NG" LOC = "P12" ;
NET "NIO_SEL" LOC = "P14" ;
NET "NIO_STB" LOC = "P42" ;
NET "NOE" LOC = "P25" ;
NET "NRESET" LOC = "P20" ;
NET "NSEL" LOC = "P28" ;
NET "NWE" LOC = "P2" ;
NET "PHI0" LOC = "P8" ;
NET "RNW" LOC = "P1" ;
NET "SCLK" LOC = "P34" ;
NET "WP" LOC = "P39" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

4
VHDL/AppleIISd.vhd
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@ -105,8 +105,7 @@ Port (
DATA_EN : out std_logic;
NG : out std_logic;
NOE : out std_logic;
NWE : out std_logic;
LED : out std_logic
NWE : out std_logic
);
end component;
@ -144,7 +143,6 @@ begin
NOE => NOE,
NWE => NWE,
NG => NG
--LED => LED
);
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate

6
VHDL/AppleIISd.xise
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@ -184,9 +184,9 @@
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>

42
VHDL/_pace.ucf
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@ -1,42 +0,0 @@
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "a10" LOC = "P38" ;
NET "a8" LOC = "P36" ;
NET "a9" LOC = "P37" ;
NET "addr<0>" LOC = "P19" ;
NET "addr<1>" LOC = "P18" ;
NET "b10" LOC = "P22" ;
NET "b8" LOC = "P26" ;
NET "b9" LOC = "P27" ;
NET "card" LOC = "P33" ;
NET "data<0>" LOC = "P3" ;
NET "data<1>" LOC = "P5" ;
NET "data<2>" LOC = "P4" ;
NET "data<3>" LOC = "P6" ;
NET "data<4>" LOC = "P7" ;
NET "data<5>" LOC = "P9" ;
NET "data<6>" LOC = "P11" ;
NET "data<7>" LOC = "P13" ;
NET "extclk" LOC = "P42" ;
NET "led" LOC = "P29" ;
NET "ndev_sel" LOC = "P24" ;
NET "ng" LOC = "P12" ;
NET "nio_sel" LOC = "P14" ;
NET "nio_stb" LOC = "P40" ;
NET "nirq" LOC = "P2" ;
NET "noe" LOC = "P25" ;
NET "nphi2" LOC = "P44" ;
NET "nreset" LOC = "P20" ;
NET "nrw" LOC = "P1" ;
NET "spi_miso" LOC = "P43" ;
NET "spi_mosi" LOC = "P35" ;
NET "spi_Nsel" LOC = "P28" ;
NET "spi_sclk" LOC = "P34" ;
NET "wp" LOC = "P39" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE