From 819904bea27c6ac863fe52319c1606d295be9fbe Mon Sep 17 00:00:00 2001
From: freitz85 <freitz85@gmail.com>
Date: Tue, 10 Oct 2017 23:37:21 +0200
Subject: [PATCH] Spi simulation working

---
 VHDL/AppleIISd.vhd      | 23 +++++-----------
 VHDL/AppleIISd.xise     |  2 +-
 VHDL/AppleIISd_Test.vhd | 58 +++++++++++++++++++++++++++++------------
 3 files changed, 49 insertions(+), 34 deletions(-)

diff --git a/VHDL/AppleIISd.vhd b/VHDL/AppleIISd.vhd
index e286153..776e8e4 100644
--- a/VHDL/AppleIISd.vhd
+++ b/VHDL/AppleIISd.vhd
@@ -70,7 +70,6 @@ architecture Behavioral of AppleIISd is
     signal card_int : std_logic;
     signal miso_int : std_logic;
     
-    signal ndev_sel_int : std_logic;
     signal rnw_int : std_logic;
     signal data_en : std_logic;
         
@@ -117,7 +116,7 @@ begin
         nreset => NRESET,
         addr => addr_low_int,
         phi0 => PHI0,
-        ndev_sel => ndev_sel_int,
+        ndev_sel => NDEV_SEL,
         clk => CLK,
         miso => miso_int,
         mosi => MOSI,
@@ -144,13 +143,11 @@ begin
     ctrl_latch: process(CLK, NRESET)
     begin
         if(NRESET = '0') then
-            ndev_sel_int <= '1';
             rnw_int <= '1';
             wp_int <= '1';
             card_int <= '1';
             miso_int <= '1';
-        elsif rising_edge(CLK) then
-            ndev_sel_int <= NDEV_SEL;
+        elsif falling_edge(CLK) then
             rnw_int <= RNW;
             wp_int <= WP;
             card_int <= CARD;
@@ -161,27 +158,19 @@ begin
     DATA <= data_out when (data_en = '1') else (others => 'Z');      -- data bus tristate
     
     -- synthesis translate_off
-    --data_dbg <= data_in;
-    --add_dbg <= addr_low_int;
+    data_dbg <= data_in;
+    add_dbg <= addr_low_int;
     -- synthesis translate_on
     
     data_latch: process(CLK)
     begin
-        --if(rising_edge(CLK) and NDEV_SEL = '0') and (RNW = '0')) then
-        --if rising_edge(CLK) and (NDEV_SEL = '0') then
-        if rising_edge(CLK) then
+        if falling_edge(CLK) then
             if (NDEV_SEL = '0') then
                 data_in <= DATA;
+                addr_low_int <= ADD_LOW;
             end if;
         end if;
     end process;
-    
-    add_latch: process(NDEV_SEL)
-    begin
-        if falling_edge(NDEV_SEL) then
-            addr_low_int <= ADD_LOW;
-        end if;
-    end process;
 
 end Behavioral;
 
diff --git a/VHDL/AppleIISd.xise b/VHDL/AppleIISd.xise
index 76c5301..fe0899d 100644
--- a/VHDL/AppleIISd.xise
+++ b/VHDL/AppleIISd.xise
@@ -155,7 +155,7 @@
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="20 us" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="50 us" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
diff --git a/VHDL/AppleIISd_Test.vhd b/VHDL/AppleIISd_Test.vhd
index b5ea6ef..aa3e604 100644
--- a/VHDL/AppleIISd_Test.vhd
+++ b/VHDL/AppleIISd_Test.vhd
@@ -165,27 +165,13 @@ BEGIN
    stim_proc: process
    begin		
       -- hold reset state.
-      wait for CLK_period * 20;	
+      wait for CLK_period * 10;	
       NRESET <= '0';
       wait for CLK_period * 20;
       NRESET <= '1';
       wait for CLK_period * 10;
-      
-      -- read reg 0
       DATA <= (others => 'Z');
       ADD_LOW <= (others => 'U');
-      wait until falling_edge(PHI0);
-      wait for ADD_valid;
-      ADD_LOW <= (others => '0');
-      RNW <= '1';
-      DATA <= (others => 'U');
-      wait until rising_edge(PHI0);
-      NDEV_SEL <= '0';
-      DATA <= (others => 'Z');
-      wait until falling_edge(PHI0);
-      NDEV_SEL <= '1';
-      wait for ADD_hold;
-      ADD_LOW <= (others => 'U');
       
       -- read reg 3
       wait until falling_edge(PHI0);
@@ -215,10 +201,50 @@ BEGIN
       wait until falling_edge(PHI0);
       NDEV_SEL <= '1';
       wait for ADD_hold;
-      wait for CLK_period;
+      --wait for CLK_period;
       ADD_LOW <= (others => 'U');
       RNW <= '1';
       DATA <= (others => 'Z');
+      
+      -- write ece
+      wait for 20 us;
+      wait until falling_edge(PHI0);
+      wait for ADD_valid;
+      ADD_LOW <= "01";
+      RNW <= '0';
+      DATA <= (others => 'U');
+      wait until rising_edge(PHI0);
+      NDEV_SEL <= '0';
+      DATA <= (others => 'Z');
+      wait for DATA_valid;
+      DATA <= x"04";
+      wait until falling_edge(PHI0);
+      NDEV_SEL <= '1';
+      wait for ADD_hold;
+      --wait for CLK_period;
+      ADD_LOW <= (others => 'U');
+      RNW <= '1';
+      DATA <= (others => 'Z');
+      
+      -- send data
+      wait until falling_edge(PHI0);
+      wait for ADD_valid;
+      ADD_LOW <= (others => '0');
+      RNW <= '0';
+      DATA <= (others => 'U');
+      wait until rising_edge(PHI0);
+      NDEV_SEL <= '0';
+      DATA <= (others => 'Z');
+      wait for DATA_valid;
+      DATA <= (others => '0');
+      wait until falling_edge(PHI0);
+      NDEV_SEL <= '1';
+      wait for ADD_hold;
+      --wait for CLK_period;
+      ADD_LOW <= (others => 'U');
+      RNW <= '1';
+      DATA <= (others => 'Z');
+      
       wait;
    end process;