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AppleIISd
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test with clocked input buffers

This commit is contained in:
freitz85 2017-10-08 21:48:07 +02:00
parent ff074dc995
commit 84cfbdde92
12 changed files with 948 additions and 431 deletions
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434
VHDL/AddressDecoder.sch
View File

@ -9,49 +9,38 @@
<signal name="A10" />
<signal name="A9" />
<signal name="A8" />
<signal name="XLXN_10" />
<signal name="CLK" />
<signal name="XLXN_14" />
<signal name="B10" />
<signal name="B9" />
<signal name="B8" />
<signal name="NIO_SEL" />
<signal name="NIO_STB" />
<signal name="XLXN_38" />
<signal name="XLXN_46" />
<signal name="XLXN_47" />
<signal name="XLXN_10" />
<signal name="NDEV_SEL" />
<signal name="NOE" />
<signal name="XLXN_53" />
<signal name="RNW" />
<signal name="XLXN_55" />
<signal name="NG" />
<signal name="DATA_EN" />
<signal name="XLXN_46" />
<signal name="XLXN_103" />
<signal name="NIO_STB" />
<signal name="XLXN_110" />
<signal name="XLXN_116" />
<signal name="XLXN_117" />
<signal name="XLXN_118" />
<signal name="XLXN_119" />
<signal name="XLXN_120" />
<port polarity="Input" name="A10" />
<port polarity="Input" name="A9" />
<port polarity="Input" name="A8" />
<port polarity="Input" name="CLK" />
<port polarity="Output" name="B10" />
<port polarity="Output" name="B9" />
<port polarity="Output" name="B8" />
<port polarity="Input" name="NIO_SEL" />
<port polarity="Input" name="NIO_STB" />
<port polarity="Input" name="NDEV_SEL" />
<port polarity="Output" name="NOE" />
<port polarity="Input" name="RNW" />
<blockdef name="fdrs">
<timestamp>2001-3-9T11:23:0</timestamp>
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="320" y1="-256" y2="-256" x1="384" />
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="64" y1="-352" y2="-352" x1="0" />
<rect width="256" x="64" y="-320" height="256" />
<line x2="192" y1="-64" y2="-32" x1="192" />
<line x2="64" y1="-32" y2="-32" x1="192" />
<line x2="80" y1="-112" y2="-128" x1="64" />
<line x2="64" y1="-128" y2="-144" x1="80" />
<line x2="192" y1="-320" y2="-352" x1="192" />
<line x2="64" y1="-352" y2="-352" x1="192" />
</blockdef>
<port polarity="Output" name="NG" />
<port polarity="Output" name="DATA_EN" />
<port polarity="Input" name="NIO_STB" />
<blockdef name="inv">
<timestamp>2001-3-9T11:23:50</timestamp>
<line x2="64" y1="-32" y2="-32" x1="0" />
@ -61,12 +50,6 @@
<line x2="64" y1="0" y2="-64" x1="64" />
<circle r="16" cx="144" cy="-32" />
</blockdef>
<blockdef name="vcc">
<timestamp>2001-3-9T11:23:11</timestamp>
<line x2="32" y1="-64" y2="-64" x1="96" />
<line x2="64" y1="0" y2="-32" x1="64" />
<line x2="64" y1="-32" y2="-64" x1="64" />
</blockdef>
<blockdef name="and2">
<timestamp>2001-5-11T10:41:37</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
@ -77,199 +60,276 @@
<line x2="144" y1="-144" y2="-144" x1="64" />
<line x2="64" y1="-48" y2="-144" x1="64" />
</blockdef>
<blockdef name="and4">
<timestamp>2001-5-11T10:43:14</timestamp>
<line x2="64" y1="-112" y2="-112" x1="144" />
<arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
<line x2="144" y1="-208" y2="-208" x1="64" />
<line x2="64" y1="-64" y2="-256" x1="64" />
<line x2="192" y1="-160" y2="-160" x1="256" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="64" y1="-192" y2="-192" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-64" y2="-64" x1="0" />
</blockdef>
<blockdef name="nand2">
<timestamp>2001-3-9T11:23:50</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="216" y1="-96" y2="-96" x1="256" />
<circle r="12" cx="204" cy="-96" />
<blockdef name="and2b1">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-48" y2="-144" x1="64" />
<line x2="144" y1="-144" y2="-144" x1="64" />
<line x2="64" y1="-48" y2="-48" x1="144" />
<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
</blockdef>
<blockdef name="or2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="192" y1="-96" y2="-96" x1="256" />
<arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
<arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
<line x2="48" y1="-144" y2="-144" x1="112" />
<arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
<line x2="48" y1="-48" y2="-48" x1="112" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="40" y1="-64" y2="-64" x1="0" />
<circle r="12" cx="52" cy="-64" />
</blockdef>
<block symbolname="fdrs" name="XLXI_16">
<blockpin signalname="CLK" name="C" />
<blockpin signalname="XLXN_14" name="D" />
<blockpin signalname="XLXN_10" name="R" />
<blockpin signalname="XLXN_46" name="S" />
<blockpin signalname="XLXN_47" name="Q" />
<blockdef name="fdp">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="80" y1="-112" y2="-128" x1="64" />
<line x2="64" y1="-128" y2="-144" x1="80" />
<rect width="256" x="64" y="-320" height="256" />
<line x2="320" y1="-256" y2="-256" x1="384" />
<line x2="192" y1="-320" y2="-352" x1="192" />
<line x2="64" y1="-352" y2="-352" x1="192" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="64" y1="-352" y2="-352" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
</blockdef>
<blockdef name="gnd">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-128" y2="-96" x1="64" />
<line x2="64" y1="-64" y2="-80" x1="64" />
<line x2="40" y1="-64" y2="-64" x1="88" />
<line x2="60" y1="-32" y2="-32" x1="68" />
<line x2="52" y1="-48" y2="-48" x1="76" />
<line x2="64" y1="-64" y2="-96" x1="64" />
</blockdef>
<blockdef name="and4b1">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="40" y1="-64" y2="-64" x1="0" />
<circle r="12" cx="52" cy="-64" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-192" y2="-192" x1="0" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="192" y1="-160" y2="-160" x1="256" />
<line x2="64" y1="-64" y2="-256" x1="64" />
<line x2="64" y1="-112" y2="-112" x1="144" />
<arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
<line x2="144" y1="-208" y2="-208" x1="64" />
</blockdef>
<blockdef name="or4">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="48" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-192" y2="-192" x1="0" />
<line x2="48" y1="-256" y2="-256" x1="0" />
<line x2="192" y1="-160" y2="-160" x1="256" />
<arc ex="112" ey="-208" sx="192" sy="-160" r="88" cx="116" cy="-120" />
<line x2="48" y1="-208" y2="-208" x1="112" />
<line x2="48" y1="-112" y2="-112" x1="112" />
<line x2="48" y1="-256" y2="-208" x1="48" />
<line x2="48" y1="-64" y2="-112" x1="48" />
<arc ex="48" ey="-208" sx="48" sy="-112" r="56" cx="16" cy="-160" />
<arc ex="192" ey="-160" sx="112" sy="-112" r="88" cx="116" cy="-200" />
</blockdef>
<block symbolname="and2" name="XLXI_36">
<blockpin signalname="NOE" name="I0" />
<blockpin signalname="NDEV_SEL" name="I1" />
<blockpin signalname="NG" name="O" />
</block>
<block symbolname="vcc" name="XLXI_17">
<blockpin signalname="XLXN_14" name="P" />
</block>
<block symbolname="and2" name="XLXI_18">
<blockpin signalname="A10" name="I0" />
<blockpin signalname="XLXN_38" name="I1" />
<blockpin signalname="B10" name="O" />
</block>
<block symbolname="and2" name="XLXI_19">
<blockpin signalname="A9" name="I0" />
<blockpin signalname="XLXN_38" name="I1" />
<blockpin signalname="B9" name="O" />
</block>
<block symbolname="and2" name="XLXI_20">
<blockpin signalname="A8" name="I0" />
<blockpin signalname="XLXN_38" name="I1" />
<blockpin signalname="B8" name="O" />
<block symbolname="and2b1" name="XLXI_50">
<blockpin signalname="NDEV_SEL" name="I0" />
<blockpin signalname="RNW" name="I1" />
<blockpin signalname="DATA_EN" name="O" />
</block>
<block symbolname="inv" name="XLXI_22">
<blockpin signalname="NIO_SEL" name="I" />
<blockpin signalname="XLXN_46" name="O" />
</block>
<block symbolname="and4" name="XLXI_30">
<blockpin signalname="A8" name="I0" />
<blockpin signalname="A9" name="I1" />
<blockpin signalname="A10" name="I2" />
<blockpin signalname="XLXN_38" name="I3" />
<block symbolname="fdp" name="XLXI_61">
<blockpin signalname="XLXN_46" name="C" />
<blockpin signalname="XLXN_103" name="D" />
<blockpin signalname="XLXN_10" name="PRE" />
<blockpin signalname="XLXN_110" name="Q" />
</block>
<block symbolname="gnd" name="XLXI_63">
<blockpin signalname="XLXN_103" name="G" />
</block>
<block symbolname="and4b1" name="XLXI_66">
<blockpin signalname="NIO_STB" name="I0" />
<blockpin signalname="A8" name="I1" />
<blockpin signalname="A9" name="I2" />
<blockpin signalname="A10" name="I3" />
<blockpin signalname="XLXN_10" name="O" />
</block>
<block symbolname="inv" name="XLXI_31">
<blockpin signalname="NIO_STB" name="I" />
<blockpin signalname="XLXN_38" name="O" />
</block>
<block symbolname="nand2" name="XLXI_32">
<blockpin signalname="XLXN_47" name="I0" />
<blockpin signalname="NDEV_SEL" name="I1" />
<blockpin signalname="XLXN_55" name="O" />
</block>
<block symbolname="inv" name="XLXI_33">
<block symbolname="inv" name="XLXI_72">
<blockpin signalname="RNW" name="I" />
<blockpin signalname="XLXN_53" name="O" />
<blockpin signalname="XLXN_116" name="O" />
</block>
<block symbolname="or2" name="XLXI_34">
<blockpin signalname="XLXN_55" name="I0" />
<blockpin signalname="XLXN_53" name="I1" />
<block symbolname="inv" name="XLXI_73">
<blockpin signalname="NDEV_SEL" name="I" />
<blockpin signalname="XLXN_117" name="O" />
</block>
<block symbolname="or4" name="XLXI_74">
<blockpin signalname="XLXN_110" name="I0" />
<blockpin signalname="NIO_STB" name="I1" />
<blockpin signalname="XLXN_117" name="I2" />
<blockpin signalname="XLXN_116" name="I3" />
<blockpin signalname="NOE" name="O" />
</block>
<block symbolname="inv" name="XLXI_75">
<blockpin signalname="NIO_STB" name="I" />
<blockpin signalname="XLXN_119" name="O" />
</block>
<block symbolname="inv" name="XLXI_76">
<blockpin signalname="NIO_STB" name="I" />
<blockpin signalname="XLXN_120" name="O" />
</block>
<block symbolname="inv" name="XLXI_77">
<blockpin signalname="NIO_STB" name="I" />
<blockpin signalname="XLXN_118" name="O" />
</block>
<block symbolname="and2" name="XLXI_78">
<blockpin signalname="A10" name="I0" />
<blockpin signalname="XLXN_118" name="I1" />
<blockpin signalname="B10" name="O" />
</block>
<block symbolname="and2" name="XLXI_79">
<blockpin signalname="A9" name="I0" />
<blockpin signalname="XLXN_119" name="I1" />
<blockpin signalname="B9" name="O" />
</block>
<block symbolname="and2" name="XLXI_80">
<blockpin signalname="A8" name="I0" />
<blockpin signalname="XLXN_120" name="I1" />
<blockpin signalname="B8" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<branch name="A10">
<wire x2="592" y1="704" y2="704" x1="320" />
<wire x2="704" y1="704" y2="704" x1="592" />
<wire x2="592" y1="704" y2="992" x1="592" />
<wire x2="1088" y1="992" y2="992" x1="592" />
<wire x2="592" y1="1072" y2="1072" x1="320" />
<wire x2="592" y1="1072" y2="1360" x1="592" />
<wire x2="1152" y1="1360" y2="1360" x1="592" />
<wire x2="1184" y1="1360" y2="1360" x1="1152" />
<wire x2="672" y1="1072" y2="1072" x1="592" />
</branch>
<branch name="A9">
<wire x2="528" y1="768" y2="768" x1="320" />
<wire x2="704" y1="768" y2="768" x1="528" />
<wire x2="528" y1="768" y2="1136" x1="528" />
<wire x2="1088" y1="1136" y2="1136" x1="528" />
<wire x2="528" y1="1136" y2="1136" x1="320" />
<wire x2="528" y1="1136" y2="1504" x1="528" />
<wire x2="1152" y1="1504" y2="1504" x1="528" />
<wire x2="1184" y1="1504" y2="1504" x1="1152" />
<wire x2="672" y1="1136" y2="1136" x1="528" />
</branch>
<branch name="A8">
<wire x2="464" y1="832" y2="832" x1="320" />
<wire x2="704" y1="832" y2="832" x1="464" />
<wire x2="464" y1="832" y2="1280" x1="464" />
<wire x2="1088" y1="1280" y2="1280" x1="464" />
</branch>
<iomarker fontsize="28" x="320" y="704" name="A10" orien="R180" />
<iomarker fontsize="28" x="320" y="768" name="A9" orien="R180" />
<iomarker fontsize="28" x="320" y="832" name="A8" orien="R180" />
<branch name="CLK">
<wire x2="912" y1="576" y2="576" x1="320" />
<wire x2="912" y1="576" y2="640" x1="912" />
<wire x2="992" y1="640" y2="640" x1="912" />
<wire x2="464" y1="1200" y2="1200" x1="320" />
<wire x2="464" y1="1200" y2="1648" x1="464" />
<wire x2="1152" y1="1648" y2="1648" x1="464" />
<wire x2="1184" y1="1648" y2="1648" x1="1152" />
<wire x2="672" y1="1200" y2="1200" x1="464" />
</branch>
<branch name="B10">
<wire x2="1664" y1="960" y2="960" x1="1344" />
<wire x2="1472" y1="1328" y2="1328" x1="1440" />
<wire x2="1664" y1="1328" y2="1328" x1="1472" />
</branch>
<branch name="B9">
<wire x2="1664" y1="1104" y2="1104" x1="1344" />
<wire x2="1472" y1="1472" y2="1472" x1="1440" />
<wire x2="1664" y1="1472" y2="1472" x1="1472" />
</branch>
<branch name="B8">
<wire x2="1664" y1="1248" y2="1248" x1="1344" />
<wire x2="1472" y1="1616" y2="1616" x1="1440" />
<wire x2="1664" y1="1616" y2="1616" x1="1472" />
</branch>
<branch name="NIO_SEL">
<wire x2="352" y1="368" y2="368" x1="320" />
</branch>
<branch name="NIO_STB">
<wire x2="336" y1="640" y2="640" x1="320" />
</branch>
<iomarker fontsize="28" x="320" y="368" name="NIO_SEL" orien="R180" />
<iomarker fontsize="28" x="320" y="640" name="NIO_STB" orien="R180" />
<instance x="336" y="672" name="XLXI_31" orien="R0" />
<branch name="XLXN_38">
<wire x2="672" y1="640" y2="640" x1="560" />
<wire x2="704" y1="640" y2="640" x1="672" />
<wire x2="672" y1="640" y2="928" x1="672" />
<wire x2="1088" y1="928" y2="928" x1="672" />
<wire x2="672" y1="928" y2="1072" x1="672" />
<wire x2="1088" y1="1072" y2="1072" x1="672" />
<wire x2="672" y1="1072" y2="1216" x1="672" />
<wire x2="1088" y1="1216" y2="1216" x1="672" />
</branch>
<instance x="704" y="896" name="XLXI_30" orien="R0" />
<branch name="XLXN_10">
<wire x2="992" y1="736" y2="736" x1="960" />
<wire x2="960" y1="1168" y2="1168" x1="928" />
<wire x2="992" y1="1104" y2="1104" x1="960" />
<wire x2="960" y1="1104" y2="1168" x1="960" />
</branch>
<branch name="XLXN_14">
<wire x2="848" y1="496" y2="512" x1="848" />
<wire x2="992" y1="512" y2="512" x1="848" />
</branch>
<iomarker fontsize="28" x="320" y="576" name="CLK" orien="R180" />
<instance x="784" y="496" name="XLXI_17" orien="R0" />
<instance x="352" y="400" name="XLXI_22" orien="R0" />
<branch name="XLXN_46">
<wire x2="992" y1="368" y2="368" x1="576" />
<wire x2="992" y1="368" y2="416" x1="992" />
</branch>
<instance x="992" y="768" name="XLXI_16" orien="R0" />
<instance x="1088" y="1056" name="XLXI_18" orien="R0" />
<instance x="1088" y="1200" name="XLXI_19" orien="R0" />
<instance x="1088" y="1344" name="XLXI_20" orien="R0" />
<iomarker fontsize="28" x="1664" y="960" name="B10" orien="R0" />
<iomarker fontsize="28" x="1664" y="1104" name="B9" orien="R0" />
<iomarker fontsize="28" x="1664" y="1248" name="B8" orien="R0" />
<instance x="1424" y="432" name="XLXI_32" orien="R0" />
<branch name="XLXN_47">
<wire x2="1392" y1="512" y2="512" x1="1376" />
<wire x2="1424" y1="368" y2="368" x1="1392" />
<wire x2="1392" y1="368" y2="512" x1="1392" />
</branch>
<branch name="NDEV_SEL">
<wire x2="1424" y1="304" y2="304" x1="320" />
</branch>
<iomarker fontsize="28" x="320" y="304" name="NDEV_SEL" orien="R180" />
<instance x="352" y="272" name="XLXI_33" orien="R0" />
<branch name="NOE">
<wire x2="2016" y1="272" y2="272" x1="2000" />
</branch>
<branch name="XLXN_53">
<wire x2="1744" y1="240" y2="240" x1="576" />
<wire x2="1872" y1="704" y2="704" x1="1760" />
<wire x2="2208" y1="704" y2="704" x1="1872" />
<wire x2="1904" y1="512" y2="512" x1="1872" />
<wire x2="1872" y1="512" y2="704" x1="1872" />
</branch>
<branch name="RNW">
<wire x2="352" y1="240" y2="240" x1="320" />
<wire x2="1072" y1="608" y2="608" x1="320" />
<wire x2="1232" y1="608" y2="608" x1="1072" />
<wire x2="1072" y1="304" y2="608" x1="1072" />
<wire x2="1872" y1="304" y2="304" x1="1072" />
</branch>
<iomarker fontsize="28" x="320" y="240" name="RNW" orien="R180" />
<instance x="1744" y="368" name="XLXI_34" orien="R0" />
<branch name="XLXN_55">
<wire x2="1696" y1="336" y2="336" x1="1680" />
<wire x2="1744" y1="304" y2="304" x1="1696" />
<wire x2="1696" y1="304" y2="336" x1="1696" />
<branch name="NG">
<wire x2="2208" y1="480" y2="480" x1="2160" />
</branch>
<iomarker fontsize="28" x="320" y="1072" name="A10" orien="R180" />
<iomarker fontsize="28" x="320" y="1136" name="A9" orien="R180" />
<iomarker fontsize="28" x="320" y="1200" name="A8" orien="R180" />
<iomarker fontsize="28" x="1664" y="1328" name="B10" orien="R0" />
<iomarker fontsize="28" x="1664" y="1472" name="B9" orien="R0" />
<iomarker fontsize="28" x="1664" y="1616" name="B8" orien="R0" />
<iomarker fontsize="28" x="320" y="672" name="NDEV_SEL" orien="R180" />
<iomarker fontsize="28" x="320" y="608" name="RNW" orien="R180" />
<branch name="DATA_EN">
<wire x2="2208" y1="336" y2="336" x1="2128" />
</branch>
<branch name="NDEV_SEL">
<wire x2="1136" y1="672" y2="672" x1="320" />
<wire x2="1232" y1="672" y2="672" x1="1136" />
<wire x2="1136" y1="448" y2="672" x1="1136" />
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<wire x2="1904" y1="448" y2="448" x1="1392" />
<wire x2="1872" y1="368" y2="368" x1="1392" />
<wire x2="1392" y1="368" y2="448" x1="1392" />
</branch>
<branch name="NIO_SEL">
<wire x2="544" y1="880" y2="880" x1="320" />
</branch>
<instance x="992" y="752" name="XLXI_61" orien="M180" />
<instance x="544" y="912" name="XLXI_22" orien="R0" />
<branch name="XLXN_46">
<wire x2="992" y1="880" y2="880" x1="768" />
</branch>
<iomarker fontsize="28" x="320" y="880" name="NIO_SEL" orien="R180" />
<branch name="XLXN_103">
<wire x2="976" y1="960" y2="960" x1="928" />
<wire x2="976" y1="960" y2="1008" x1="976" />
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</branch>
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<iomarker fontsize="28" x="320" y="1264" name="NIO_STB" orien="R180" />
<instance x="672" y="1328" name="XLXI_66" orien="R0" />
<branch name="NIO_STB">
<wire x2="400" y1="1264" y2="1264" x1="320" />
<wire x2="640" y1="1264" y2="1264" x1="400" />
<wire x2="672" y1="1264" y2="1264" x1="640" />
<wire x2="640" y1="1264" y2="1296" x1="640" />
<wire x2="640" y1="1296" y2="1440" x1="640" />
<wire x2="640" y1="1440" y2="1584" x1="640" />
<wire x2="928" y1="1584" y2="1584" x1="640" />
<wire x2="928" y1="1440" y2="1440" x1="640" />
<wire x2="928" y1="1296" y2="1296" x1="640" />
<wire x2="1504" y1="736" y2="736" x1="400" />
<wire x2="400" y1="736" y2="1264" x1="400" />
</branch>
<branch name="XLXN_110">
<wire x2="1440" y1="1008" y2="1008" x1="1376" />
<wire x2="1440" y1="800" y2="1008" x1="1440" />
<wire x2="1504" y1="800" y2="800" x1="1440" />
</branch>
<instance x="1872" y="432" name="XLXI_50" orien="R0" />
<iomarker fontsize="28" x="2208" y="336" name="DATA_EN" orien="R0" />
<iomarker fontsize="28" x="2208" y="480" name="NG" orien="R0" />
<iomarker fontsize="28" x="2208" y="704" name="NOE" orien="R0" />
<instance x="1904" y="576" name="XLXI_36" orien="R0" />
<instance x="1232" y="640" name="XLXI_72" orien="R0" />
<instance x="1232" y="704" name="XLXI_73" orien="R0" />
<instance x="1504" y="864" name="XLXI_74" orien="R0" />
<branch name="XLXN_116">
<wire x2="1504" y1="608" y2="608" x1="1456" />
</branch>
<branch name="XLXN_117">
<wire x2="1504" y1="672" y2="672" x1="1456" />
</branch>
<instance x="928" y="1328" name="XLXI_77" orien="R0" />
<instance x="928" y="1472" name="XLXI_75" orien="R0" />
<instance x="928" y="1616" name="XLXI_76" orien="R0" />
<branch name="XLXN_118">
<wire x2="1184" y1="1296" y2="1296" x1="1152" />
</branch>
<instance x="1184" y="1424" name="XLXI_78" orien="R0" />
<instance x="1184" y="1568" name="XLXI_79" orien="R0" />
<instance x="1184" y="1712" name="XLXI_80" orien="R0" />
<branch name="XLXN_119">
<wire x2="1184" y1="1440" y2="1440" x1="1152" />
</branch>
<branch name="XLXN_120">
<wire x2="1184" y1="1584" y2="1584" x1="1152" />
</branch>
<iomarker fontsize="28" x="2016" y="272" name="NOE" orien="R0" />
</sheet>
</drawing>

38
VHDL/AddressDecoder.sym
View File

@ -1,42 +1,48 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="AddressDecoder">
<symboltype>BLOCK</symboltype>
<timestamp>2017-9-3T12:42:25</timestamp>
<timestamp>2017-10-8T19:38:25</timestamp>
<pin polarity="Input" x="0" y="-416" name="A10" />
<pin polarity="Input" x="0" y="-352" name="A9" />
<pin polarity="Input" x="0" y="-288" name="A8" />
<pin polarity="Input" x="0" y="-224" name="CLK" />
<pin polarity="Input" x="0" y="-160" name="NIO_SEL" />
<pin polarity="Input" x="0" y="-96" name="NIO_STB" />
<pin polarity="Input" x="0" y="-32" name="NDEV_SEL" />
<pin polarity="Input" x="0" y="32" name="RNW" />
<pin polarity="Input" x="0" y="-96" name="NIO_STB" />
<pin polarity="Output" x="384" y="-416" name="B10" />
<pin polarity="Output" x="384" y="-288" name="B9" />
<pin polarity="Output" x="384" y="-160" name="B8" />
<pin polarity="Output" x="384" y="-32" name="NOE" />
<pin polarity="Output" x="384" y="96" name="NG" />
<pin polarity="Output" x="384" y="160" name="DATA_EN" />
<graph>
<rect width="256" x="64" y="-448" height="448" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-456" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin A10" />
<line x2="0" y1="-416" y2="-416" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin A9" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin A8" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin CLK" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin NIO_SEL" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin NIO_STB" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin NDEV_SEL" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="32" type="pin RNW" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin NIO_STB" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin B10" />
<line x2="384" y1="-416" y2="-416" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin B9" />
<line x2="384" y1="-288" y2="-288" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin B8" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin NOE" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="96" type="pin NG" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="160" type="pin DATA_EN" />
<line x2="384" y1="160" y2="160" x1="320" />
<line x2="384" y1="96" y2="96" x1="320" />
<line x2="0" y1="32" y2="32" x1="64" />
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<line x2="384" y1="-32" y2="-32" x1="320" />
<rect width="256" x="64" y="-448" height="640" />
</graph>
</symbol>

BIN
VHDL/AppleIISd.ipf
View File

Binary file not shown.

57
VHDL/AppleIISd.sym Normal file
View File

@ -0,0 +1,57 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="AppleIISd">
<symboltype>BLOCK</symboltype>
<timestamp>2017-10-8T19:42:44</timestamp>
<pin polarity="Input" x="0" y="-304" name="is_read" />
<pin polarity="Input" x="0" y="-240" name="reset" />
<pin polarity="Input" x="0" y="-816" name="phi0" />
<pin polarity="Input" x="0" y="-176" name="selected" />
<pin polarity="Input" x="0" y="-768" name="clk" />
<pin polarity="Input" x="0" y="-704" name="miso" />
<pin polarity="Input" x="0" y="-480" name="wp" />
<pin polarity="Input" x="0" y="-416" name="card" />
<pin polarity="Input" x="0" y="-112" name="data_in(7:0)" />
<pin polarity="Input" x="0" y="-368" name="addr(1:0)" />
<pin polarity="Output" x="384" y="-816" name="mosi" />
<pin polarity="Output" x="384" y="-752" name="sclk" />
<pin polarity="Output" x="384" y="-688" name="nsel" />
<pin polarity="Output" x="384" y="-560" name="led" />
<pin polarity="Output" x="384" y="-512" name="data_out(7:0)" />
<graph>
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-904" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-304" type="pin is_read" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-240" type="pin reset" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="68" y="-816" type="pin phi0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-176" type="pin selected" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-768" type="pin clk" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-704" type="pin miso" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-480" type="pin wp" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin card" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-112" type="pin data_in(7:0)" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-368" type="pin addr(1:0)" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-816" type="pin mosi" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-752" type="pin sclk" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-688" type="pin nsel" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-560" type="pin led" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-512" type="pin data_out(7:0)" />
<line x2="0" y1="-480" y2="-480" x1="64" />
<line x2="0" y1="-416" y2="-416" x1="64" />
<rect width="256" x="64" y="-896" height="860" />
<line x2="64" y1="-816" y2="-816" x1="0" />
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<line x2="0" y1="-240" y2="-240" x1="64" />
<line x2="0" y1="-176" y2="-176" x1="64" />
<rect width="64" x="0" y="-124" height="24" />
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<rect width="64" x="0" y="-380" height="24" />
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<line x2="384" y1="-688" y2="-688" x1="320" />
<line x2="384" y1="-816" y2="-816" x1="320" />
<rect width="64" x="320" y="-524" height="24" />
<line x2="384" y1="-512" y2="-512" x1="320" />
<line x2="384" y1="-560" y2="-560" x1="320" />
</graph>
</symbol>

64
VHDL/AppleIISd.ucf
View File

@ -1,38 +1,38 @@
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "a10" LOC = "P38" ;
NET "a8" LOC = "P36" ;
NET "a9" LOC = "P37" ;
NET "addr<0>" LOC = "P19" ;
NET "addr<1>" LOC = "P18" ;
NET "b10" LOC = "P22" ;
NET "b8" LOC = "P26" ;
NET "b9" LOC = "P27" ;
NET "card" LOC = "P33" ;
NET "data<0>" LOC = "P3" ;
NET "data<1>" LOC = "P4" ;
NET "data<2>" LOC = "P5" ;
NET "data<3>" LOC = "P6" ;
NET "data<4>" LOC = "P7" ;
NET "data<5>" LOC = "P9" ;
NET "data<6>" LOC = "P11" ;
NET "data<7>" LOC = "P13" ;
NET "clk_7m" LOC = "P43" ;
NET "led" LOC = "P29" ;
NET "ndev_sel" LOC = "P24" ;
NET "ng" LOC = "P12" ;
NET "nio_sel" LOC = "P14" ;
NET "nio_stb" LOC = "P42" ;
NET "noe" LOC = "P25" ;
NET "clk_phi0" LOC = "P8" ;
NET "nreset" LOC = "P20" ;
NET "nrw" LOC = "P1" ;
NET "spi_miso" LOC = "P40" ;
NET "spi_mosi" LOC = "P35" ;
NET "spi_Nsel" LOC = "P28" ;
NET "spi_sclk" LOC = "P34" ;
NET "wp" LOC = "P39" ;
NET "A10" LOC = "P38" ;
NET "A8" LOC = "P36" ;
NET "A9" LOC = "P37" ;
NET "A0" LOC = "P19" ;
NET "A1" LOC = "P18" ;
NET "B10" LOC = "P22" ;
NET "B8" LOC = "P26" ;
NET "B9" LOC = "P27" ;
NET "CARD" LOC = "P33" ;
NET "DATA<0>" LOC = "P3" ;
NET "DATA<1>" LOC = "P4" ;
NET "DATA<2>" LOC = "P5" ;
NET "DATA<3>" LOC = "P6" ;
NET "DATA<4>" LOC = "P7" ;
NET "DATA<5>" LOC = "P9" ;
NET "DATA<6>" LOC = "P11" ;
NET "DATA<7>" LOC = "P13" ;
NET "CLK" LOC = "P43" ;
NET "LED" LOC = "P29" ;
NET "NDEV_SEL" LOC = "P24" ;
NET "NG" LOC = "P12" ;
NET "NIO_SEL" LOC = "P14" ;
NET "NIO_STB" LOC = "P42" ;
NET "NOE" LOC = "P25" ;
NET "PHI0" LOC = "P8" ;
NET "NRESET" LOC = "P20" ;
NET "RNW" LOC = "P1" ;
NET "MISO" LOC = "P40" ;
NET "MOSI" LOC = "P35" ;
NET "NSEL" LOC = "P28" ;
NET "SCLK" LOC = "P34" ;
NET "WP" LOC = "P39" ;
#PACE: Start of PACE Area Constraints

269
VHDL/AppleIISd.vhd
View File

@ -36,31 +36,21 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AppleIISd is
Port (
data : inout STD_LOGIC_VECTOR (7 downto 0);
nrw : in STD_LOGIC;
nreset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0);
is_read : in STD_LOGIC;
reset : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (1 downto 0);
clk_phi0 : in STD_LOGIC;
ndev_sel : in STD_LOGIC;
clk_7m : in STD_LOGIC;
spi_miso: in std_logic;
spi_mosi : out STD_LOGIC;
spi_sclk : out STD_LOGIC;
spi_Nsel : out STD_LOGIC;
phi0 : in STD_LOGIC;
selected : in STD_LOGIC;
clk : in STD_LOGIC;
miso: in std_logic;
mosi : out STD_LOGIC;
sclk : out STD_LOGIC;
nsel : out STD_LOGIC;
wp : in STD_LOGIC;
card : in STD_LOGIC;
led : out STD_LOGIC;
a8 : in std_logic;
a9 : in std_logic;
a10 : in std_logic;
nio_sel : in std_logic;
nio_stb : in std_logic;
b8 : out std_logic;
b9 : out std_logic;
b10 : out std_logic;
noe : out std_logic;
ng : out std_logic
led : out STD_LOGIC
);
constant DIV_WIDTH : integer := 3;
@ -69,36 +59,21 @@ end AppleIISd;
architecture Behavioral of AppleIISd is
-- interface signals
signal selected: std_logic;
signal reset: std_logic;
signal is_read: std_logic;
signal int_din: std_logic_vector (7 downto 0);
signal int_dout: std_logic_vector (7 downto 0);
signal int_mosi: std_logic;
signal int_miso: std_logic;
signal int_sclk: std_logic;
--------------------------
-- internal state
signal spidatain: std_logic_vector (7 downto 0);
signal spidataout: std_logic_vector (7 downto 0);
signal inited: std_logic; -- card initialized
signal inited_set: std_logic;
-- spi register flags
signal tc: std_logic; -- transmission complete; cleared on spi data read
signal bsy: std_logic; -- SPI busy
signal frx: std_logic; -- fast receive mode
signal tmo: std_logic; -- tri-state mosi
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
signal cpol: std_logic; -- shift clock polarity; 0=rising edge, 1=falling edge
signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
signal slavesel: std_logic; -- slave select output (0=selected)
signal int_miso: std_logic;
--------------------------
-- helper signals
@ -111,56 +86,15 @@ architecture Behavioral of AppleIISd is
-- spi clock
signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
-- TODO divcnt is not used at all??
signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
--signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
signal shiftclk : std_logic;
component AddressDecoder
port (
A8 : in std_logic;
A9 : in std_logic;
A10 : in std_logic;
CLK : in std_logic;
NDEV_SEL : in std_logic;
NIO_SEL : in std_logic;
NIO_STB : in std_logic;
RNW : in std_logic;
B8 : out std_logic;
B9 : out std_logic;
B10 : out std_logic;
NOE : out std_logic
);
end component;
begin
add_dec : AddressDecoder
port map (
A8 => a8,
A9 => a9,
A10 => a10,
CLK => clk_7m,
NDEV_SEL => ndev_sel,
NIO_SEL => nio_sel,
NIO_STB => nio_stb,
RNW => nrw,
B8 => b8,
B9 => b9,
B10 => b10,
NOE => noe);
led <= not (inited_set);
begin
--led <= not (inited);
led <= not bsy;
--led <= not (bsy or not slavesel);
ng <= ndev_sel and nio_sel and nio_stb;
bsy <= start_shifting or shifting2;
process(clk_7m, reset, card, inited_set)
begin
if(reset = '1' or card = '1') then
inited <= '0';
elsif rising_edge(inited_set) then
inited <= '1';
end if;
end process;
process(start_shifting, shiftdone, shiftclk)
begin
if (rising_edge(shiftclk)) then
@ -199,7 +133,7 @@ begin
end if;
end process;
inproc: process(reset, shifting2, shiftcnt, shiftclk, spidatain, int_miso)
inproc: process(reset, shifting2, shiftcnt, shiftclk, spidatain, miso)
begin
if (reset='1') then
spidatain <= (others => '0');
@ -212,31 +146,31 @@ begin
end if;
end process;
outproc: process(reset, shifting2, spidataout, cpol, cpha, shiftcnt, shiftclk)
outproc: process(reset, shifting2, spidataout, shiftcnt, shiftclk)
begin
if (reset='1') then
int_mosi <= '1';
int_sclk <= cpol;
mosi <= '1';
sclk <= '0';
else
-- clock is sync'd
if (rising_edge(shiftclk)) then
if (shifting2='0' or shiftdone = '1') then
int_mosi <= '1';
int_sclk <= cpol;
mosi <= '1';
sclk <= '0';
else
-- output data directly from output register
case shiftcnt(3 downto 1) is
when "000" => int_mosi <= spidataout(7);
when "001" => int_mosi <= spidataout(6);
when "010" => int_mosi <= spidataout(5);
when "011" => int_mosi <= spidataout(4);
when "100" => int_mosi <= spidataout(3);
when "101" => int_mosi <= spidataout(2);
when "110" => int_mosi <= spidataout(1);
when "111" => int_mosi <= spidataout(0);
when others => int_mosi <= '1';
when "000" => mosi <= spidataout(7);
when "001" => mosi <= spidataout(6);
when "010" => mosi <= spidataout(5);
when "011" => mosi <= spidataout(4);
when "100" => mosi <= spidataout(3);
when "101" => mosi <= spidataout(2);
when "110" => mosi <= spidataout(1);
when "111" => mosi <= spidataout(0);
when others => mosi <= '1';
end case;
int_sclk <= cpol xor cpha xor shiftcnt(0);
sclk <= '0' xor '0' xor shiftcnt(0);
end if;
end if;
end if;
@ -244,13 +178,13 @@ begin
-- shift operation enable
shiften: process(reset, selected, nrw, addr, frx, shiftdone)
shiften: process(reset, selected, is_read, addr, frx, shiftdone)
begin
-- start shifting
if (reset='1' or shiftdone='1') then
start_shifting <= '0';
elsif (falling_edge(selected) and addr="00" and (frx='1' or nrw='0')) then
-- access to register 00, either write (nrw=0) or fast receive bit set (frx)
elsif (falling_edge(selected) and addr="00" and (frx='1' or is_read='0')) then
-- access to register 00, either write (is_read=0) or fast receive bit set (frx)
-- then both types of access (write but also read)
start_shifting <= '1';
end if;
@ -259,49 +193,33 @@ begin
--------------------------
-- spiclk - spi clock generation
-- spiclk is still 2 times the freq. than sclk
clksrc <= clk_phi0 when (ece = '0') else clk_7m;
clksrc <= phi0 when (ece = '0') else clk;
-- is a pulse signal to allow for divisor==0
--shiftclk <= clksrc when divcnt = "000000" else '0';
shiftclk <= clksrc when bsy = '1' else '0';
clkgen: process(reset, divisor, clksrc)
begin
if (reset='1') then
divcnt <= divisor;
elsif (falling_edge(clksrc)) then
if (shiftclk = '1') then
divcnt <= divisor;
else
divcnt <= divcnt - 1;
end if;
end if;
end process;
-- clkgen: process(reset, divisor, clksrc)
-- begin
-- if (reset='1') then
-- divcnt <= divisor;
-- elsif (falling_edge(clksrc)) then
-- if (shiftclk = '1') then
-- divcnt <= divisor;
-- else
-- divcnt <= divcnt - 1;
-- end if;
-- end if;
-- end process;
--------------------------
-- interface section
-- inputs
reset <= not (nreset);
selected <= not(ndev_sel);
int_din <= data;
int_miso <= (spi_miso and not slavesel);
process(selected, clk_7m)
begin
if(selected = '0') then
is_read <= '0';
elsif(rising_edge(clk_7m) and selected = '1' and clk_phi0 = '1' and nrw = '1') then
is_read <= '1';
end if;
end process;
int_miso <= (miso and not slavesel);
-- outputs
data <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
spi_sclk <= int_sclk;
spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state
spi_Nsel <= slavesel;
nsel <= slavesel;
tc_proc: process (selected, shiftdone)
begin
if (shiftdone = '1') then
@ -314,72 +232,61 @@ begin
--------------------------
-- cpu register section
-- cpu read
cpu_read: process (is_read, addr,
spidatain, tc, bsy, frx, tmo, ece, cpol, cpha, divisor,
slavesel, wp, card, inited)
cpu_read: process(addr, spidatain, tc, bsy, frx,
ece, divisor, slavesel, wp, card, inited)
begin
if (is_read = '1') then
case addr is
when "00" => -- read SPI data in
int_dout <= spidatain;
when "01" => -- read status register
int_dout(0) <= cpha;
int_dout(1) <= cpol;
int_dout(2) <= ece;
int_dout(3) <= tmo;
int_dout(4) <= frx;
int_dout(5) <= bsy;
int_dout(6) <= '0';
int_dout(7) <= tc;
when "10" => -- read sclk divisor
int_dout(DIV_WIDTH-1 downto 0) <= divisor;
int_dout(7 downto 3) <= (others => '0');
when "11" => -- read slave select / slave interrupt state
int_dout(0) <= slavesel;
int_dout(4 downto 1) <= (others => '0');
int_dout(5) <= wp;
int_dout(6) <= card;
int_dout(7) <= inited;
when others =>
int_dout <= (others => '0');
end case;
else
int_dout <= (others => '0');
end if;
case addr is
when "00" => -- read SPI data in
data_out <= spidatain;
when "01" => -- read status register
data_out(0) <= '0';
data_out(1) <= '0';
data_out(2) <= ece;
data_out(3) <= '0';
data_out(4) <= frx;
data_out(5) <= bsy;
data_out(6) <= '0';
data_out(7) <= tc;
when "10" => -- read sclk divisor
data_out(DIV_WIDTH-1 downto 0) <= divisor;
data_out(7 downto 3) <= (others => '0');
when "11" => -- read slave select / slave interrupt state
data_out(0) <= slavesel;
data_out(4 downto 1) <= (others => '0');
data_out(5) <= wp;
data_out(6) <= card;
data_out(7) <= inited;
when others =>
data_out <= (others => '0');
end case;
end process;
-- cpu write
cpu_write: process(reset, selected, nrw, addr, int_din, card, inited)
cpu_write: process(reset, selected, is_read, addr, data_in, card, inited)
begin
if (reset = '1') then
cpha <= '0';
cpol <= '0';
ece <= '0';
tmo <= '0';
frx <= '0';
slavesel <= '1';
divisor <= (others => '0');
spidataout <= (others => '1');
inited_set <= '0';
inited <= '0';
elsif (card = '1') then
inited_set <= '0';
elsif (falling_edge(selected) and nrw = '0') then
inited <= '0';
elsif (falling_edge(selected) and is_read = '0') then
case addr is
when "00" => -- write SPI data out (see other process above)
spidataout <= int_din;
spidataout <= data_in;
when "01" => -- write status register
cpha <= int_din(0);
cpol <= int_din(1);
ece <= int_din(2);
tmo <= int_din(3);
frx <= int_din(4);
ece <= data_in(2);
frx <= data_in(4);
-- no bit 5 - 7
when "10" => -- write divisor
divisor <= int_din(DIV_WIDTH-1 downto 0);
divisor <= data_in(DIV_WIDTH-1 downto 0);
when "11" => -- write slave select / slave interrupt enable
slavesel <= int_din(0);
slavesel <= data_in(0);
-- no bit 1 - 6
inited_set <= int_din(7);
inited <= data_in(7);
when others =>
end case;
end if;

36
VHDL/AppleIISd.xise
View File

@ -17,15 +17,19 @@
<files>
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="io_buffers.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
@ -42,7 +46,7 @@
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="90" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@ -74,10 +78,10 @@
<property xil_pn:name="Hierarchy Separator" xil_pn:value="_" xil_pn:valueState="non-default"/>
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AppleIISd|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="AppleIISd.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|io_buffers" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="io_buffers.sch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/io_buffers" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
@ -86,10 +90,13 @@
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
@ -112,14 +119,14 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="io_buffers" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AppleIISd_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="io_buffers_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
@ -161,14 +168,15 @@
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>

1
VHDL/in_buf.jhd Normal file
View File

@ -0,0 +1 @@
MODULE in_buf

12
VHDL/in_buf.sch Normal file
View File

@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="xc9500xl" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
</sheet>
</drawing>

466
VHDL/io_buffers.sch Normal file
View File

@ -0,0 +1,466 @@
<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="xc9500xl" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="NIO_SEL" />
<signal name="DATA(7:0)" />
<signal name="CLK" />
<signal name="RNW" />
<signal name="XLXN_52(7:0)" />
<signal name="XLXN_56" />
<signal name="NIO_STB" />
<signal name="NDEV_SEL" />
<signal name="XLXN_65" />
<signal name="XLXN_66" />
<signal name="XLXN_77" />
<signal name="XLXN_78" />
<signal name="XLXN_79" />
<signal name="XLXN_84" />
<signal name="A8" />
<signal name="A9" />
<signal name="A10" />
<signal name="PHI0" />
<signal name="MISO" />
<signal name="A0" />
<signal name="A1" />
<signal name="CARD" />
<signal name="WP" />
<signal name="add(1:0)" />
<signal name="add(0)" />
<signal name="add(1)" />
<signal name="XLXN_100" />
<signal name="XLXN_101" />
<signal name="NRESET" />
<signal name="XLXN_105(7:0)" />
<signal name="B10" />
<signal name="B9" />
<signal name="B8" />
<signal name="NOE" />
<signal name="NG" />
<signal name="MOSI" />
<signal name="SCLK" />
<signal name="NSEL" />
<signal name="XLXN_126" />
<signal name="XLXN_128" />
<signal name="XLXN_129" />
<signal name="XLXN_131" />
<signal name="LED" />
<port polarity="Input" name="NIO_SEL" />
<port polarity="BiDirectional" name="DATA(7:0)" />
<port polarity="Input" name="CLK" />
<port polarity="Input" name="RNW" />
<port polarity="Input" name="NIO_STB" />
<port polarity="Input" name="NDEV_SEL" />
<port polarity="Input" name="A8" />
<port polarity="Input" name="A9" />
<port polarity="Input" name="A10" />
<port polarity="Input" name="PHI0" />
<port polarity="Input" name="MISO" />
<port polarity="Input" name="A0" />
<port polarity="Input" name="A1" />
<port polarity="Input" name="CARD" />
<port polarity="Input" name="WP" />
<port polarity="Input" name="NRESET" />
<port polarity="Output" name="B10" />
<port polarity="Output" name="B9" />
<port polarity="Output" name="B8" />
<port polarity="Output" name="NOE" />
<port polarity="Output" name="NG" />
<port polarity="Output" name="MOSI" />
<port polarity="Output" name="SCLK" />
<port polarity="Output" name="NSEL" />
<port polarity="Output" name="LED" />
<blockdef name="ld4">
<timestamp>2000-1-1T10:10:10</timestamp>
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</blockdef>
<blockdef name="bufe8">
<timestamp>2000-1-1T10:10:10</timestamp>
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<line x2="96" y1="-48" y2="-96" x1="96" />
</blockdef>
<blockdef name="AddressDecoder">
<timestamp>2017-10-8T19:38:25</timestamp>
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<rect width="256" x="64" y="-448" height="640" />
</blockdef>
<blockdef name="AppleIISd">
<timestamp>2017-10-8T19:42:44</timestamp>
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<rect width="64" x="0" y="-124" height="24" />
<line x2="0" y1="-112" y2="-112" x1="64" />
<rect width="64" x="0" y="-380" height="24" />
<line x2="0" y1="-368" y2="-368" x1="64" />
<line x2="0" y1="-768" y2="-768" x1="64" />
<line x2="0" y1="-704" y2="-704" x1="64" />
<line x2="384" y1="-752" y2="-752" x1="320" />
<line x2="384" y1="-688" y2="-688" x1="320" />
<line x2="384" y1="-816" y2="-816" x1="320" />
<rect width="64" x="320" y="-524" height="24" />
<line x2="384" y1="-512" y2="-512" x1="320" />
<line x2="384" y1="-560" y2="-560" x1="320" />
</blockdef>
<blockdef name="inv">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="160" y1="-32" y2="-32" x1="224" />
<line x2="128" y1="-64" y2="-32" x1="64" />
<line x2="64" y1="-32" y2="0" x1="128" />
<line x2="64" y1="0" y2="-64" x1="64" />
<circle r="16" cx="144" cy="-32" />
</blockdef>
<block symbolname="ld8" name="XLXI_2">
<blockpin signalname="DATA(7:0)" name="D(7:0)" />
<blockpin signalname="CLK" name="G" />
<blockpin signalname="XLXN_105(7:0)" name="Q(7:0)" />
</block>
<block symbolname="bufe8" name="XLXI_8">
<blockpin signalname="XLXN_56" name="E" />
<blockpin signalname="XLXN_52(7:0)" name="I(7:0)" />
<blockpin signalname="DATA(7:0)" name="O(7:0)" />
</block>
<block symbolname="AddressDecoder" name="XLXI_11">
<blockpin signalname="XLXN_79" name="A10" />
<blockpin signalname="XLXN_78" name="A9" />
<blockpin signalname="XLXN_77" name="A8" />
<blockpin signalname="XLXN_65" name="NIO_SEL" />
<blockpin signalname="XLXN_84" name="NDEV_SEL" />
<blockpin signalname="XLXN_128" name="RNW" />
<blockpin signalname="XLXN_66" name="NIO_STB" />
<blockpin signalname="B10" name="B10" />
<blockpin signalname="B9" name="B9" />
<blockpin signalname="B8" name="B8" />
<blockpin signalname="NOE" name="NOE" />
<blockpin signalname="NG" name="NG" />
<blockpin signalname="XLXN_56" name="DATA_EN" />
</block>
<block symbolname="AppleIISd" name="XLXI_17">
<blockpin signalname="XLXN_128" name="is_read" />
<blockpin signalname="XLXN_126" name="reset" />
<blockpin signalname="PHI0" name="phi0" />
<blockpin signalname="XLXN_129" name="selected" />
<blockpin signalname="CLK" name="clk" />
<blockpin signalname="XLXN_131" name="miso" />
<blockpin signalname="XLXN_101" name="wp" />
<blockpin signalname="XLXN_100" name="card" />
<blockpin signalname="XLXN_105(7:0)" name="data_in(7:0)" />
<blockpin signalname="add(1:0)" name="addr(1:0)" />
<blockpin signalname="MOSI" name="mosi" />
<blockpin signalname="SCLK" name="sclk" />
<blockpin signalname="NSEL" name="nsel" />
<blockpin signalname="LED" name="led" />
<blockpin signalname="XLXN_52(7:0)" name="data_out(7:0)" />
</block>
<block symbolname="ld4" name="XLXI_3">
<blockpin signalname="NIO_SEL" name="D0" />
<blockpin signalname="NIO_STB" name="D1" />
<blockpin signalname="NDEV_SEL" name="D2" />
<blockpin signalname="RNW" name="D3" />
<blockpin signalname="CLK" name="G" />
<blockpin signalname="XLXN_65" name="Q0" />
<blockpin signalname="XLXN_66" name="Q1" />
<blockpin signalname="XLXN_84" name="Q2" />
<blockpin signalname="XLXN_128" name="Q3" />
</block>
<block symbolname="ld4" name="XLXI_21">
<blockpin signalname="WP" name="D0" />
<blockpin signalname="CARD" name="D1" />
<blockpin signalname="A1" name="D2" />
<blockpin signalname="A0" name="D3" />
<blockpin signalname="CLK" name="G" />
<blockpin signalname="XLXN_101" name="Q0" />
<blockpin signalname="XLXN_100" name="Q1" />
<blockpin signalname="add(1)" name="Q2" />
<blockpin signalname="add(0)" name="Q3" />
</block>
<block symbolname="ld4" name="XLXI_22">
<blockpin signalname="MISO" name="D0" />
<blockpin signalname="A10" name="D1" />
<blockpin signalname="A9" name="D2" />
<blockpin signalname="A8" name="D3" />
<blockpin signalname="CLK" name="G" />
<blockpin signalname="XLXN_131" name="Q0" />
<blockpin signalname="XLXN_79" name="Q1" />
<blockpin signalname="XLXN_78" name="Q2" />
<blockpin signalname="XLXN_77" name="Q3" />
</block>
<block symbolname="inv" name="XLXI_23">
<blockpin signalname="XLXN_84" name="I" />
<blockpin signalname="XLXN_129" name="O" />
</block>
<block symbolname="inv" name="XLXI_24">
<blockpin signalname="NRESET" name="I" />
<blockpin signalname="XLXN_126" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="656" y="528" name="XLXI_2" orien="R0" />
<iomarker fontsize="28" x="224" y="400" name="CLK" orien="R180" />
<branch name="NIO_SEL">
<wire x2="656" y1="1808" y2="1808" x1="528" />
</branch>
<branch name="DATA(7:0)">
<wire x2="608" y1="272" y2="272" x1="560" />
<wire x2="656" y1="272" y2="272" x1="608" />
<wire x2="608" y1="144" y2="272" x1="608" />
<wire x2="2800" y1="144" y2="144" x1="608" />
<wire x2="2800" y1="144" y2="624" x1="2800" />
<wire x2="2800" y1="624" y2="624" x1="2736" />
</branch>
<iomarker fontsize="28" x="560" y="272" name="DATA(7:0)" orien="R180" />
<branch name="CLK">
<wire x2="304" y1="400" y2="400" x1="224" />
<wire x2="656" y1="400" y2="400" x1="304" />
<wire x2="304" y1="400" y2="528" x1="304" />
<wire x2="304" y1="528" y2="944" x1="304" />
<wire x2="304" y1="944" y2="1472" x1="304" />
<wire x2="656" y1="1472" y2="1472" x1="304" />
<wire x2="304" y1="1472" y2="1648" x1="304" />
<wire x2="304" y1="1648" y2="2128" x1="304" />
<wire x2="656" y1="2128" y2="2128" x1="304" />
<wire x2="656" y1="944" y2="944" x1="304" />
<wire x2="1904" y1="528" y2="528" x1="304" />
<wire x2="2000" y1="368" y2="368" x1="1904" />
<wire x2="1904" y1="368" y2="528" x1="1904" />
</branch>
<branch name="RNW">
<wire x2="656" y1="2000" y2="2000" x1="528" />
</branch>
<branch name="XLXN_56">
<wire x2="2512" y1="2128" y2="2128" x1="1808" />
<wire x2="2512" y1="688" y2="2128" x1="2512" />
</branch>
<branch name="NIO_STB">
<wire x2="656" y1="1872" y2="1872" x1="528" />
</branch>
<branch name="NDEV_SEL">
<wire x2="656" y1="1936" y2="1936" x1="528" />
</branch>
<branch name="XLXN_66">
<wire x2="1424" y1="1872" y2="1872" x1="1040" />
</branch>
<instance x="656" y="1600" name="XLXI_22" orien="R0" />
<branch name="XLXN_78">
<wire x2="1216" y1="1280" y2="1280" x1="1040" />
<wire x2="1216" y1="1280" y2="1616" x1="1216" />
<wire x2="1424" y1="1616" y2="1616" x1="1216" />
</branch>
<branch name="XLXN_79">
<wire x2="1248" y1="1216" y2="1216" x1="1040" />
<wire x2="1248" y1="1216" y2="1552" x1="1248" />
<wire x2="1424" y1="1552" y2="1552" x1="1248" />
</branch>
<instance x="1328" y="1328" name="XLXI_23" orien="R0" />
<branch name="XLXN_84">
<wire x2="1312" y1="1936" y2="1936" x1="1040" />
<wire x2="1424" y1="1936" y2="1936" x1="1312" />
<wire x2="1328" y1="1296" y2="1296" x1="1312" />
<wire x2="1312" y1="1296" y2="1936" x1="1312" />
</branch>
<instance x="656" y="1072" name="XLXI_21" orien="R0" />
<branch name="A8">
<wire x2="656" y1="1344" y2="1344" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="1344" name="A8" orien="R180" />
<branch name="A9">
<wire x2="656" y1="1280" y2="1280" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="1280" name="A9" orien="R180" />
<branch name="A10">
<wire x2="656" y1="1216" y2="1216" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="1216" name="A10" orien="R180" />
<branch name="PHI0">
<wire x2="2000" y1="320" y2="320" x1="1776" />
</branch>
<branch name="MISO">
<wire x2="656" y1="1152" y2="1152" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="1152" name="MISO" orien="R180" />
<branch name="A0">
<wire x2="656" y1="816" y2="816" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="816" name="A0" orien="R180" />
<branch name="A1">
<wire x2="656" y1="752" y2="752" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="752" name="A1" orien="R180" />
<branch name="CARD">
<wire x2="656" y1="688" y2="688" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="688" name="CARD" orien="R180" />
<branch name="WP">
<wire x2="656" y1="624" y2="624" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="624" name="WP" orien="R180" />
<bustap x2="1168" y1="752" y2="752" x1="1264" />
<bustap x2="1168" y1="816" y2="816" x1="1264" />
<branch name="add(0)">
<wire x2="1168" y1="816" y2="816" x1="1040" />
</branch>
<branch name="add(1)">
<wire x2="1168" y1="752" y2="752" x1="1040" />
</branch>
<instance x="1552" y="1264" name="XLXI_24" orien="R0" />
<iomarker fontsize="28" x="1536" y="1232" name="NRESET" orien="R180" />
<branch name="NRESET">
<wire x2="1552" y1="1232" y2="1232" x1="1536" />
</branch>
<branch name="XLXN_105(7:0)">
<wire x2="1600" y1="272" y2="272" x1="1040" />
<wire x2="1600" y1="272" y2="1024" x1="1600" />
<wire x2="2000" y1="1024" y2="1024" x1="1600" />
</branch>
<instance x="2000" y="1136" name="XLXI_17" orien="R0">
</instance>
<branch name="XLXN_101">
<wire x2="1056" y1="624" y2="624" x1="1040" />
<wire x2="1056" y1="624" y2="656" x1="1056" />
<wire x2="2000" y1="656" y2="656" x1="1056" />
</branch>
<branch name="XLXN_100">
<wire x2="1056" y1="688" y2="688" x1="1040" />
<wire x2="1056" y1="688" y2="720" x1="1056" />
<wire x2="2000" y1="720" y2="720" x1="1056" />
</branch>
<branch name="add(1:0)">
<wire x2="1264" y1="752" y2="768" x1="1264" />
<wire x2="1264" y1="768" y2="816" x1="1264" />
<wire x2="2000" y1="768" y2="768" x1="1264" />
</branch>
<instance x="656" y="2256" name="XLXI_3" orien="R0" />
<branch name="XLXN_65">
<wire x2="1424" y1="1808" y2="1808" x1="1040" />
</branch>
<iomarker fontsize="28" x="528" y="1936" name="NDEV_SEL" orien="R180" />
<iomarker fontsize="28" x="528" y="1872" name="NIO_STB" orien="R180" />
<iomarker fontsize="28" x="528" y="1808" name="NIO_SEL" orien="R180" />
<iomarker fontsize="28" x="528" y="2000" name="RNW" orien="R180" />
<instance x="1424" y="1968" name="XLXI_11" orien="R0">
</instance>
<branch name="XLXN_77">
<wire x2="1184" y1="1344" y2="1344" x1="1040" />
<wire x2="1184" y1="1344" y2="1680" x1="1184" />
<wire x2="1424" y1="1680" y2="1680" x1="1184" />
</branch>
<branch name="B10">
<wire x2="1840" y1="1552" y2="1552" x1="1808" />
</branch>
<iomarker fontsize="28" x="1840" y="1552" name="B10" orien="R0" />
<branch name="B9">
<wire x2="1840" y1="1680" y2="1680" x1="1808" />
</branch>
<iomarker fontsize="28" x="1840" y="1680" name="B9" orien="R0" />
<branch name="B8">
<wire x2="1840" y1="1808" y2="1808" x1="1808" />
</branch>
<iomarker fontsize="28" x="1840" y="1808" name="B8" orien="R0" />
<branch name="NOE">
<wire x2="1840" y1="1936" y2="1936" x1="1808" />
</branch>
<iomarker fontsize="28" x="1840" y="1936" name="NOE" orien="R0" />
<branch name="NG">
<wire x2="1840" y1="2064" y2="2064" x1="1808" />
</branch>
<iomarker fontsize="28" x="1840" y="2064" name="NG" orien="R0" />
<iomarker fontsize="28" x="1776" y="320" name="PHI0" orien="R180" />
<branch name="XLXN_126">
<wire x2="1888" y1="1232" y2="1232" x1="1776" />
<wire x2="2000" y1="896" y2="896" x1="1888" />
<wire x2="1888" y1="896" y2="1232" x1="1888" />
</branch>
<branch name="XLXN_128">
<wire x2="1280" y1="2000" y2="2000" x1="1040" />
<wire x2="1424" y1="2000" y2="2000" x1="1280" />
<wire x2="1280" y1="1168" y2="2000" x1="1280" />
<wire x2="1680" y1="1168" y2="1168" x1="1280" />
<wire x2="2000" y1="832" y2="832" x1="1680" />
<wire x2="1680" y1="832" y2="1168" x1="1680" />
</branch>
<branch name="XLXN_129">
<wire x2="1792" y1="1296" y2="1296" x1="1552" />
<wire x2="1792" y1="960" y2="1296" x1="1792" />
<wire x2="2000" y1="960" y2="960" x1="1792" />
</branch>
<branch name="XLXN_131">
<wire x2="1520" y1="1152" y2="1152" x1="1040" />
<wire x2="1520" y1="592" y2="1152" x1="1520" />
<wire x2="1936" y1="592" y2="592" x1="1520" />
<wire x2="2000" y1="432" y2="432" x1="1936" />
<wire x2="1936" y1="432" y2="592" x1="1936" />
</branch>
<branch name="NSEL">
<wire x2="2400" y1="448" y2="448" x1="2384" />
<wire x2="2416" y1="448" y2="448" x1="2400" />
<wire x2="2448" y1="448" y2="448" x1="2416" />
</branch>
<branch name="SCLK">
<wire x2="2400" y1="384" y2="384" x1="2384" />
<wire x2="2448" y1="384" y2="384" x1="2400" />
</branch>
<branch name="MOSI">
<wire x2="2400" y1="320" y2="320" x1="2384" />
<wire x2="2448" y1="320" y2="320" x1="2400" />
</branch>
<instance x="2512" y="592" name="XLXI_8" orien="M180" />
<branch name="XLXN_52(7:0)">
<wire x2="2512" y1="624" y2="624" x1="2384" />
</branch>
<iomarker fontsize="28" x="2448" y="448" name="NSEL" orien="R0" />
<iomarker fontsize="28" x="2448" y="384" name="SCLK" orien="R0" />
<iomarker fontsize="28" x="2448" y="320" name="MOSI" orien="R0" />
<branch name="LED">
<wire x2="2400" y1="576" y2="576" x1="2384" />
<wire x2="2448" y1="576" y2="576" x1="2400" />
</branch>
<iomarker fontsize="28" x="2448" y="576" name="LED" orien="R0" />
</sheet>
</drawing>

0
VHDL/io_buffers.tim Normal file
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2
VHDL/sch2HdlBatchFile
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@ -1 +1 @@
sch2hdl,-intstyle,ise,-family,xc9500xl,-verilog,U:/AppleIISd/VHDL/AddressDecoder.vf,-w,U:/AppleIISd/VHDL/AddressDecoder.sch
sch2hdl,-intstyle,ise,-family,xc9500xl,-verilog,U:/AppleIISd/VHDL/io_buffers.vf,-w,U:/AppleIISd/VHDL/io_buffers.sch