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Test bench

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This commit is contained in:
freitz85 2017-10-10 02:53:21 +02:00
parent 797993500e
commit 8a6e7e647e
2 changed files with 32 additions and 9 deletions
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21
VHDL/IO.vhd
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@ -52,7 +52,10 @@ Port (
MOSI : out std_logic; MOSI : out std_logic;
NSEL : out std_logic; NSEL : out std_logic;
SCLK : out std_logic; SCLK : out std_logic;
WP : in std_logic WP : in std_logic;
data_dbg : out std_logic_vector (7 downto 0);
add_dbg : out std_logic_vector (1 downto 0)
); );
end IO; end IO;
@ -160,17 +163,23 @@ begin
end process; end process;
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
data_dbg <= data_in;
add_dbg <= addr_low_int;
data_latch: process(ndev_sel) data_latch: process(CLK)
begin begin
if(rising_edge(ndev_sel) and (rnw_int = '0')) then --if(rising_edge(CLK) and NDEV_SEL = '0') and (RNW = '0')) then
data_in <= DATA; --if rising_edge(CLK) and (NDEV_SEL = '0') then
if rising_edge(CLK) then
if (NDEV_SEL = '0') then
data_in <= DATA;
end if;
end if; end if;
end process; end process;
add_latch: process(ndev_sel) add_latch: process(NDEV_SEL)
begin begin
if falling_edge(ndev_sel) then if falling_edge(NDEV_SEL) then
addr_low_int <= ADD_LOW; addr_low_int <= ADD_LOW;
end if; end if;
end process; end process;

20
VHDL/IO_Test.vhd
View File

@ -62,7 +62,10 @@ ARCHITECTURE behavior OF IO_Test IS
MOSI : OUT std_logic; MOSI : OUT std_logic;
NSEL : OUT std_logic; NSEL : OUT std_logic;
SCLK : OUT std_logic; SCLK : OUT std_logic;
WP : IN std_logic WP : IN std_logic;
data_dbg : out std_logic_vector (7 downto 0);
add_dbg : out std_logic_vector (1 downto 0)
); );
END COMPONENT; END COMPONENT;
@ -94,6 +97,9 @@ ARCHITECTURE behavior OF IO_Test IS
signal MOSI : std_logic; signal MOSI : std_logic;
signal NSEL : std_logic; signal NSEL : std_logic;
signal SCLK : std_logic; signal SCLK : std_logic;
signal data_dbg : std_logic_vector (7 downto 0);
signal add_dbg : std_logic_vector (1 downto 0);
-- Clock period definitions -- Clock period definitions
constant CLK_period : time := 142 ns; constant CLK_period : time := 142 ns;
@ -123,7 +129,10 @@ BEGIN
MOSI => MOSI, MOSI => MOSI,
NSEL => NSEL, NSEL => NSEL,
SCLK => SCLK, SCLK => SCLK,
WP => WP WP => WP,
data_dbg => data_dbg,
add_dbg => add_dbg
); );
-- Clock process definitions -- Clock process definitions
@ -159,6 +168,7 @@ BEGIN
wait for CLK_period * 10; wait for CLK_period * 10;
-- read reg 0 -- read reg 0
DATA <= (others => 'Z');
wait until falling_edge(PHI0); wait until falling_edge(PHI0);
wait for 300 ns; wait for 300 ns;
ADD_LOW <= (others => '0'); ADD_LOW <= (others => '0');
@ -191,12 +201,16 @@ BEGIN
wait for 300 ns; wait for 300 ns;
ADD_LOW <= (others => '0'); ADD_LOW <= (others => '0');
RNW <= '0'; RNW <= '0';
DATA <= (others => 'U');
wait until rising_edge(PHI0); wait until rising_edge(PHI0);
NDEV_SEL <= '0'; NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait for 200 ns;
DATA <= (others => '0'); DATA <= (others => '0');
wait until falling_edge(PHI0); wait until falling_edge(PHI0);
NDEV_SEL <= '1'; NDEV_SEL <= '1';
wait for CLK_period; wait for 15 ns;
--wait for CLK_period;
ADD_LOW <= (others => 'U'); ADD_LOW <= (others => 'U');
RNW <= '1'; RNW <= '1';
DATA <= (others => 'Z'); DATA <= (others => 'Z');