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Test for old AddressDecoder

This commit is contained in:
freitz85 2017-10-16 20:21:09 +02:00
parent f2314f838d
commit b37df65a45
9 changed files with 1054 additions and 563 deletions
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15
VHDL/AddressDecoder.vhd
View File

@ -63,11 +63,16 @@ begin
B <= A when (NIO_STB = '0') else (others => '0');
DATA_EN <= RNW and not ndev_sel_int and PHI0;
NG <= (ndev_sel_int and noe_int) or not PHI0;
NOE <= noe_int or not PHI0;
noe_int <= not RNW or not ndev_sel_int
or (nio_sel_int and nio_stb_int)
or (nio_sel_int and ncs);
--NG <= (ndev_sel_int and noe_int) or not PHI0;
--NOE <= noe_int or not PHI0;
--noe_int <= not RNW or not ndev_sel_int
-- or (nio_sel_int and nio_stb_int)
-- or (nio_sel_int and ncs);
NG <= (NDEV_SEL and NIO_SEL and NIO_STB)
or (ncs and NDEV_SEL and NIO_SEL);
NOE <= not RNW or not NDEV_SEL
or (not NIO_STB and ncs);
cfxx <= A(8) and A(9) and A(10) and not nio_stb_int;

1
VHDL/AddressDecoder_old.jhd Normal file
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@ -0,0 +1 @@
MODULE AddressDecoder_old

275
VHDL/AddressDecoder_old.sch Normal file
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@ -0,0 +1,275 @@
<?xml version="1.0" encoding="UTF-8"?>
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<attr value="xc9500xl" name="DeviceFamilyName">
<trait delete="all:0" />
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<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="A10" />
<signal name="A9" />
<signal name="A8" />
<signal name="XLXN_10" />
<signal name="CLK" />
<signal name="XLXN_14" />
<signal name="B10" />
<signal name="B9" />
<signal name="B8" />
<signal name="NIO_SEL" />
<signal name="NIO_STB" />
<signal name="XLXN_38" />
<signal name="XLXN_46" />
<signal name="XLXN_47" />
<signal name="NDEV_SEL" />
<signal name="NOE" />
<signal name="XLXN_53" />
<signal name="RNW" />
<signal name="XLXN_55" />
<port polarity="Input" name="A10" />
<port polarity="Input" name="A9" />
<port polarity="Input" name="A8" />
<port polarity="Input" name="CLK" />
<port polarity="Output" name="B10" />
<port polarity="Output" name="B9" />
<port polarity="Output" name="B8" />
<port polarity="Input" name="NIO_SEL" />
<port polarity="Input" name="NIO_STB" />
<port polarity="Input" name="NDEV_SEL" />
<port polarity="Output" name="NOE" />
<port polarity="Input" name="RNW" />
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<timestamp>2001-5-11T10:41:37</timestamp>
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</blockdef>
<blockdef name="nand2">
<timestamp>2001-3-9T11:23:50</timestamp>
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<timestamp>2000-1-1T10:10:10</timestamp>
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<line x2="48" y1="-48" y2="-48" x1="112" />
</blockdef>
<block symbolname="fdrs" name="XLXI_16">
<blockpin signalname="CLK" name="C" />
<blockpin signalname="XLXN_14" name="D" />
<blockpin signalname="XLXN_10" name="R" />
<blockpin signalname="XLXN_46" name="S" />
<blockpin signalname="XLXN_47" name="Q" />
</block>
<block symbolname="vcc" name="XLXI_17">
<blockpin signalname="XLXN_14" name="P" />
</block>
<block symbolname="and2" name="XLXI_18">
<blockpin signalname="A10" name="I0" />
<blockpin signalname="XLXN_38" name="I1" />
<blockpin signalname="B10" name="O" />
</block>
<block symbolname="and2" name="XLXI_19">
<blockpin signalname="A9" name="I0" />
<blockpin signalname="XLXN_38" name="I1" />
<blockpin signalname="B9" name="O" />
</block>
<block symbolname="and2" name="XLXI_20">
<blockpin signalname="A8" name="I0" />
<blockpin signalname="XLXN_38" name="I1" />
<blockpin signalname="B8" name="O" />
</block>
<block symbolname="inv" name="XLXI_22">
<blockpin signalname="NIO_SEL" name="I" />
<blockpin signalname="XLXN_46" name="O" />
</block>
<block symbolname="and4" name="XLXI_30">
<blockpin signalname="A8" name="I0" />
<blockpin signalname="A9" name="I1" />
<blockpin signalname="A10" name="I2" />
<blockpin signalname="XLXN_38" name="I3" />
<blockpin signalname="XLXN_10" name="O" />
</block>
<block symbolname="inv" name="XLXI_31">
<blockpin signalname="NIO_STB" name="I" />
<blockpin signalname="XLXN_38" name="O" />
</block>
<block symbolname="nand2" name="XLXI_32">
<blockpin signalname="XLXN_47" name="I0" />
<blockpin signalname="NDEV_SEL" name="I1" />
<blockpin signalname="XLXN_55" name="O" />
</block>
<block symbolname="inv" name="XLXI_33">
<blockpin signalname="RNW" name="I" />
<blockpin signalname="XLXN_53" name="O" />
</block>
<block symbolname="or2" name="XLXI_34">
<blockpin signalname="XLXN_55" name="I0" />
<blockpin signalname="XLXN_53" name="I1" />
<blockpin signalname="NOE" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<branch name="A10">
<wire x2="592" y1="704" y2="704" x1="320" />
<wire x2="704" y1="704" y2="704" x1="592" />
<wire x2="592" y1="704" y2="992" x1="592" />
<wire x2="1088" y1="992" y2="992" x1="592" />
</branch>
<branch name="A9">
<wire x2="528" y1="768" y2="768" x1="320" />
<wire x2="704" y1="768" y2="768" x1="528" />
<wire x2="528" y1="768" y2="1136" x1="528" />
<wire x2="1088" y1="1136" y2="1136" x1="528" />
</branch>
<branch name="A8">
<wire x2="464" y1="832" y2="832" x1="320" />
<wire x2="704" y1="832" y2="832" x1="464" />
<wire x2="464" y1="832" y2="1280" x1="464" />
<wire x2="1088" y1="1280" y2="1280" x1="464" />
</branch>
<iomarker fontsize="28" x="320" y="704" name="A10" orien="R180" />
<iomarker fontsize="28" x="320" y="768" name="A9" orien="R180" />
<iomarker fontsize="28" x="320" y="832" name="A8" orien="R180" />
<branch name="CLK">
<wire x2="912" y1="576" y2="576" x1="320" />
<wire x2="912" y1="576" y2="640" x1="912" />
<wire x2="992" y1="640" y2="640" x1="912" />
</branch>
<branch name="B10">
<wire x2="1664" y1="960" y2="960" x1="1344" />
</branch>
<branch name="B9">
<wire x2="1664" y1="1104" y2="1104" x1="1344" />
</branch>
<branch name="B8">
<wire x2="1664" y1="1248" y2="1248" x1="1344" />
</branch>
<branch name="NIO_SEL">
<wire x2="352" y1="368" y2="368" x1="320" />
</branch>
<branch name="NIO_STB">
<wire x2="336" y1="640" y2="640" x1="320" />
</branch>
<iomarker fontsize="28" x="320" y="368" name="NIO_SEL" orien="R180" />
<iomarker fontsize="28" x="320" y="640" name="NIO_STB" orien="R180" />
<instance x="336" y="672" name="XLXI_31" orien="R0" />
<branch name="XLXN_38">
<wire x2="672" y1="640" y2="640" x1="560" />
<wire x2="704" y1="640" y2="640" x1="672" />
<wire x2="672" y1="640" y2="928" x1="672" />
<wire x2="1088" y1="928" y2="928" x1="672" />
<wire x2="672" y1="928" y2="1072" x1="672" />
<wire x2="1088" y1="1072" y2="1072" x1="672" />
<wire x2="672" y1="1072" y2="1216" x1="672" />
<wire x2="1088" y1="1216" y2="1216" x1="672" />
</branch>
<instance x="704" y="896" name="XLXI_30" orien="R0" />
<branch name="XLXN_10">
<wire x2="992" y1="736" y2="736" x1="960" />
</branch>
<branch name="XLXN_14">
<wire x2="848" y1="496" y2="512" x1="848" />
<wire x2="992" y1="512" y2="512" x1="848" />
</branch>
<iomarker fontsize="28" x="320" y="576" name="CLK" orien="R180" />
<instance x="784" y="496" name="XLXI_17" orien="R0" />
<instance x="352" y="400" name="XLXI_22" orien="R0" />
<branch name="XLXN_46">
<wire x2="992" y1="368" y2="368" x1="576" />
<wire x2="992" y1="368" y2="416" x1="992" />
</branch>
<instance x="992" y="768" name="XLXI_16" orien="R0" />
<instance x="1088" y="1056" name="XLXI_18" orien="R0" />
<instance x="1088" y="1200" name="XLXI_19" orien="R0" />
<instance x="1088" y="1344" name="XLXI_20" orien="R0" />
<iomarker fontsize="28" x="1664" y="960" name="B10" orien="R0" />
<iomarker fontsize="28" x="1664" y="1104" name="B9" orien="R0" />
<iomarker fontsize="28" x="1664" y="1248" name="B8" orien="R0" />
<instance x="1424" y="432" name="XLXI_32" orien="R0" />
<branch name="XLXN_47">
<wire x2="1392" y1="512" y2="512" x1="1376" />
<wire x2="1424" y1="368" y2="368" x1="1392" />
<wire x2="1392" y1="368" y2="512" x1="1392" />
</branch>
<branch name="NDEV_SEL">
<wire x2="1424" y1="304" y2="304" x1="320" />
</branch>
<iomarker fontsize="28" x="320" y="304" name="NDEV_SEL" orien="R180" />
<instance x="352" y="272" name="XLXI_33" orien="R0" />
<branch name="NOE">
<wire x2="2016" y1="272" y2="272" x1="2000" />
</branch>
<branch name="XLXN_53">
<wire x2="1744" y1="240" y2="240" x1="576" />
</branch>
<branch name="RNW">
<wire x2="352" y1="240" y2="240" x1="320" />
</branch>
<iomarker fontsize="28" x="320" y="240" name="RNW" orien="R180" />
<instance x="1744" y="368" name="XLXI_34" orien="R0" />
<branch name="XLXN_55">
<wire x2="1696" y1="336" y2="336" x1="1680" />
<wire x2="1744" y1="304" y2="304" x1="1696" />
<wire x2="1696" y1="304" y2="336" x1="1696" />
</branch>
<iomarker fontsize="28" x="2016" y="272" name="NOE" orien="R0" />
</sheet>
</drawing>

0
VHDL/AddressDecoder_old.schlog Normal file
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172
VHDL/AddressDecoder_old_Test.vhd Normal file
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@ -0,0 +1,172 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:42:22 10/10/2017
-- Design Name:
-- Module Name: C:/Git/AppleIISd/VHDL/AddressDecoder_Test.vhd
-- Project Name: AppleIISd
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: AddressDecoder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY AddressDecoder_old_Test IS
END AddressDecoder_old_Test;
ARCHITECTURE behavior OF AddressDecoder_old_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT AddressDecoder_old
PORT(
A8 : IN std_logic;
A9 : IN std_logic;
A10 : IN std_logic;
B8 : OUT std_logic;
B9 : OUT std_logic;
B10 : OUT std_logic;
RNW : IN std_logic;
CLK : IN std_logic;
NDEV_SEL : IN std_logic;
NIO_SEL : IN std_logic;
NIO_STB : IN std_logic;
NOE : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(10 downto 8) := "101";
signal RNW : std_logic := '1';
signal NDEV_SEL : std_logic := '1';
signal NIO_SEL : std_logic := '1';
signal NIO_STB : std_logic := '1';
signal NRESET : std_logic := '1';
signal CLK : std_logic := '0';
signal PHI0 : std_logic := '1';
--Outputs
signal B : std_logic_vector(10 downto 8);
signal DATA_EN : std_logic;
signal NG : std_logic;
signal NOE : std_logic;
-- Clock period definitions
constant CLK_period : time := 142 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: AddressDecoder_old PORT MAP (
A8 => A(8),
A9 => A(9),
A10 => A(10),
B8 => B(8),
B9 => B(9),
B10 => B(10),
RNW => RNW,
CLK => CLK,
NDEV_SEL => NDEV_SEL,
NIO_SEL => NIO_SEL,
NIO_STB => NIO_STB,
NOE => NOE
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
PHI0_process :process(CLK)
variable counter : integer range 0 to 7;
begin
if rising_edge(CLK) or falling_edge(CLK) then
counter := counter + 1;
if counter = 7 then
PHI0 <= not PHI0;
counter := 0;
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state.
wait for CLK_period * 10;
NRESET <= '0';
wait for CLK_period * 20;
NRESET <= '1';
wait for CLK_period * 10;
-- insert stimulus here
-- CPLD access
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- CnXX access
NIO_SEL <= '0';
wait until falling_edge(PHI0);
NIO_SEL <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- C8xx access, selected
NIO_STB <= '0';
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- CPLD access
NDEV_SEL <= '0';
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- CFFF access
A <= "111";
NIO_STB <= '0';
wait until falling_edge(PHI0);
A <= "000";
NIO_STB <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- C8xx access, unselected
NIO_STB <= '0';
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
wait;
end process;
END;

1092
VHDL/AppleIISd.jed
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25
VHDL/AppleIISd.xise
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@ -16,28 +16,35 @@
<files>
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
</file>
<file xil_pn:name="AddressDecoder_old.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AddressDecoder_old_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="52"/>
</file>
</files>
<properties>
@ -152,8 +159,8 @@
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
@ -163,7 +170,7 @@
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@ -198,7 +205,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>

37
VHDL/AppleIISd_Test.vhd
View File

@ -265,6 +265,38 @@ BEGIN
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
-- read eprom low
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
ADD_HIGH <= "101";
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NIO_SEL <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NIO_SEL <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
-- read eprom high
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
ADD_HIGH <= "101";
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NIO_STB <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
-- read $CFFF
wait until falling_edge(PHI0);
wait for ADD_valid;
@ -289,15 +321,14 @@ BEGIN
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NIO_SEL <= '0';
NIO_STB <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NIO_SEL <= '1';
NIO_STB <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
wait;
end process;

0
VHDL/sch2HdlBatchFile Normal file
View File