mirror of
https://github.com/freitz85/AppleIISd.git
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Test for old AddressDecoder
This commit is contained in:
freitz85
parent
f2314f838d
commit
b37df65a45
@ -63,11 +63,16 @@ begin
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B <= A when (NIO_STB = '0') else (others => '0');
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B <= A when (NIO_STB = '0') else (others => '0');
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DATA_EN <= RNW and not ndev_sel_int and PHI0;
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DATA_EN <= RNW and not ndev_sel_int and PHI0;
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NG <= (ndev_sel_int and noe_int) or not PHI0;
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--NG <= (ndev_sel_int and noe_int) or not PHI0;
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NOE <= noe_int or not PHI0;
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--NOE <= noe_int or not PHI0;
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noe_int <= not RNW or not ndev_sel_int
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--noe_int <= not RNW or not ndev_sel_int
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or (nio_sel_int and nio_stb_int)
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-- or (nio_sel_int and nio_stb_int)
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or (nio_sel_int and ncs);
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-- or (nio_sel_int and ncs);
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NG <= (NDEV_SEL and NIO_SEL and NIO_STB)
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or (ncs and NDEV_SEL and NIO_SEL);
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NOE <= not RNW or not NDEV_SEL
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or (not NIO_STB and ncs);
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cfxx <= A(8) and A(9) and A(10) and not nio_stb_int;
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cfxx <= A(8) and A(9) and A(10) and not nio_stb_int;
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1
VHDL/AddressDecoder_old.jhd
Normal file
1
VHDL/AddressDecoder_old.jhd
Normal file
@ -0,0 +1 @@
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MODULE AddressDecoder_old
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275
VHDL/AddressDecoder_old.sch
Normal file
275
VHDL/AddressDecoder_old.sch
Normal file
@ -0,0 +1,275 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<drawing version="7">
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<attr value="xc9500xl" name="DeviceFamilyName">
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<trait delete="all:0" />
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<trait editname="all:0" />
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<trait edittrait="all:0" />
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</attr>
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<netlist>
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<signal name="A10" />
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<signal name="A9" />
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<signal name="A8" />
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<signal name="XLXN_10" />
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<signal name="CLK" />
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<signal name="XLXN_14" />
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<signal name="B10" />
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<signal name="B9" />
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<signal name="B8" />
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<signal name="NIO_SEL" />
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<signal name="NIO_STB" />
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<signal name="XLXN_38" />
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<signal name="XLXN_46" />
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<signal name="XLXN_47" />
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<signal name="NDEV_SEL" />
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<signal name="NOE" />
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<signal name="XLXN_53" />
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<signal name="RNW" />
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<signal name="XLXN_55" />
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<port polarity="Input" name="A10" />
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<port polarity="Input" name="A9" />
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<port polarity="Input" name="A8" />
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<port polarity="Input" name="CLK" />
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<port polarity="Output" name="B10" />
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<port polarity="Output" name="B9" />
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<port polarity="Output" name="B8" />
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<port polarity="Input" name="NIO_SEL" />
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<port polarity="Input" name="NIO_STB" />
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<port polarity="Input" name="NDEV_SEL" />
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<port polarity="Output" name="NOE" />
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<port polarity="Input" name="RNW" />
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<blockdef name="fdrs">
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<timestamp>2001-3-9T11:23:0</timestamp>
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<line x2="64" y1="-128" y2="-128" x1="0" />
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<line x2="64" y1="-256" y2="-256" x1="0" />
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<line x2="320" y1="-256" y2="-256" x1="384" />
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<line x2="64" y1="-32" y2="-32" x1="0" />
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<line x2="64" y1="-352" y2="-352" x1="0" />
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<rect width="256" x="64" y="-320" height="256" />
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<line x2="192" y1="-64" y2="-32" x1="192" />
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<line x2="64" y1="-32" y2="-32" x1="192" />
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<line x2="80" y1="-112" y2="-128" x1="64" />
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<line x2="64" y1="-128" y2="-144" x1="80" />
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<line x2="192" y1="-320" y2="-352" x1="192" />
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<line x2="64" y1="-352" y2="-352" x1="192" />
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</blockdef>
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<blockdef name="inv">
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<timestamp>2001-3-9T11:23:50</timestamp>
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<line x2="64" y1="-32" y2="-32" x1="0" />
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<line x2="160" y1="-32" y2="-32" x1="224" />
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<line x2="128" y1="-64" y2="-32" x1="64" />
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<line x2="64" y1="-32" y2="0" x1="128" />
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<line x2="64" y1="0" y2="-64" x1="64" />
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<circle r="16" cx="144" cy="-32" />
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</blockdef>
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<blockdef name="vcc">
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<timestamp>2001-3-9T11:23:11</timestamp>
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<line x2="32" y1="-64" y2="-64" x1="96" />
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<line x2="64" y1="0" y2="-32" x1="64" />
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<line x2="64" y1="-32" y2="-64" x1="64" />
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</blockdef>
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<blockdef name="and2">
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<timestamp>2001-5-11T10:41:37</timestamp>
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<line x2="64" y1="-64" y2="-64" x1="0" />
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<line x2="64" y1="-128" y2="-128" x1="0" />
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<line x2="192" y1="-96" y2="-96" x1="256" />
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<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
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<line x2="64" y1="-48" y2="-48" x1="144" />
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<line x2="144" y1="-144" y2="-144" x1="64" />
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<line x2="64" y1="-48" y2="-144" x1="64" />
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</blockdef>
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<blockdef name="and4">
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<timestamp>2001-5-11T10:43:14</timestamp>
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<line x2="64" y1="-112" y2="-112" x1="144" />
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<arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
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<line x2="144" y1="-208" y2="-208" x1="64" />
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<line x2="64" y1="-64" y2="-256" x1="64" />
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<line x2="192" y1="-160" y2="-160" x1="256" />
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<line x2="64" y1="-256" y2="-256" x1="0" />
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<line x2="64" y1="-192" y2="-192" x1="0" />
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<line x2="64" y1="-128" y2="-128" x1="0" />
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<line x2="64" y1="-64" y2="-64" x1="0" />
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</blockdef>
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<blockdef name="nand2">
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<timestamp>2001-3-9T11:23:50</timestamp>
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<line x2="64" y1="-64" y2="-64" x1="0" />
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<line x2="64" y1="-128" y2="-128" x1="0" />
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<line x2="216" y1="-96" y2="-96" x1="256" />
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<circle r="12" cx="204" cy="-96" />
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<line x2="64" y1="-48" y2="-144" x1="64" />
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<line x2="144" y1="-144" y2="-144" x1="64" />
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<line x2="64" y1="-48" y2="-48" x1="144" />
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<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
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</blockdef>
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<blockdef name="or2">
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<timestamp>2000-1-1T10:10:10</timestamp>
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<line x2="64" y1="-64" y2="-64" x1="0" />
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<line x2="64" y1="-128" y2="-128" x1="0" />
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<line x2="192" y1="-96" y2="-96" x1="256" />
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<arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
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<arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
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<line x2="48" y1="-144" y2="-144" x1="112" />
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<arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
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<line x2="48" y1="-48" y2="-48" x1="112" />
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</blockdef>
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<block symbolname="fdrs" name="XLXI_16">
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<blockpin signalname="CLK" name="C" />
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<blockpin signalname="XLXN_14" name="D" />
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<blockpin signalname="XLXN_10" name="R" />
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<blockpin signalname="XLXN_46" name="S" />
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<blockpin signalname="XLXN_47" name="Q" />
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</block>
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<block symbolname="vcc" name="XLXI_17">
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<blockpin signalname="XLXN_14" name="P" />
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</block>
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<block symbolname="and2" name="XLXI_18">
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<blockpin signalname="A10" name="I0" />
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<blockpin signalname="XLXN_38" name="I1" />
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<blockpin signalname="B10" name="O" />
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</block>
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<block symbolname="and2" name="XLXI_19">
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<blockpin signalname="A9" name="I0" />
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<blockpin signalname="XLXN_38" name="I1" />
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<blockpin signalname="B9" name="O" />
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</block>
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<block symbolname="and2" name="XLXI_20">
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<blockpin signalname="A8" name="I0" />
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<blockpin signalname="XLXN_38" name="I1" />
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<blockpin signalname="B8" name="O" />
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</block>
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<block symbolname="inv" name="XLXI_22">
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<blockpin signalname="NIO_SEL" name="I" />
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<blockpin signalname="XLXN_46" name="O" />
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</block>
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<block symbolname="and4" name="XLXI_30">
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<blockpin signalname="A8" name="I0" />
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<blockpin signalname="A9" name="I1" />
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<blockpin signalname="A10" name="I2" />
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<blockpin signalname="XLXN_38" name="I3" />
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<blockpin signalname="XLXN_10" name="O" />
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</block>
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<block symbolname="inv" name="XLXI_31">
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<blockpin signalname="NIO_STB" name="I" />
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<blockpin signalname="XLXN_38" name="O" />
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</block>
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<block symbolname="nand2" name="XLXI_32">
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<blockpin signalname="XLXN_47" name="I0" />
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<blockpin signalname="NDEV_SEL" name="I1" />
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<blockpin signalname="XLXN_55" name="O" />
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</block>
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<block symbolname="inv" name="XLXI_33">
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<blockpin signalname="RNW" name="I" />
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<blockpin signalname="XLXN_53" name="O" />
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</block>
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<block symbolname="or2" name="XLXI_34">
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<blockpin signalname="XLXN_55" name="I0" />
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<blockpin signalname="XLXN_53" name="I1" />
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<blockpin signalname="NOE" name="O" />
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</block>
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</netlist>
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<sheet sheetnum="1" width="3520" height="2720">
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<branch name="A10">
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<wire x2="592" y1="704" y2="704" x1="320" />
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<wire x2="704" y1="704" y2="704" x1="592" />
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<wire x2="592" y1="704" y2="992" x1="592" />
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<wire x2="1088" y1="992" y2="992" x1="592" />
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</branch>
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<branch name="A9">
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<wire x2="528" y1="768" y2="768" x1="320" />
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<wire x2="704" y1="768" y2="768" x1="528" />
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<wire x2="528" y1="768" y2="1136" x1="528" />
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<wire x2="1088" y1="1136" y2="1136" x1="528" />
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</branch>
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<branch name="A8">
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<wire x2="464" y1="832" y2="832" x1="320" />
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<wire x2="704" y1="832" y2="832" x1="464" />
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<wire x2="464" y1="832" y2="1280" x1="464" />
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<wire x2="1088" y1="1280" y2="1280" x1="464" />
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</branch>
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<iomarker fontsize="28" x="320" y="704" name="A10" orien="R180" />
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<iomarker fontsize="28" x="320" y="768" name="A9" orien="R180" />
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<iomarker fontsize="28" x="320" y="832" name="A8" orien="R180" />
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<branch name="CLK">
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<wire x2="912" y1="576" y2="576" x1="320" />
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<wire x2="912" y1="576" y2="640" x1="912" />
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<wire x2="992" y1="640" y2="640" x1="912" />
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</branch>
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<branch name="B10">
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<wire x2="1664" y1="960" y2="960" x1="1344" />
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</branch>
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<branch name="B9">
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<wire x2="1664" y1="1104" y2="1104" x1="1344" />
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</branch>
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<branch name="B8">
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<wire x2="1664" y1="1248" y2="1248" x1="1344" />
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</branch>
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<branch name="NIO_SEL">
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<wire x2="352" y1="368" y2="368" x1="320" />
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</branch>
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<branch name="NIO_STB">
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<wire x2="336" y1="640" y2="640" x1="320" />
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</branch>
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||||||
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<iomarker fontsize="28" x="320" y="368" name="NIO_SEL" orien="R180" />
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|
<iomarker fontsize="28" x="320" y="640" name="NIO_STB" orien="R180" />
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|
<instance x="336" y="672" name="XLXI_31" orien="R0" />
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<branch name="XLXN_38">
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|
<wire x2="672" y1="640" y2="640" x1="560" />
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||||||
|
<wire x2="704" y1="640" y2="640" x1="672" />
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||||||
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<wire x2="672" y1="640" y2="928" x1="672" />
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||||||
|
<wire x2="1088" y1="928" y2="928" x1="672" />
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||||||
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<wire x2="672" y1="928" y2="1072" x1="672" />
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||||||
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<wire x2="1088" y1="1072" y2="1072" x1="672" />
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||||||
|
<wire x2="672" y1="1072" y2="1216" x1="672" />
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||||||
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<wire x2="1088" y1="1216" y2="1216" x1="672" />
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||||||
|
</branch>
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||||||
|
<instance x="704" y="896" name="XLXI_30" orien="R0" />
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||||||
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<branch name="XLXN_10">
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||||||
|
<wire x2="992" y1="736" y2="736" x1="960" />
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||||||
|
</branch>
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||||||
|
<branch name="XLXN_14">
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||||||
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<wire x2="848" y1="496" y2="512" x1="848" />
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||||||
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<wire x2="992" y1="512" y2="512" x1="848" />
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</branch>
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||||||
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<iomarker fontsize="28" x="320" y="576" name="CLK" orien="R180" />
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<instance x="784" y="496" name="XLXI_17" orien="R0" />
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<instance x="352" y="400" name="XLXI_22" orien="R0" />
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<branch name="XLXN_46">
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<wire x2="992" y1="368" y2="368" x1="576" />
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<wire x2="992" y1="368" y2="416" x1="992" />
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</branch>
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<instance x="992" y="768" name="XLXI_16" orien="R0" />
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<instance x="1088" y="1056" name="XLXI_18" orien="R0" />
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<instance x="1088" y="1200" name="XLXI_19" orien="R0" />
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<instance x="1088" y="1344" name="XLXI_20" orien="R0" />
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||||||
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<iomarker fontsize="28" x="1664" y="960" name="B10" orien="R0" />
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<iomarker fontsize="28" x="1664" y="1104" name="B9" orien="R0" />
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||||||
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<iomarker fontsize="28" x="1664" y="1248" name="B8" orien="R0" />
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||||||
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<instance x="1424" y="432" name="XLXI_32" orien="R0" />
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||||||
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<branch name="XLXN_47">
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||||||
|
<wire x2="1392" y1="512" y2="512" x1="1376" />
|
||||||
|
<wire x2="1424" y1="368" y2="368" x1="1392" />
|
||||||
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<wire x2="1392" y1="368" y2="512" x1="1392" />
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||||||
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</branch>
|
||||||
|
<branch name="NDEV_SEL">
|
||||||
|
<wire x2="1424" y1="304" y2="304" x1="320" />
|
||||||
|
</branch>
|
||||||
|
<iomarker fontsize="28" x="320" y="304" name="NDEV_SEL" orien="R180" />
|
||||||
|
<instance x="352" y="272" name="XLXI_33" orien="R0" />
|
||||||
|
<branch name="NOE">
|
||||||
|
<wire x2="2016" y1="272" y2="272" x1="2000" />
|
||||||
|
</branch>
|
||||||
|
<branch name="XLXN_53">
|
||||||
|
<wire x2="1744" y1="240" y2="240" x1="576" />
|
||||||
|
</branch>
|
||||||
|
<branch name="RNW">
|
||||||
|
<wire x2="352" y1="240" y2="240" x1="320" />
|
||||||
|
</branch>
|
||||||
|
<iomarker fontsize="28" x="320" y="240" name="RNW" orien="R180" />
|
||||||
|
<instance x="1744" y="368" name="XLXI_34" orien="R0" />
|
||||||
|
<branch name="XLXN_55">
|
||||||
|
<wire x2="1696" y1="336" y2="336" x1="1680" />
|
||||||
|
<wire x2="1744" y1="304" y2="304" x1="1696" />
|
||||||
|
<wire x2="1696" y1="304" y2="336" x1="1696" />
|
||||||
|
</branch>
|
||||||
|
<iomarker fontsize="28" x="2016" y="272" name="NOE" orien="R0" />
|
||||||
|
</sheet>
|
||||||
|
</drawing>
|
||||||
0
VHDL/AddressDecoder_old.schlog
Normal file
0
VHDL/AddressDecoder_old.schlog
Normal file
172
VHDL/AddressDecoder_old_Test.vhd
Normal file
172
VHDL/AddressDecoder_old_Test.vhd
Normal file
@ -0,0 +1,172 @@
|
|||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- Company:
|
||||||
|
-- Engineer:
|
||||||
|
--
|
||||||
|
-- Create Date: 23:42:22 10/10/2017
|
||||||
|
-- Design Name:
|
||||||
|
-- Module Name: C:/Git/AppleIISd/VHDL/AddressDecoder_Test.vhd
|
||||||
|
-- Project Name: AppleIISd
|
||||||
|
-- Target Device:
|
||||||
|
-- Tool versions:
|
||||||
|
-- Description:
|
||||||
|
--
|
||||||
|
-- VHDL Test Bench Created by ISE for module: AddressDecoder
|
||||||
|
--
|
||||||
|
-- Dependencies:
|
||||||
|
--
|
||||||
|
-- Revision:
|
||||||
|
-- Revision 0.01 - File Created
|
||||||
|
-- Additional Comments:
|
||||||
|
--
|
||||||
|
-- Notes:
|
||||||
|
-- This testbench has been automatically generated using types std_logic and
|
||||||
|
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||||
|
-- that these types always be used for the top-level I/O of a design in order
|
||||||
|
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||||
|
-- simulation model.
|
||||||
|
--------------------------------------------------------------------------------
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.ALL;
|
||||||
|
|
||||||
|
-- Uncomment the following library declaration if using
|
||||||
|
-- arithmetic functions with Signed or Unsigned values
|
||||||
|
--USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
ENTITY AddressDecoder_old_Test IS
|
||||||
|
END AddressDecoder_old_Test;
|
||||||
|
|
||||||
|
ARCHITECTURE behavior OF AddressDecoder_old_Test IS
|
||||||
|
|
||||||
|
-- Component Declaration for the Unit Under Test (UUT)
|
||||||
|
|
||||||
|
COMPONENT AddressDecoder_old
|
||||||
|
PORT(
|
||||||
|
A8 : IN std_logic;
|
||||||
|
A9 : IN std_logic;
|
||||||
|
A10 : IN std_logic;
|
||||||
|
B8 : OUT std_logic;
|
||||||
|
B9 : OUT std_logic;
|
||||||
|
B10 : OUT std_logic;
|
||||||
|
RNW : IN std_logic;
|
||||||
|
CLK : IN std_logic;
|
||||||
|
NDEV_SEL : IN std_logic;
|
||||||
|
NIO_SEL : IN std_logic;
|
||||||
|
NIO_STB : IN std_logic;
|
||||||
|
NOE : OUT std_logic
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
|
||||||
|
--Inputs
|
||||||
|
signal A : std_logic_vector(10 downto 8) := "101";
|
||||||
|
signal RNW : std_logic := '1';
|
||||||
|
signal NDEV_SEL : std_logic := '1';
|
||||||
|
signal NIO_SEL : std_logic := '1';
|
||||||
|
signal NIO_STB : std_logic := '1';
|
||||||
|
signal NRESET : std_logic := '1';
|
||||||
|
signal CLK : std_logic := '0';
|
||||||
|
signal PHI0 : std_logic := '1';
|
||||||
|
|
||||||
|
--Outputs
|
||||||
|
signal B : std_logic_vector(10 downto 8);
|
||||||
|
signal DATA_EN : std_logic;
|
||||||
|
signal NG : std_logic;
|
||||||
|
signal NOE : std_logic;
|
||||||
|
|
||||||
|
-- Clock period definitions
|
||||||
|
constant CLK_period : time := 142 ns;
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
|
||||||
|
-- Instantiate the Unit Under Test (UUT)
|
||||||
|
uut: AddressDecoder_old PORT MAP (
|
||||||
|
A8 => A(8),
|
||||||
|
A9 => A(9),
|
||||||
|
A10 => A(10),
|
||||||
|
B8 => B(8),
|
||||||
|
B9 => B(9),
|
||||||
|
B10 => B(10),
|
||||||
|
RNW => RNW,
|
||||||
|
CLK => CLK,
|
||||||
|
NDEV_SEL => NDEV_SEL,
|
||||||
|
NIO_SEL => NIO_SEL,
|
||||||
|
NIO_STB => NIO_STB,
|
||||||
|
NOE => NOE
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Clock process definitions
|
||||||
|
CLK_process :process
|
||||||
|
begin
|
||||||
|
CLK <= '0';
|
||||||
|
wait for CLK_period/2;
|
||||||
|
CLK <= '1';
|
||||||
|
wait for CLK_period/2;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
PHI0_process :process(CLK)
|
||||||
|
variable counter : integer range 0 to 7;
|
||||||
|
begin
|
||||||
|
if rising_edge(CLK) or falling_edge(CLK) then
|
||||||
|
counter := counter + 1;
|
||||||
|
if counter = 7 then
|
||||||
|
PHI0 <= not PHI0;
|
||||||
|
counter := 0;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- Stimulus process
|
||||||
|
stim_proc: process
|
||||||
|
begin
|
||||||
|
-- hold reset state.
|
||||||
|
wait for CLK_period * 10;
|
||||||
|
NRESET <= '0';
|
||||||
|
wait for CLK_period * 20;
|
||||||
|
NRESET <= '1';
|
||||||
|
wait for CLK_period * 10;
|
||||||
|
|
||||||
|
-- insert stimulus here
|
||||||
|
-- CPLD access
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
NDEV_SEL <= '0';
|
||||||
|
wait until falling_edge(PHI0);
|
||||||
|
NDEV_SEL <= '1';
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
-- CnXX access
|
||||||
|
NIO_SEL <= '0';
|
||||||
|
wait until falling_edge(PHI0);
|
||||||
|
NIO_SEL <= '1';
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
-- C8xx access, selected
|
||||||
|
NIO_STB <= '0';
|
||||||
|
wait until falling_edge(PHI0);
|
||||||
|
NIO_STB <= '1';
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
-- CPLD access
|
||||||
|
NDEV_SEL <= '0';
|
||||||
|
wait until falling_edge(PHI0);
|
||||||
|
NDEV_SEL <= '1';
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
-- CFFF access
|
||||||
|
A <= "111";
|
||||||
|
NIO_STB <= '0';
|
||||||
|
wait until falling_edge(PHI0);
|
||||||
|
A <= "000";
|
||||||
|
NIO_STB <= '1';
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
-- C8xx access, unselected
|
||||||
|
NIO_STB <= '0';
|
||||||
|
wait until falling_edge(PHI0);
|
||||||
|
NIO_STB <= '1';
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
END;
|
||||||
1092
VHDL/AppleIISd.jed
1092
VHDL/AppleIISd.jed
File diff suppressed because it is too large
Load Diff
@ -16,28 +16,35 @@
|
|||||||
|
|
||||||
<files>
|
<files>
|
||||||
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
|
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
|
||||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||||
</file>
|
</file>
|
||||||
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
|
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
|
||||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||||
</file>
|
</file>
|
||||||
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
|
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
|
||||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||||
</file>
|
</file>
|
||||||
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
|
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
|
||||||
</file>
|
</file>
|
||||||
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
|
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
|
||||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||||
</file>
|
</file>
|
||||||
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
|
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
|
||||||
</file>
|
</file>
|
||||||
|
<file xil_pn:name="AddressDecoder_old.sch" xil_pn:type="FILE_SCHEMATIC">
|
||||||
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||||
|
</file>
|
||||||
|
<file xil_pn:name="AddressDecoder_old_Test.vhd" xil_pn:type="FILE_VHDL">
|
||||||
|
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||||
|
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="52"/>
|
||||||
|
</file>
|
||||||
</files>
|
</files>
|
||||||
|
|
||||||
<properties>
|
<properties>
|
||||||
@ -152,8 +159,8 @@
|
|||||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test" xil_pn:valueState="non-default"/>
|
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="non-default"/>
|
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||||
@ -163,7 +170,7 @@
|
|||||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="default"/>
|
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||||
@ -198,7 +205,7 @@
|
|||||||
<!-- -->
|
<!-- -->
|
||||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||||
<!-- -->
|
<!-- -->
|
||||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
|
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
|
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
|
||||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
|
||||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||||
|
|||||||
@ -265,6 +265,38 @@ BEGIN
|
|||||||
ADD_LOW <= (others => 'U');
|
ADD_LOW <= (others => 'U');
|
||||||
ADD_HIGH <= (others => 'U');
|
ADD_HIGH <= (others => 'U');
|
||||||
|
|
||||||
|
-- read eprom low
|
||||||
|
wait until falling_edge(PHI0);
|
||||||
|
wait for ADD_valid;
|
||||||
|
ADD_LOW <= (others => '0');
|
||||||
|
ADD_HIGH <= "101";
|
||||||
|
RNW <= '1';
|
||||||
|
DATA <= (others => 'U');
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
NIO_SEL <= '0';
|
||||||
|
DATA <= (others => 'Z');
|
||||||
|
wait until falling_edge(PHI0);
|
||||||
|
NIO_SEL <= '1';
|
||||||
|
wait for ADD_hold;
|
||||||
|
ADD_LOW <= (others => 'U');
|
||||||
|
ADD_HIGH <= (others => 'U');
|
||||||
|
|
||||||
|
-- read eprom high
|
||||||
|
wait until falling_edge(PHI0);
|
||||||
|
wait for ADD_valid;
|
||||||
|
ADD_LOW <= (others => '0');
|
||||||
|
ADD_HIGH <= "101";
|
||||||
|
RNW <= '1';
|
||||||
|
DATA <= (others => 'U');
|
||||||
|
wait until rising_edge(PHI0);
|
||||||
|
NIO_STB <= '0';
|
||||||
|
DATA <= (others => 'Z');
|
||||||
|
wait until falling_edge(PHI0);
|
||||||
|
NIO_STB <= '1';
|
||||||
|
wait for ADD_hold;
|
||||||
|
ADD_LOW <= (others => 'U');
|
||||||
|
ADD_HIGH <= (others => 'U');
|
||||||
|
|
||||||
-- read $CFFF
|
-- read $CFFF
|
||||||
wait until falling_edge(PHI0);
|
wait until falling_edge(PHI0);
|
||||||
wait for ADD_valid;
|
wait for ADD_valid;
|
||||||
@ -289,15 +321,14 @@ BEGIN
|
|||||||
RNW <= '1';
|
RNW <= '1';
|
||||||
DATA <= (others => 'U');
|
DATA <= (others => 'U');
|
||||||
wait until rising_edge(PHI0);
|
wait until rising_edge(PHI0);
|
||||||
NIO_SEL <= '0';
|
NIO_STB <= '0';
|
||||||
DATA <= (others => 'Z');
|
DATA <= (others => 'Z');
|
||||||
wait until falling_edge(PHI0);
|
wait until falling_edge(PHI0);
|
||||||
NIO_SEL <= '1';
|
NIO_STB <= '1';
|
||||||
wait for ADD_hold;
|
wait for ADD_hold;
|
||||||
ADD_LOW <= (others => 'U');
|
ADD_LOW <= (others => 'U');
|
||||||
ADD_HIGH <= (others => 'U');
|
ADD_HIGH <= (others => 'U');
|
||||||
|
|
||||||
|
|
||||||
wait;
|
wait;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
|
|||||||
0
VHDL/sch2HdlBatchFile
Normal file
0
VHDL/sch2HdlBatchFile
Normal file
Loading…
Reference in New Issue
Block a user