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NWE signal added, not tested
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@ -31,18 +31,19 @@ use IEEE.STD_LOGIC_1164.ALL;
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entity AddressDecoder is
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Port ( A : in std_logic_vector (11 downto 8);
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B : out std_logic_vector (10 downto 8); -- to EPROM
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B : out std_logic_vector (10 downto 8); -- to EEPROM
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CLK : in std_logic;
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PHI0 : in std_logic;
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RNW : in std_logic;
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NDEV_SEL : in std_logic; -- $C0n0 - $C0nF
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NIO_SEL : in std_logic; -- $Cs00 - $CsFF
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NIO_STB : in std_logic; -- $C800 - $CFFF
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NDEV_SEL : in std_logic; -- $C0n0 - $C0nF, CPLD registers
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NIO_SEL : in std_logic; -- $Cs00 - $CsFF, EEPROM bank 0
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NIO_STB : in std_logic; -- $C800 - $CFFF, EEPROM banks 1 to 7
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NRESET : in std_logic;
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DATA_EN : out std_logic; -- to CPLD
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NG : out std_logic; -- to bus transceiver
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NOE : out std_logic;
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LED : out std_logic); -- to EPROM
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NOE : out std_logic; -- to EEPROM
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NWE : out std_logic; -- to EEPROM
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LED : out std_logic);
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end AddressDecoder;
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architecture Behavioral of AddressDecoder is
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@ -81,6 +82,9 @@ begin
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NOE <= not RNW
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or not NDEV_SEL
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or (not NIO_STB and ncs);
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NWE <= RNW
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or not NDEV_SEL
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or (not NIO_STB and ncs);
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cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;
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@ -53,6 +53,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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DATA_EN : OUT std_logic;
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NG : OUT std_logic;
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NOE : OUT std_logic;
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NWE : OUT std_logic;
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LED : OUT std_logic
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);
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END COMPONENT;
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@ -73,6 +74,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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signal DATA_EN : std_logic;
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signal NG : std_logic;
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signal NOE : std_logic;
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signal NWE : std_logic;
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signal LED : std_logic;
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-- Clock period definitions
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@ -94,6 +96,7 @@ BEGIN
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DATA_EN => DATA_EN,
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NG => NG,
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NOE => NOE,
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NWE => NWE,
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LED => LED
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);
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@ -153,7 +156,16 @@ BEGIN
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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-- C8xx write access, selected
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RNW <= '0'
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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-- C9xx access, selected
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RNW <= '1';
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A <= "1001"; -- must become "010"
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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@ -161,7 +173,16 @@ BEGIN
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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-- C9xx access write, selected
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RNW <= '0';
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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-- CPLD access
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RNW <= '1';
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A <= "0101"; -- must become "000"
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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@ -28,6 +28,7 @@ NET "NG" LOC = "P12" ;
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NET "NIO_SEL" LOC = "P14" ;
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NET "NIO_STB" LOC = "P42" ;
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NET "NOE" LOC = "P25" ;
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NET "NWE" LOC = "P5" ;
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NET "PHI0" LOC = "P8" ;
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NET "NRESET" LOC = "P20" ;
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NET "RNW" LOC = "P1" ;
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@ -43,6 +43,7 @@ Port (
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NIO_SEL : in std_logic;
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NIO_STB : in std_logic;
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NOE : out std_logic;
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NWE : out std_logic;
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PHI0 : in std_logic;
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NRESET : in std_logic;
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RNW : in std_logic;
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@ -104,10 +105,12 @@ Port (
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DATA_EN : out std_logic;
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NG : out std_logic;
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NOE : out std_logic;
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NWE : out std_logic;
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LED : out std_logic
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);
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end component;
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begin
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spi: SpiController port map(
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data_in => data_in,
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@ -139,6 +142,7 @@ begin
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NRESET => NRESET,
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DATA_EN => data_en,
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NOE => NOE,
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NWE => NWE,
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NG => NG
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--LED => LED
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);
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