diff --git a/.untf b/.untf deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/SPI6502B.cel b/VHDL/SPI6502B.cel deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/SPI6502B.lfp b/VHDL/SPI6502B.lfp deleted file mode 100644 index 96eff7a..0000000 --- a/VHDL/SPI6502B.lfp +++ /dev/null @@ -1,27 +0,0 @@ -# begin LFP file C:\sources\AppleIISd\SPI6502B.lfp -designfile spi6502b.ngd -IO_GROUP "spi_Nsel" ; -IO_GROUP "spi_miso" ; -IO_GROUP "spi_int" ; -IO_GROUP "cpu_d" ; -IO_GROUP "cpu_a" ; -NET "spi_sclk" COLOR=6 ; -NET "spi_mosi" COLOR=6 ; -NET "Ncs2" COLOR=6 ; -NET "extclk" COLOR=6 ; -NET "cpu_rnw" COLOR=6 ; -NET "cpu_Nres" COLOR=6 ; -NET "cpu_Nphi2" COLOR=6 ; -NET "cpu_Nirq" COLOR=6 ; -NET "cpu_d<7>" COLOR=6 IO_GROUP="cpu_d" ; -NET "cpu_d<6>" COLOR=6 IO_GROUP="cpu_d" ; -NET "cpu_d<5>" COLOR=6 IO_GROUP="cpu_d" ; -NET "cpu_d<4>" COLOR=6 IO_GROUP="cpu_d" ; -NET "cpu_d<3>" COLOR=6 IO_GROUP="cpu_d" ; -NET "cpu_d<2>" COLOR=6 IO_GROUP="cpu_d" ; -NET "cpu_d<1>" COLOR=6 IO_GROUP="cpu_d" ; -NET "cpu_d<0>" COLOR=6 IO_GROUP="cpu_d" ; -NET "cpu_a<1>" COLOR=6 IO_GROUP="cpu_a" ; -NET "cpu_a<0>" COLOR=6 IO_GROUP="cpu_a" ; -INST "spi_mosi_OBUFE" COLOR=7 ; -INST "cpu_Nirq_OBUFE" COLOR=8 ; diff --git a/VHDL/SPI6502B.ucf.untf b/VHDL/SPI6502B.ucf.untf deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/_pace.ucf b/VHDL/_pace.ucf deleted file mode 100644 index 9d5d775..0000000 --- a/VHDL/_pace.ucf +++ /dev/null @@ -1,42 +0,0 @@ -#net "diag" loc="P29"; - -#PACE: Start of Constraints generated by PACE - -#PACE: Start of PACE I/O Pin Assignments -NET "A10" LOC = "P38" ; -NET "A10_B" LOC = "P25" ; -NET "A8" LOC = "P36" ; -NET "A8_B" LOC = "P27" ; -NET "A9" LOC = "P37" ; -NET "A9_B" LOC = "P26" ; -NET "cpu_a<0>" LOC = "P22" ; -NET "cpu_a<1>" LOC = "P24" ; -NET "cpu_d<0>" LOC = "P2" ; -NET "cpu_d<1>" LOC = "P3" ; -NET "cpu_d<2>" LOC = "P4" ; -NET "cpu_d<3>" LOC = "P8" ; -NET "cpu_d<4>" LOC = "P9" ; -NET "cpu_d<5>" LOC = "P11" ; -NET "cpu_d<6>" LOC = "P12" ; -NET "cpu_d<7>" LOC = "P13" ; -NET "cpu_Nirq" LOC = "P14" ; -NET "cpu_Nphi2" LOC = "P5" ; -NET "cpu_Nres" LOC = "P19" ; -NET "cpu_rnw" LOC = "P7" ; -NET "extclk" LOC = "P6" ; -NET "IO_SEL" LOC = "P40" ; -NET "IO_STB" LOC = "P43" ; -NET "led" LOC = "P29" ; -NET "Ncs2" LOC = "P18" ; -NET "OE" LOC = "P1" ; -NET "spi_int" LOC = "P42" ; -NET "spi_miso" LOC = "P44" ; -NET "spi_mosi" LOC = "P35" ; -NET "spi_Nsel" LOC = "P28" ; -NET "spi_sclk" LOC = "P34" ; - -#PACE: Start of PACE Area Constraints - -#PACE: Start of PACE Prohibit Constraints - -#PACE: End of Constraints generated by PACE diff --git a/address_decoder.sch b/VHDL/address_decoder.sch similarity index 100% rename from address_decoder.sch rename to VHDL/address_decoder.sch diff --git a/VHDL/spi65.cdf b/VHDL/spi65.cdf deleted file mode 100644 index d3ad07b..0000000 --- a/VHDL/spi65.cdf +++ /dev/null @@ -1,16 +0,0 @@ -JedecChain; -FileRevision(JESDxxA); -/* NoviceMode */ -/* Active Mode BS */ -/* Mode BS */ -/* Cable PlatformCableUSB usb21 6000000 */ - P ActionCode(Cfg) - Device - PartName(xc9572xl) - File("C:\sources\spi65\spi6502b.jed") - ; -/* Mode SS */ -/* Mode SM */ -/* Mode BSFILE */ -/* Mode HW140 */ -ChainEnd; diff --git a/VHDL/spi65.dhp b/VHDL/spi65.dhp deleted file mode 100644 index 1cadedc..0000000 --- a/VHDL/spi65.dhp +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.2e -$91x4>763-Xnzd}foo8#5+72(-k0=989971304g<9=<=5;=841c851011?9<;=o415567623:?k0=99:410;13g<9=3:94>855c851?381>?95o415;74=31>;k0=97626711=g<9=32>:;=58:8EweoFhgnn6O}ciMan`es{01I`bmdTxrf=>EHEDC_XHJ8;BPFEQCC02Ida}Gasuc8Akrn|pCeyo4Eovjp|Hfelh0JdbjDdrfjau?3OcgiCobec9EmicHjcFby64FhnfTdroi2Lb`h]jrwgpe>OikeoiBle8:KmwqHfel<0@BOKEE:8Hdh`}hmnn6Bfbscq}Kgjm8;0@dl}as{Ppdrbeld55Berqbc`ue3YkhglijN`of=>Vfzzo_e`k;;Qcqp<=V}hfbjdk}f:QSM337:K;%=#xgd018WUO1=98I=#?!vif.5506;2Y[E;;?2C3-5+pol$;;;<=4SQK5154E9';%zej"10627>UWA??;>O?!1/tk`(76=890_]G9510A5+7)~an&=?<>3:QSM337:K;%=#xgd,31745<[YC=9=;>2:QSM337:K;%=#xgd,6157=TX@<>.0,ula+3;880_]G9510A5+7)~an&4??=;RRJ2065J8$:"{fk-915?Vcu~lyi7Yk|tWg`pjttj2^d|KgceMkpp==Rf`~Em`kk;TqfWqgsmdoex~?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED84Xe`\Ma773QnfS@oeosTfvvohf8:0TicPMhllvScu{`ee;6okd^ffgg=flmUoin#>76d8eabumzyThhm`ddp27>gcl{oxRjjcnffv(7?9890mij}erq\``ehllx&=5<>3:cg`wct{Vnnobjjr/hk`417:cg`wct{Vnnobjjr/hk`(7?8:1j`ao4bdjbrliuieo0nhfnvhmqei+69;o0nhfnvhmqei+6:9o0nhfnvhmqei+6:1o0nhfnvhmqei+6>1o0nhfnvhmqei+6??n0nhfnvhmqei+38m1iieoyinpbh(2?k2hndlxfosco)=b65`8mkek}mo&=:udgyoGeckAul48wlkwdl20}g9510ag>uwa??;>o#>10a8wuo1=98i!:m4sqk5154e%8<=b,64e>uwa??;>o#8b:qsm337:k'3;h5|te]okbodW8;=8<<4suf\hjankVediaee58qvc*993<7x}j-0333>stm$;:;:5zsd/25=1<}zo&=?;8;tqf)441?2xi ?9569vw`+6>?=0y~k"1614?pub%8=?:6{|e,142>stm$93:6{|e,662>stm$>=96{|e,76?pub%?<0y~k"8448qvc*0?wKL};l;AB{210;47>4<6;:k;;?4=a863k5b281e?k4=;%1g>6e:010e5152;k28<5\1c850?7=9:9j<:<52`;76>Ua2?>1=7?<3`246?4flk<0_454i9=96?okf`9Pb?03280:?>o?7381e`0f3Z;i6;:51;307d6di38h>8o4Sg850?7=9:9jU6j332c3gg<69o8<7^h56582>454i9ii6<=n0e`95addm2Ym6;:51;307d6cj3;nm=;4S0`921<62898m<<>:3c17g=Tn332c264<5i;>:7^?m:7695?74;h;n57<;b438Wc<1<3;1=>=n1d;961c212Y:n78;:08276g6mh0:;=9i;Rd921<62898m=0:6<=7b7mh1Xj78;:08276e1i>09h87:;R3a>32=93;8?n9?a;060d4<[o0=87?5121`35g=:<>i86]>b;47>4<6;:i<=0:6<=73c181X=o494;39565d?9k1>::i2:Qe>32=93;8?n9?a;0424c<[8h1:94>:010g2b62;k;=l5\f;47>4<6;:ih183h=7B=6:19L53<73L9h7>51;394~U68332a4`4<5i9;j7c?l:09a6`<7290>6=ua6282?kc=92E8;7>4$0d94>"6=38?7)?8:19'67<73-8:6l5@1583?J7?291D:?4>{|`6f?6=83:1vs@1d83?xd013:1<7>50zl57?463go1==>4O2594>"6l3?=7)4}zG831=vsrb6c94?6=83:pb;=5239ma?7782E8;7>4$0f913=#:90<<6*=3;6;?J32291D:?4>{|M2=?7|uth=m7>50;294~h1;39;7ck52:M03?6<,891:85@d;28K34=9rwD=44>{|a0`<7290:6=ua62866>hb2=1D?:4?;%a90<=#;10;7)?<:778K47=82E:>7>4O4694>I1:3;pqB8>:0y~f17=83:1<7>tn719=1=im320C>950:&2e?273-9j69<4O4694>I2;3:0C;<51zL24<6stwvqpxI4783>4<629qX==494;39565d?m;1>l>>b:l2g?752;2xj35=92dn6<5@3683?!7a291/=84;5:&23?6<,;81<6*=1;`8K42=82E:47>4O7095~{e<:0;6=4?:1ym26<63go1>6A<7;28 45=<;1Dh7>4O7095~{zj=>1<7>50;2xj35=92dn695@3683?!e=<;1/?54?;%30>142;28K02=82E=>7?t}N42>4}zutwvqMNL{4a922>fkoimqMNM{1CDU}H:00996A=c;0f?J4d2:90C>?5249L77<5i2E8:7<:;N14>7g85@3b81e>I3:38>7B:<:2f8K1>=:<1D84496sO@ \ No newline at end of file diff --git a/VHDL/spi6502b._hrpt b/VHDL/spi6502b._hrpt deleted file mode 100644 index 804880a..0000000 --- a/VHDL/spi6502b._hrpt +++ /dev/null @@ -1 +0,0 @@ -Up-to-date diff --git a/VHDL/spi6502b.gyd b/VHDL/spi6502b.gyd deleted file mode 100644 index bccfda3..0000000 --- a/VHDL/spi6502b.gyd +++ /dev/null @@ -1,61 +0,0 @@ -Pin Freeze File: version G.38 - -9572XL44PC XC9572XL-10-PC44 -Ncs2 S:PIN18 -a10 S:PIN38 -a8 S:PIN36 -a9 S:PIN37 -cpu_Nphi2 S:PIN5 -cpu_Nres S:PIN19 -cpu_a<0> S:PIN22 -cpu_a<1> S:PIN24 -cpu_rnw S:PIN7 -extclk S:PIN6 -nio_sel S:PIN40 -nio_stb S:PIN43 -spi_int S:PIN42 -spi_miso S:PIN44 -b10 S:PIN27 -b8 S:PIN25 -b9 S:PIN26 -cpu_Nirq S:PIN39 -cpu_d<0> S:PIN2 -cpu_d<1> S:PIN3 -cpu_d<2> S:PIN4 -cpu_d<3> S:PIN8 -cpu_d<4> S:PIN9 -cpu_d<5> S:PIN11 -cpu_d<6> S:PIN12 -cpu_d<7> S:PIN13 -spi_mosi S:PIN35 -spi_sclk S:PIN34 -led S:PIN29 -ng S:PIN20 -noe S:PIN14 -spi_Nsel S:PIN28 - - -;The remaining section of the .gyd file is for documentation purposes only. -;It shows where your internal equations were placed in the last successful fit. - -PARTITION FB1_1 spidataout<3> spidataout<2> spidataout<1> spidataout<0> - int_dout<0> int_dout<1> tmo int_dout<2> - slaveinten frx ece divisor<2> - divisor<1> divisor<0> int_dout<3> cpol - int_dout<4> cpha -PARTITION FB2_1 EXP6_ int_mosi shifting2 tc - shiftcnt<0> $OpTx$INV$24__$INT spidatain<7> spidatain<6> - cpu_Nirq_OBUFE spidatain<5> spidatain<4> spidatain<3> - spidatain<2> -PARTITION FB2_18 start_shifting/start_shifting_RSTF__$INT -PARTITION FB3_2 int_dout<5> -PARTITION FB3_5 int_dout<6> -PARTITION FB3_8 int_dout<7> noe_OBUF -PARTITION FB3_15 ng_OBUF -PARTITION FB3_17 add_dec/XLXN_11 cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST -PARTITION FB4_1 shiftdone b8_OBUF start_shifting spidataout<7> - b9_OBUF spidataout<6> spidataout<5> b10_OBUF - spidataout<4> spidatain<1> slavesel spidatain<0> - shiftcnt<3> led_OBUF shiftcnt<2> shiftcnt<1> - int_sclk ier - diff --git a/VHDL/spi6502b.imp b/VHDL/spi6502b.imp deleted file mode 100644 index 804880a..0000000 --- a/VHDL/spi6502b.imp +++ /dev/null @@ -1 +0,0 @@ -Up-to-date diff --git a/VHDL/spi6502b.jed b/VHDL/spi6502b.jed deleted file mode 100644 index 8252845..0000000 --- a/VHDL/spi6502b.jed +++ /dev/null @@ -1,1666 +0,0 @@ -Programmer Jedec Bit Map -Date Extracted: Thu May 11 02:09:28 2017 - -QF46656* -QP44* -QV0* -F0* -X0* -J0 0* -N DEVICE XC9572XL-10-PC44* -N PPMAP 11 1* -N PPMAP 29 11* -N PPMAP 31 12* -N PPMAP 33 13* -N PPMAP 38 14* -N PPMAP 46 18* -N PPMAP 49 19* -N PPMAP 12 2* -N PPMAP 50 20* -N PPMAP 52 22* -N PPMAP 59 24* -N PPMAP 62 25* -N PPMAP 63 26* -N PPMAP 65 27* -N PPMAP 68 28* -N PPMAP 72 29* -N PPMAP 13 3* -N PPMAP 82 33* -N PPMAP 83 34* -N PPMAP 87 35* -N PPMAP 88 36* -N PPMAP 89 37* -N PPMAP 90 38* -N PPMAP 92 39* -N PPMAP 15 4* -N PPMAP 3 40* -N PPMAP 7 42* -N PPMAP 9 43* -N PPMAP 10 44* -N PPMAP 20 5* -N PPMAP 21 6* -N PPMAP 24 7* -N PPMAP 26 8* -N PPMAP 27 9* -L0000000 00000000 10000000 00000000 00000000* -L0000032 10000000 10000000 00000000 00000000* -L0000064 00000000 10000000 00000000 00000000* -L0000096 00000000 10000000 00000000 00000000* -L0000128 00000000 10000000 00000000 00000100* -L0000160 00000000 00000000 00000000 00000000* -L0000192 00000000 00000000 00000000 00000100* -L0000224 00000000 10000000 00000000 00000000* -L0000256 00000000 00000000 00000000 00000000* -L0000288 000000 100000 000000 000000* -L0000312 000000 000001 000000 000000* -L0000336 000000 100000 000000 000000* -L0000360 000000 100000 000000 000000* -L0000384 000000 000000 000000 000000* -L0000408 000000 000000 000000 000000* -L0000432 00000000 00000000 00000000 00000000* -L0000464 00000000 00000000 00000000 00000000* -L0000496 10000000 00000000 00000000 00000000* -L0000528 00000000 01000000 00000000 00000000* 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00000000 11100000 00000000* -L0046448 01100100 00000000 11100000 00000000* -L0046480 01100100 00000000 10000000 00000000* -L0046512 010001 000000 000000 000000* -L0046536 010010 000000 000000 000000* -L0046560 010010 000000 000000 000000* -L0046584 010010 000000 000000 000000* -L0046608 010000 000000 000000 000000* -L0046632 000000 000000 000000 000000* -C9205* -18E9 diff --git a/VHDL/spi6502b.mfd b/VHDL/spi6502b.mfd deleted file mode 100644 index a1c2f4f..0000000 --- a/VHDL/spi6502b.mfd +++ /dev/null @@ -1,750 +0,0 @@ -MDF Database: version 1.0 -MDF_INFO | spi6502b | XC9572XL-10-PC44 -MACROCELL | 1 | 1 | int_mosi -ATTRIBUTES | 8652706 | 0 -INPUTS | 12 | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | shiftdone | spidataout<4> | shifting2 | spidataout<0> | EXP6_.EXP | shifting2.EXP | $OpTx$INV$24__$INT | cpu_Nres | tmo -INPUTMC | 11 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 0 | 3 | 8 | 1 | 2 | 0 | 3 | 1 | 0 | 1 | 2 | 1 | 5 | 0 | 6 -INPUTP | 1 | 49 -IMPORTS | 2 | 1 | 0 | 1 | 2 -EQ | 21 | - !spi_mosi.D = shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & - !shiftdone & !spidataout<0> & shifting2 - # !shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & - !shiftdone & !spidataout<4> & shifting2 -;Imported pterms FB2_1 - # shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & - !shiftdone & !spidataout<2> & shifting2 - # shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & - !shiftdone & !spidataout<3> & shifting2 - # !shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & - !shiftdone & !spidataout<5> & shifting2 - # !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & - !shiftdone & !spidataout<6> & shifting2 - # !shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & - !shiftdone & !spidataout<7> & shifting2 -;Imported pterms FB2_3 - # shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & - !shiftdone & !spidataout<1> & shifting2; - spi_mosi.CLK = !$OpTx$INV$24__$INT; - spi_mosi.AP = !cpu_Nres; - spi_mosi.OE = !tmo; - -MACROCELL | 3 | 10 | slavesel -ATTRIBUTES | 4588514 | 0 -OUTPUTMC | 4 | 3 | 10 | 3 | 11 | 0 | 4 | 3 | 13 -INPUTS | 7 | spi_Nsel | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 3 | 10 -INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24 -EQ | 5 | - spi_Nsel.T = spi_Nsel & cpu_a<1> & cpu_a<0> & !cpu_d<0>.PIN - # !spi_Nsel & cpu_a<1> & cpu_a<0> & cpu_d<0>.PIN; - spi_Nsel.CLK = Ncs2; - spi_Nsel.AP = !cpu_Nres; - spi_Nsel.CE = !cpu_rnw; - -MACROCELL | 0 | 15 | cpol -ATTRIBUTES | 4326256 | 0 -OUTPUTMC | 3 | 0 | 15 | 3 | 16 | 0 | 5 -INPUTS | 7 | cpol | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 15 -INPUTP | 6 | 59 | 52 | 13 | 46 | 49 | 24 -EQ | 5 | - cpol.T = cpol & !cpu_a<1> & cpu_a<0> & !cpu_d<1>.PIN - # !cpol & !cpu_a<1> & cpu_a<0> & cpu_d<1>.PIN; - cpol.CLK = Ncs2; - cpol.AR = !cpu_Nres; - cpol.CE = !cpu_rnw; - -MACROCELL | 0 | 10 | ece -ATTRIBUTES | 4326256 | 0 -OUTPUTMC | 3 | 0 | 10 | 0 | 7 | 1 | 5 -INPUTS | 7 | ece | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 10 -INPUTP | 6 | 59 | 52 | 15 | 46 | 49 | 24 -EQ | 5 | - ece.T = ece & !cpu_a<1> & cpu_a<0> & !cpu_d<2>.PIN - # !ece & !cpu_a<1> & cpu_a<0> & cpu_d<2>.PIN; - ece.CLK = Ncs2; - ece.AR = !cpu_Nres; - ece.CE = !cpu_rnw; - -MACROCELL | 0 | 17 | cpha -ATTRIBUTES | 4326256 | 0 -OUTPUTMC | 4 | 0 | 17 | 3 | 16 | 0 | 4 | 3 | 15 -INPUTS | 7 | cpha | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 17 -INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24 -EQ | 5 | - cpha.T = cpha & !cpu_a<1> & cpu_a<0> & !cpu_d<0>.PIN - # !cpha & !cpu_a<1> & cpu_a<0> & cpu_d<0>.PIN; - cpha.CLK = Ncs2; - cpha.AR = !cpu_Nres; - cpha.CE = !cpu_rnw; - -MACROCELL | 0 | 9 | frx -ATTRIBUTES | 4326256 | 0 -OUTPUTMC | 3 | 0 | 9 | 3 | 2 | 0 | 16 -INPUTS | 7 | frx | cpu_a<1> | cpu_a<0> | cpu_d<4>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 9 -INPUTP | 6 | 59 | 52 | 27 | 46 | 49 | 24 -EQ | 5 | - frx.T = frx & !cpu_a<1> & cpu_a<0> & !cpu_d<4>.PIN - # !frx & !cpu_a<1> & cpu_a<0> & cpu_d<4>.PIN; - frx.CLK = Ncs2; - frx.AR = !cpu_Nres; - frx.CE = !cpu_rnw; - -MACROCELL | 3 | 17 | ier -ATTRIBUTES | 4326256 | 0 -OUTPUTMC | 3 | 3 | 17 | 2 | 4 | 2 | 17 -INPUTS | 7 | ier | cpu_a<1> | cpu_a<0> | cpu_d<6>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 3 | 17 -INPUTP | 6 | 59 | 52 | 31 | 46 | 49 | 24 -EQ | 5 | - ier.T = ier & !cpu_a<1> & cpu_a<0> & !cpu_d<6>.PIN - # !ier & !cpu_a<1> & cpu_a<0> & cpu_d<6>.PIN; - ier.CLK = Ncs2; - ier.AR = !cpu_Nres; - ier.CE = !cpu_rnw; - -MACROCELL | 0 | 8 | slaveinten -ATTRIBUTES | 4326256 | 0 -OUTPUTMC | 3 | 0 | 8 | 0 | 16 | 2 | 17 -INPUTS | 7 | slaveinten | cpu_a<1> | cpu_a<0> | cpu_d<4>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 8 -INPUTP | 6 | 59 | 52 | 27 | 46 | 49 | 24 -EQ | 5 | - slaveinten.T = slaveinten & cpu_a<1> & cpu_a<0> & !cpu_d<4>.PIN - # !slaveinten & cpu_a<1> & cpu_a<0> & cpu_d<4>.PIN; - slaveinten.CLK = Ncs2; - slaveinten.AR = !cpu_Nres; - slaveinten.CE = !cpu_rnw; - -MACROCELL | 0 | 6 | tmo -ATTRIBUTES | 4326256 | 0 -OUTPUTMC | 3 | 1 | 1 | 0 | 6 | 0 | 14 -INPUTS | 7 | tmo | cpu_a<1> | cpu_a<0> | cpu_d<3>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 6 -INPUTP | 6 | 59 | 52 | 26 | 46 | 49 | 24 -EQ | 5 | - tmo.T = tmo & !cpu_a<1> & cpu_a<0> & !cpu_d<3>.PIN - # !tmo & !cpu_a<1> & cpu_a<0> & cpu_d<3>.PIN; - tmo.CLK = Ncs2; - tmo.AR = !cpu_Nres; - tmo.CE = !cpu_rnw; - -MACROCELL | 0 | 13 | divisor<0> -ATTRIBUTES | 4326256 | 0 -OUTPUTMC | 2 | 0 | 13 | 0 | 4 -INPUTS | 7 | divisor<0> | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 13 -INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24 -EQ | 5 | - divisor<0>.T = divisor<0> & cpu_a<1> & !cpu_a<0> & !cpu_d<0>.PIN - # !divisor<0> & cpu_a<1> & !cpu_a<0> & cpu_d<0>.PIN; - divisor<0>.CLK = Ncs2; - divisor<0>.AR = !cpu_Nres; - divisor<0>.CE = !cpu_rnw; - -MACROCELL | 0 | 12 | divisor<1> -ATTRIBUTES | 4326256 | 0 -OUTPUTMC | 2 | 0 | 12 | 0 | 5 -INPUTS | 7 | divisor<1> | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 12 -INPUTP | 6 | 59 | 52 | 13 | 46 | 49 | 24 -EQ | 5 | - divisor<1>.T = divisor<1> & cpu_a<1> & !cpu_a<0> & !cpu_d<1>.PIN - # !divisor<1> & cpu_a<1> & !cpu_a<0> & cpu_d<1>.PIN; - divisor<1>.CLK = Ncs2; - divisor<1>.AR = !cpu_Nres; - divisor<1>.CE = !cpu_rnw; - -MACROCELL | 0 | 11 | divisor<2> -ATTRIBUTES | 4326256 | 0 -OUTPUTMC | 2 | 0 | 11 | 0 | 7 -INPUTS | 7 | divisor<2> | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 11 -INPUTP | 6 | 59 | 52 | 15 | 46 | 49 | 24 -EQ | 5 | - divisor<2>.T = divisor<2> & cpu_a<1> & !cpu_a<0> & !cpu_d<2>.PIN - # !divisor<2> & cpu_a<1> & !cpu_a<0> & cpu_d<2>.PIN; - divisor<2>.CLK = Ncs2; - divisor<2>.AR = !cpu_Nres; - divisor<2>.CE = !cpu_rnw; - -MACROCELL | 3 | 11 | spidatain<0> -ATTRIBUTES | 8520560 | 0 -OUTPUTMC | 2 | 3 | 9 | 0 | 4 -INPUTS | 6 | spi_Nsel | spi_miso | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2 -INPUTMC | 4 | 3 | 10 | 1 | 5 | 1 | 4 | 1 | 2 -INPUTP | 2 | 10 | 49 -EQ | 4 | - spidatain<0>.D = !spi_Nsel & spi_miso; - spidatain<0>.CLK = !$OpTx$INV$24__$INT; - spidatain<0>.AR = !cpu_Nres; - spidatain<0>.CE = shiftcnt<0> & shifting2; - -MACROCELL | 3 | 9 | spidatain<1> -ATTRIBUTES | 8520560 | 0 -OUTPUTMC | 2 | 1 | 12 | 0 | 5 -INPUTS | 5 | spidatain<0> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2 -INPUTMC | 4 | 3 | 11 | 1 | 5 | 1 | 4 | 1 | 2 -INPUTP | 1 | 49 -EQ | 4 | - spidatain<1>.D = spidatain<0>; - spidatain<1>.CLK = !$OpTx$INV$24__$INT; - spidatain<1>.AR = !cpu_Nres; - spidatain<1>.CE = shiftcnt<0> & shifting2; - -MACROCELL | 1 | 12 | spidatain<2> -ATTRIBUTES | 8520560 | 0 -OUTPUTMC | 2 | 1 | 11 | 0 | 7 -INPUTS | 5 | spidatain<1> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2 -INPUTMC | 4 | 3 | 9 | 1 | 5 | 1 | 4 | 1 | 2 -INPUTP | 1 | 49 -EQ | 4 | - spidatain<2>.D = spidatain<1>; - spidatain<2>.CLK = !$OpTx$INV$24__$INT; - spidatain<2>.AR = !cpu_Nres; - spidatain<2>.CE = shiftcnt<0> & shifting2; - -MACROCELL | 1 | 11 | spidatain<3> -ATTRIBUTES | 8520560 | 0 -OUTPUTMC | 2 | 1 | 10 | 0 | 14 -INPUTS | 5 | spidatain<2> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2 -INPUTMC | 4 | 1 | 12 | 1 | 5 | 1 | 4 | 1 | 2 -INPUTP | 1 | 49 -EQ | 4 | - spidatain<3>.D = spidatain<2>; - spidatain<3>.CLK = !$OpTx$INV$24__$INT; - spidatain<3>.AR = !cpu_Nres; - spidatain<3>.CE = shiftcnt<0> & shifting2; - -MACROCELL | 1 | 10 | spidatain<4> -ATTRIBUTES | 8520560 | 0 -OUTPUTMC | 2 | 1 | 9 | 0 | 16 -INPUTS | 5 | spidatain<3> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2 -INPUTMC | 4 | 1 | 11 | 1 | 5 | 1 | 4 | 1 | 2 -INPUTP | 1 | 49 -EQ | 4 | - spidatain<4>.D = spidatain<3>; - spidatain<4>.CLK = !$OpTx$INV$24__$INT; - spidatain<4>.AR = !cpu_Nres; - spidatain<4>.CE = shiftcnt<0> & shifting2; - -MACROCELL | 1 | 9 | spidatain<5> -ATTRIBUTES | 8520560 | 0 -OUTPUTMC | 2 | 1 | 7 | 2 | 1 -INPUTS | 5 | spidatain<4> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2 -INPUTMC | 4 | 1 | 10 | 1 | 5 | 1 | 4 | 1 | 2 -INPUTP | 1 | 49 -EQ | 4 | - spidatain<5>.D = spidatain<4>; - spidatain<5>.CLK = !$OpTx$INV$24__$INT; - spidatain<5>.AR = !cpu_Nres; - spidatain<5>.CE = shiftcnt<0> & shifting2; - -MACROCELL | 1 | 7 | spidatain<6> -ATTRIBUTES | 8520560 | 0 -OUTPUTMC | 2 | 1 | 6 | 2 | 4 -INPUTS | 5 | spidatain<5> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2 -INPUTMC | 4 | 1 | 9 | 1 | 5 | 1 | 4 | 1 | 2 -INPUTP | 1 | 49 -EQ | 4 | - spidatain<6>.D = spidatain<5>; - spidatain<6>.CLK = !$OpTx$INV$24__$INT; - spidatain<6>.AR = !cpu_Nres; - spidatain<6>.CE = shiftcnt<0> & shifting2; - -MACROCELL | 1 | 6 | spidatain<7> -ATTRIBUTES | 8520560 | 0 -OUTPUTMC | 1 | 2 | 7 -INPUTS | 5 | spidatain<6> | $OpTx$INV$24__$INT | cpu_Nres | shiftcnt<0> | shifting2 -INPUTMC | 4 | 1 | 7 | 1 | 5 | 1 | 4 | 1 | 2 -INPUTP | 1 | 49 -EQ | 4 | - spidatain<7>.D = spidatain<6>; - spidatain<7>.CLK = !$OpTx$INV$24__$INT; - spidatain<7>.AR = !cpu_Nres; - spidatain<7>.CE = shiftcnt<0> & shifting2; - -MACROCELL | 3 | 16 | int_sclk -ATTRIBUTES | 8651698 | 0 -INPUTS | 8 | cpol | cpu_Nres | cpha | shiftcnt<0> | shiftdone | shifting2 | $OpTx$INV$24__$INT | shiftcnt<1>.EXP -INPUTMC | 7 | 0 | 15 | 0 | 17 | 1 | 4 | 3 | 0 | 1 | 2 | 1 | 5 | 3 | 15 -INPUTP | 1 | 49 -IMPORTS | 1 | 3 | 15 -EQ | 9 | - spi_sclk.D = cpol - $ cpu_Nres & !cpha & shiftcnt<0> & !shiftdone & - shifting2 -;Imported pterms FB4_16 - # cpu_Nres & cpha & !shiftcnt<0> & !shiftdone & - shifting2; - spi_sclk.CLK = !$OpTx$INV$24__$INT; - spi_sclk.AP = !cpu_Nres & cpol; - spi_sclk.AR = !cpu_Nres & !cpol; - -MACROCELL | 0 | 14 | int_dout<3> -ATTRIBUTES | 265986 | 0 -INPUTS | 7 | Ncs2 | cpu_rnw | spidatain<3> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | tmo -INPUTMC | 2 | 1 | 11 | 0 | 6 -INPUTP | 5 | 46 | 24 | 59 | 52 | 20 -EQ | 5 | - cpu_d<3> = !Ncs2 & cpu_rnw & tmo & !cpu_a<1> & cpu_a<0> & - cpu_Nphi2 - # !Ncs2 & cpu_rnw & spidatain<3> & !cpu_a<1> & - !cpu_a<0> & cpu_Nphi2; - cpu_d<3>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2; - -MACROCELL | 2 | 1 | int_dout<5> -ATTRIBUTES | 265986 | 0 -INPUTS | 8 | Ncs2 | cpu_rnw | cpu_a<1> | start_shifting | cpu_a<0> | cpu_Nphi2 | shifting2 | spidatain<5> -INPUTMC | 3 | 3 | 2 | 1 | 2 | 1 | 9 -INPUTP | 5 | 46 | 24 | 59 | 52 | 20 -EQ | 7 | - cpu_d<5> = !Ncs2 & cpu_rnw & spidatain<5> & !cpu_a<1> & - !cpu_a<0> & cpu_Nphi2 - # !Ncs2 & cpu_rnw & !cpu_a<1> & start_shifting & - cpu_a<0> & cpu_Nphi2 - # !Ncs2 & cpu_rnw & !cpu_a<1> & cpu_a<0> & - shifting2 & cpu_Nphi2; - cpu_d<5>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2; - -MACROCELL | 2 | 4 | int_dout<6> -ATTRIBUTES | 265986 | 0 -INPUTS | 7 | Ncs2 | cpu_rnw | spidatain<6> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | ier -INPUTMC | 2 | 1 | 7 | 3 | 17 -INPUTP | 5 | 46 | 24 | 59 | 52 | 20 -EQ | 5 | - cpu_d<6> = !Ncs2 & cpu_rnw & ier & !cpu_a<1> & cpu_a<0> & - cpu_Nphi2 - # !Ncs2 & cpu_rnw & spidatain<6> & !cpu_a<1> & - !cpu_a<0> & cpu_Nphi2; - cpu_d<6>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2; - -MACROCELL | 2 | 7 | int_dout<7> -ATTRIBUTES | 265986 | 0 -INPUTS | 7 | Ncs2 | cpu_rnw | spidatain<7> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | tc -INPUTMC | 2 | 1 | 6 | 1 | 3 -INPUTP | 5 | 46 | 24 | 59 | 52 | 20 -EQ | 5 | - cpu_d<7> = !Ncs2 & cpu_rnw & spidatain<7> & !cpu_a<1> & - !cpu_a<0> & cpu_Nphi2 - # !Ncs2 & cpu_rnw & !cpu_a<1> & tc & cpu_a<0> & - cpu_Nphi2; - cpu_d<7>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2; - -MACROCELL | 3 | 12 | shiftcnt<3> -ATTRIBUTES | 4326192 | 0 -OUTPUTMC | 5 | 1 | 1 | 3 | 12 | 3 | 0 | 1 | 0 | 1 | 2 -INPUTS | 7 | shiftcnt<2> | shiftcnt<0> | shiftcnt<1> | shifting2 | shiftcnt<3> | $OpTx$INV$24__$INT | cpu_Nres -INPUTMC | 6 | 3 | 14 | 1 | 4 | 3 | 15 | 1 | 2 | 3 | 12 | 1 | 5 -INPUTP | 1 | 49 -EQ | 5 | - shiftcnt<3>.T = shiftcnt<3> & !shifting2 - # shiftcnt<2> & shiftcnt<0> & shiftcnt<1> & - shifting2; - shiftcnt<3>.CLK = !$OpTx$INV$24__$INT; - shiftcnt<3>.AR = !cpu_Nres; - -MACROCELL | 3 | 14 | shiftcnt<2> -ATTRIBUTES | 4326192 | 0 -OUTPUTMC | 6 | 1 | 1 | 3 | 12 | 3 | 14 | 3 | 0 | 1 | 0 | 1 | 2 -INPUTS | 6 | shiftcnt<0> | shiftcnt<1> | shifting2 | shiftcnt<2> | $OpTx$INV$24__$INT | cpu_Nres -INPUTMC | 5 | 1 | 4 | 3 | 15 | 1 | 2 | 3 | 14 | 1 | 5 -INPUTP | 1 | 49 -EQ | 4 | - shiftcnt<2>.T = shiftcnt<2> & !shifting2 - # shiftcnt<0> & shiftcnt<1> & shifting2; - shiftcnt<2>.CLK = !$OpTx$INV$24__$INT; - shiftcnt<2>.AR = !cpu_Nres; - -MACROCELL | 1 | 4 | shiftcnt<0> -ATTRIBUTES | 8520496 | 0 -OUTPUTMC | 14 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 0 -INPUTS | 4 | shiftcnt<0> | shifting2 | $OpTx$INV$24__$INT | cpu_Nres -INPUTMC | 3 | 1 | 4 | 1 | 2 | 1 | 5 -INPUTP | 1 | 49 -EQ | 3 | - shiftcnt<0>.D = !shiftcnt<0> & shifting2; - shiftcnt<0>.CLK = !$OpTx$INV$24__$INT; - shiftcnt<0>.AR = !cpu_Nres; - -MACROCELL | 3 | 15 | shiftcnt<1> -ATTRIBUTES | 8520496 | 0 -OUTPUTMC | 8 | 1 | 1 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 0 | 1 | 0 | 1 | 2 | 3 | 16 -INPUTS | 7 | shiftcnt<0> | shiftcnt<1> | shifting2 | $OpTx$INV$24__$INT | cpu_Nres | cpha | shiftdone -INPUTMC | 6 | 1 | 4 | 3 | 15 | 1 | 2 | 1 | 5 | 0 | 17 | 3 | 0 -INPUTP | 1 | 49 -EXPORTS | 1 | 3 | 16 -EQ | 6 | - shiftcnt<1>.D = shiftcnt<0> & !shiftcnt<1> & shifting2 - # !shiftcnt<0> & shiftcnt<1> & shifting2; - shiftcnt<1>.CLK = !$OpTx$INV$24__$INT; - shiftcnt<1>.AR = !cpu_Nres; - shiftcnt<1>.EXP = cpu_Nres & cpha & !shiftcnt<0> & !shiftdone & - shifting2 - -MACROCELL | 3 | 0 | shiftdone -ATTRIBUTES | 8520496 | 0 -OUTPUTMC | 7 | 1 | 1 | 3 | 16 | 1 | 3 | 1 | 2 | 1 | 17 | 1 | 0 | 3 | 15 -INPUTS | 6 | shiftcnt<3> | shiftcnt<2> | shiftcnt<0> | shiftcnt<1> | $OpTx$INV$24__$INT | cpu_Nres -INPUTMC | 5 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 1 | 5 -INPUTP | 1 | 49 -EQ | 4 | - shiftdone.D = shiftcnt<3> & shiftcnt<2> & shiftcnt<0> & - shiftcnt<1>; - shiftdone.CLK = !$OpTx$INV$24__$INT; - shiftdone.AR = !cpu_Nres; - -MACROCELL | 3 | 2 | start_shifting -ATTRIBUTES | 4326192 | 0 -OUTPUTMC | 5 | 2 | 1 | 3 | 2 | 1 | 2 | 3 | 13 | 1 | 5 -INPUTS | 7 | frx | cpu_a<1> | start_shifting | cpu_a<0> | cpu_rnw | Ncs2 | start_shifting/start_shifting_RSTF__$INT -INPUTMC | 3 | 0 | 9 | 3 | 2 | 1 | 17 -INPUTP | 4 | 59 | 52 | 24 | 46 -EQ | 4 | - start_shifting.T = !cpu_rnw & !cpu_a<1> & !start_shifting & !cpu_a<0> - # frx & !cpu_a<1> & !start_shifting & !cpu_a<0>; - start_shifting.CLK = Ncs2; - start_shifting.AR = !start_shifting/start_shifting_RSTF__$INT; - -MACROCELL | 1 | 3 | tc -ATTRIBUTES | 8520672 | 0 -OUTPUTMC | 2 | 2 | 7 | 2 | 17 -INPUTS | 4 | Ncs2 | shiftdone | cpu_a<1> | cpu_a<0> -INPUTMC | 1 | 3 | 0 -INPUTP | 3 | 46 | 59 | 52 -EQ | 4 | - tc.D = Gnd; - tc.CLK = Ncs2; - tc.AP = shiftdone; - tc.CE = !cpu_a<1> & !cpu_a<0>; - -MACROCELL | 0 | 3 | spidataout<0> -ATTRIBUTES | 4326240 | 0 -OUTPUTMC | 2 | 1 | 1 | 0 | 3 -INPUTS | 7 | cpu_a<1> | spidataout<0> | cpu_a<0> | cpu_d<0>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 3 -INPUTP | 6 | 59 | 52 | 12 | 46 | 49 | 24 -EQ | 6 | - spidataout<0>.T = !cpu_a<1> & spidataout<0> & !cpu_a<0> & - !cpu_d<0>.PIN - # !cpu_a<1> & !spidataout<0> & !cpu_a<0> & - cpu_d<0>.PIN; - spidataout<0>.CLK = Ncs2; - spidataout<0>.CE = cpu_Nres & !cpu_rnw; - -MACROCELL | 0 | 2 | spidataout<1> -ATTRIBUTES | 4326240 | 0 -OUTPUTMC | 2 | 0 | 2 | 1 | 2 -INPUTS | 7 | cpu_a<1> | spidataout<1> | cpu_a<0> | cpu_d<1>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 2 -INPUTP | 6 | 59 | 52 | 13 | 46 | 49 | 24 -EQ | 6 | - spidataout<1>.T = !cpu_a<1> & spidataout<1> & !cpu_a<0> & - !cpu_d<1>.PIN - # !cpu_a<1> & !spidataout<1> & !cpu_a<0> & - cpu_d<1>.PIN; - spidataout<1>.CLK = Ncs2; - spidataout<1>.CE = cpu_Nres & !cpu_rnw; - -MACROCELL | 0 | 1 | spidataout<2> -ATTRIBUTES | 4326240 | 0 -OUTPUTMC | 2 | 1 | 0 | 0 | 1 -INPUTS | 7 | cpu_a<1> | spidataout<2> | cpu_a<0> | cpu_d<2>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 1 -INPUTP | 6 | 59 | 52 | 15 | 46 | 49 | 24 -EQ | 6 | - spidataout<2>.T = !cpu_a<1> & spidataout<2> & !cpu_a<0> & - !cpu_d<2>.PIN - # !cpu_a<1> & !spidataout<2> & !cpu_a<0> & - cpu_d<2>.PIN; - spidataout<2>.CLK = Ncs2; - spidataout<2>.CE = cpu_Nres & !cpu_rnw; - -MACROCELL | 0 | 0 | spidataout<3> -ATTRIBUTES | 4326240 | 0 -OUTPUTMC | 2 | 1 | 0 | 0 | 0 -INPUTS | 7 | cpu_a<1> | spidataout<3> | cpu_a<0> | cpu_d<3>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 0 | 0 -INPUTP | 6 | 59 | 52 | 26 | 46 | 49 | 24 -EQ | 6 | - spidataout<3>.T = !cpu_a<1> & spidataout<3> & !cpu_a<0> & - !cpu_d<3>.PIN - # !cpu_a<1> & !spidataout<3> & !cpu_a<0> & - cpu_d<3>.PIN; - spidataout<3>.CLK = Ncs2; - spidataout<3>.CE = cpu_Nres & !cpu_rnw; - -MACROCELL | 3 | 8 | spidataout<4> -ATTRIBUTES | 4326240 | 0 -OUTPUTMC | 2 | 1 | 1 | 3 | 8 -INPUTS | 7 | cpu_a<1> | spidataout<4> | cpu_a<0> | cpu_d<4>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 3 | 8 -INPUTP | 6 | 59 | 52 | 27 | 46 | 49 | 24 -EQ | 6 | - spidataout<4>.T = !cpu_a<1> & spidataout<4> & !cpu_a<0> & - !cpu_d<4>.PIN - # !cpu_a<1> & !spidataout<4> & !cpu_a<0> & - cpu_d<4>.PIN; - spidataout<4>.CLK = Ncs2; - spidataout<4>.CE = cpu_Nres & !cpu_rnw; - -MACROCELL | 3 | 6 | spidataout<5> -ATTRIBUTES | 4326240 | 0 -OUTPUTMC | 2 | 1 | 0 | 3 | 6 -INPUTS | 7 | cpu_a<1> | spidataout<5> | cpu_a<0> | cpu_d<5>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 3 | 6 -INPUTP | 6 | 59 | 52 | 29 | 46 | 49 | 24 -EQ | 6 | - spidataout<5>.T = !cpu_a<1> & spidataout<5> & !cpu_a<0> & - !cpu_d<5>.PIN - # !cpu_a<1> & !spidataout<5> & !cpu_a<0> & - cpu_d<5>.PIN; - spidataout<5>.CLK = Ncs2; - spidataout<5>.CE = cpu_Nres & !cpu_rnw; - -MACROCELL | 3 | 5 | spidataout<6> -ATTRIBUTES | 4326240 | 0 -OUTPUTMC | 2 | 1 | 0 | 3 | 5 -INPUTS | 7 | cpu_a<1> | spidataout<6> | cpu_a<0> | cpu_d<6>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 3 | 5 -INPUTP | 6 | 59 | 52 | 31 | 46 | 49 | 24 -EQ | 6 | - spidataout<6>.T = !cpu_a<1> & spidataout<6> & !cpu_a<0> & - !cpu_d<6>.PIN - # !cpu_a<1> & !spidataout<6> & !cpu_a<0> & - cpu_d<6>.PIN; - spidataout<6>.CLK = Ncs2; - spidataout<6>.CE = cpu_Nres & !cpu_rnw; - -MACROCELL | 3 | 3 | spidataout<7> -ATTRIBUTES | 4326240 | 0 -OUTPUTMC | 2 | 1 | 0 | 3 | 3 -INPUTS | 7 | cpu_a<1> | spidataout<7> | cpu_a<0> | cpu_d<7>.PIN | Ncs2 | cpu_Nres | cpu_rnw -INPUTMC | 1 | 3 | 3 -INPUTP | 6 | 59 | 52 | 33 | 46 | 49 | 24 -EQ | 6 | - spidataout<7>.T = !cpu_a<1> & spidataout<7> & !cpu_a<0> & - !cpu_d<7>.PIN - # !cpu_a<1> & !spidataout<7> & !cpu_a<0> & - cpu_d<7>.PIN; - spidataout<7>.CLK = Ncs2; - spidataout<7>.CE = cpu_Nres & !cpu_rnw; - -MACROCELL | 2 | 14 | ng_OBUF -ATTRIBUTES | 264962 | 0 -INPUTS | 3 | Ncs2 | nio_stb | nio_sel -INPUTP | 3 | 46 | 9 | 3 -EQ | 1 | - ng = Ncs2 & nio_stb & nio_sel; - -MACROCELL | 0 | 4 | int_dout<0> -ATTRIBUTES | 265986 | 0 -INPUTS | 9 | Ncs2 | cpu_rnw | spidatain<0> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | divisor<0> | cpha | spi_Nsel -INPUTMC | 4 | 3 | 11 | 0 | 13 | 0 | 17 | 3 | 10 -INPUTP | 5 | 46 | 24 | 59 | 52 | 20 -EQ | 9 | - cpu_d<0> = !Ncs2 & cpu_rnw & spi_Nsel & cpu_a<1> & - cpu_a<0> & cpu_Nphi2 - # !Ncs2 & cpu_rnw & cpha & !cpu_a<1> & cpu_a<0> & - cpu_Nphi2 - # !Ncs2 & cpu_rnw & divisor<0> & cpu_a<1> & - !cpu_a<0> & cpu_Nphi2 - # !Ncs2 & cpu_rnw & spidatain<0> & !cpu_a<1> & - !cpu_a<0> & cpu_Nphi2; - cpu_d<0>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2; - -MACROCELL | 0 | 5 | int_dout<1> -ATTRIBUTES | 265986 | 0 -INPUTS | 8 | Ncs2 | cpu_rnw | spidatain<1> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | cpol | divisor<1> -INPUTMC | 3 | 3 | 9 | 0 | 15 | 0 | 12 -INPUTP | 5 | 46 | 24 | 59 | 52 | 20 -EQ | 7 | - cpu_d<1> = !Ncs2 & cpu_rnw & cpol & !cpu_a<1> & cpu_a<0> & - cpu_Nphi2 - # !Ncs2 & cpu_rnw & divisor<1> & cpu_a<1> & - !cpu_a<0> & cpu_Nphi2 - # !Ncs2 & cpu_rnw & spidatain<1> & !cpu_a<1> & - !cpu_a<0> & cpu_Nphi2; - cpu_d<1>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2; - -MACROCELL | 0 | 7 | int_dout<2> -ATTRIBUTES | 265986 | 0 -INPUTS | 8 | Ncs2 | cpu_rnw | spidatain<2> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | ece | divisor<2> -INPUTMC | 3 | 1 | 12 | 0 | 10 | 0 | 11 -INPUTP | 5 | 46 | 24 | 59 | 52 | 20 -EQ | 7 | - cpu_d<2> = !Ncs2 & cpu_rnw & ece & !cpu_a<1> & cpu_a<0> & - cpu_Nphi2 - # !Ncs2 & cpu_rnw & divisor<2> & cpu_a<1> & - !cpu_a<0> & cpu_Nphi2 - # !Ncs2 & cpu_rnw & spidatain<2> & !cpu_a<1> & - !cpu_a<0> & cpu_Nphi2; - cpu_d<2>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2; - -MACROCELL | 0 | 16 | int_dout<4> -ATTRIBUTES | 265986 | 0 -INPUTS | 9 | Ncs2 | cpu_rnw | spidatain<4> | cpu_a<1> | cpu_a<0> | cpu_Nphi2 | spi_int | frx | slaveinten -INPUTMC | 3 | 1 | 10 | 0 | 9 | 0 | 8 -INPUTP | 6 | 46 | 24 | 59 | 52 | 20 | 7 -EQ | 9 | - cpu_d<4> = !Ncs2 & cpu_rnw & frx & !cpu_a<1> & cpu_a<0> & - cpu_Nphi2 - # !Ncs2 & cpu_rnw & slaveinten & cpu_a<1> & - cpu_a<0> & cpu_Nphi2 - # !Ncs2 & cpu_rnw & spidatain<4> & !cpu_a<1> & - !cpu_a<0> & cpu_Nphi2 - # !Ncs2 & cpu_rnw & cpu_a<1> & !cpu_a<0> & !spi_int & - cpu_Nphi2; - cpu_d<4>.OE = !Ncs2 & cpu_rnw & cpu_Nphi2; - -MACROCELL | 1 | 2 | shifting2 -ATTRIBUTES | 8520480 | 0 -OUTPUTMC | 19 | 1 | 1 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 2 | 1 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 13 | 1 | 5 | 1 | 0 | 1 | 2 -INPUTS | 8 | shiftdone | start_shifting | $OpTx$INV$24__$INT | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | spidataout<1> | shifting2 -INPUTMC | 8 | 3 | 0 | 3 | 2 | 1 | 5 | 3 | 12 | 3 | 14 | 3 | 15 | 0 | 2 | 1 | 2 -EXPORTS | 1 | 1 | 1 -EQ | 4 | - shifting2.D = !shiftdone & start_shifting; - shifting2.CLK = !$OpTx$INV$24__$INT; - shifting2.EXP = shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & - !shiftdone & !spidataout<1> & shifting2 - -MACROCELL | 2 | 16 | add_dec/XLXN_11 -ATTRIBUTES | 8553216 | 0 -OUTPUTMC | 1 | 2 | 8 -INPUTS | 4 | nio_stb | a9 | a8 | a10 -INPUTP | 4 | 9 | 89 | 88 | 90 -EQ | 2 | - !add_dec/XLXN_11.D = !nio_stb & a9 & a8 & a10; - add_dec/XLXN_11.CLK = extclk; // GCK -GLOBALS | 1 | 2 | extclk - -MACROCELL | 3 | 7 | b10_OBUF -ATTRIBUTES | 264962 | 0 -INPUTS | 2 | a10 | nio_sel -INPUTP | 2 | 90 | 3 -EQ | 1 | - b10 = a10 & nio_sel; - -MACROCELL | 3 | 1 | b8_OBUF -ATTRIBUTES | 264962 | 0 -INPUTS | 2 | a8 | nio_sel -INPUTP | 2 | 88 | 3 -EQ | 1 | - b8 = a8 & nio_sel; - -MACROCELL | 3 | 4 | b9_OBUF -ATTRIBUTES | 264962 | 0 -INPUTS | 2 | a9 | nio_sel -INPUTP | 2 | 89 | 3 -EQ | 1 | - b9 = a9 & nio_sel; - -MACROCELL | 3 | 13 | led_OBUF -ATTRIBUTES | 264962 | 0 -INPUTS | 3 | spi_Nsel | start_shifting | shifting2 -INPUTMC | 3 | 3 | 10 | 3 | 2 | 1 | 2 -EQ | 1 | - led = spi_Nsel & !start_shifting & !shifting2; - -MACROCELL | 2 | 8 | noe_OBUF -ATTRIBUTES | 264962 | 0 -INPUTS | 3 | nio_sel | add_dec/XLXN_11 | nio_stb -INPUTMC | 1 | 2 | 16 -INPUTP | 2 | 3 | 9 -EQ | 2 | - !noe = !nio_stb & add_dec/XLXN_11 - # !nio_sel & add_dec/XLXN_11; - -MACROCELL | 1 | 8 | cpu_Nirq_OBUFE -ATTRIBUTES | 265986 | 0 -INPUTS | 1 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST -INPUTMC | 1 | 2 | 17 -EQ | 2 | - cpu_Nirq = Gnd; - cpu_Nirq.OE = cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST; - -MACROCELL | 1 | 5 | $OpTx$INV$24__$INT -ATTRIBUTES | 133888 | 0 -OUTPUTMC | 16 | 1 | 1 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 0 | 1 | 2 -INPUTS | 5 | ece | cpu_Nphi2 | extclk | start_shifting | shifting2 -INPUTMC | 3 | 0 | 10 | 3 | 2 | 1 | 2 -INPUTP | 2 | 20 | 21 -EQ | 3 | - $OpTx$INV$24__$INT = ece & !extclk - # !ece & !cpu_Nphi2 - # !start_shifting & !shifting2; - -MACROCELL | 1 | 17 | start_shifting/start_shifting_RSTF__$INT -ATTRIBUTES | 133888 | 0 -OUTPUTMC | 1 | 3 | 2 -INPUTS | 2 | cpu_Nres | shiftdone -INPUTMC | 1 | 3 | 0 -INPUTP | 1 | 49 -EQ | 1 | - start_shifting/start_shifting_RSTF__$INT = cpu_Nres & !shiftdone; - -MACROCELL | 2 | 17 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST -ATTRIBUTES | 133888 | 0 -OUTPUTMC | 1 | 1 | 8 -INPUTS | 4 | ier | tc | slaveinten | spi_int -INPUTMC | 3 | 3 | 17 | 1 | 3 | 0 | 8 -INPUTP | 1 | 7 -EQ | 2 | - cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST = ier & tc - # slaveinten & !spi_int; - -MACROCELL | 1 | 0 | EXP6_ -ATTRIBUTES | 2048 | 0 -OUTPUTMC | 1 | 1 | 1 -INPUTS | 10 | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | shiftdone | spidataout<2> | shifting2 | spidataout<3> | spidataout<5> | spidataout<6> | spidataout<7> -INPUTMC | 10 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 0 | 0 | 1 | 1 | 2 | 0 | 0 | 3 | 6 | 3 | 5 | 3 | 3 -EXPORTS | 1 | 1 | 1 -EQ | 10 | - EXP6_.EXP = shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & - !shiftdone & !spidataout<2> & shifting2 - # shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & - !shiftdone & !spidataout<3> & shifting2 - # !shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & - !shiftdone & !spidataout<5> & shifting2 - # !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & - !shiftdone & !spidataout<6> & shifting2 - # !shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & - !shiftdone & !spidataout<7> & shifting2 - -PIN | cpu_Nres | 64 | 0 | N/A | 49 | 35 | 1 | 1 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 3 | 11 | 3 | 9 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 7 | 1 | 6 | 3 | 16 | 3 | 12 | 3 | 14 | 1 | 4 | 3 | 15 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 1 | 17 -PIN | Ncs2 | 64 | 0 | N/A | 46 | 30 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 1 | 3 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 2 | 14 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16 -PIN | cpu_rnw | 64 | 0 | N/A | 24 | 28 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16 -PIN | cpu_a<0> | 64 | 0 | N/A | 52 | 29 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 1 | 3 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16 -PIN | cpu_a<1> | 64 | 0 | N/A | 59 | 29 | 3 | 10 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 17 | 0 | 8 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 3 | 2 | 1 | 3 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16 -PIN | spi_miso | 64 | 0 | N/A | 10 | 1 | 3 | 11 -PIN | nio_stb | 64 | 0 | N/A | 9 | 3 | 2 | 14 | 2 | 16 | 2 | 8 -PIN | a9 | 64 | 0 | N/A | 89 | 2 | 2 | 16 | 3 | 4 -PIN | a8 | 64 | 0 | N/A | 88 | 2 | 2 | 16 | 3 | 1 -PIN | a10 | 64 | 0 | N/A | 90 | 2 | 2 | 16 | 3 | 7 -PIN | cpu_Nphi2 | 64 | 0 | N/A | 20 | 9 | 0 | 14 | 2 | 1 | 2 | 4 | 2 | 7 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 16 | 1 | 5 -PIN | nio_sel | 64 | 0 | N/A | 3 | 5 | 2 | 14 | 3 | 7 | 3 | 1 | 3 | 4 | 2 | 8 -PIN | spi_int | 64 | 0 | N/A | 7 | 2 | 0 | 16 | 2 | 17 -PIN | extclk | 8256 | 0 | N/A | 21 | 2 | 1 | 5 | 2 | 16 -PIN | spi_mosi | 536871040 | 0 | N/A | 87 -PIN | spi_Nsel | 536871040 | 0 | N/A | 68 -PIN | spi_sclk | 536871040 | 0 | N/A | 83 -PIN | ng | 536871040 | 0 | N/A | 50 -PIN | b10 | 536871040 | 0 | N/A | 65 -PIN | b8 | 536871040 | 0 | N/A | 62 -PIN | b9 | 536871040 | 0 | N/A | 63 -PIN | led | 536871040 | 0 | N/A | 72 -PIN | noe | 536871040 | 0 | N/A | 38 -PIN | cpu_Nirq | 536871040 | 0 | N/A | 92 -PIN | cpu_d<3> | 536870976 | 0 | N/A | 26 | 2 | 0 | 6 | 0 | 0 -PIN | cpu_d<5> | 536870976 | 0 | N/A | 29 | 1 | 3 | 6 -PIN | cpu_d<6> | 536870976 | 0 | N/A | 31 | 2 | 3 | 17 | 3 | 5 -PIN | cpu_d<7> | 536870976 | 0 | N/A | 33 | 1 | 3 | 3 -PIN | cpu_d<0> | 536870976 | 0 | N/A | 12 | 4 | 3 | 10 | 0 | 17 | 0 | 13 | 0 | 3 -PIN | cpu_d<1> | 536870976 | 0 | N/A | 13 | 3 | 0 | 15 | 0 | 12 | 0 | 2 -PIN | cpu_d<2> | 536870976 | 0 | N/A | 15 | 3 | 0 | 10 | 0 | 11 | 0 | 1 -PIN | cpu_d<4> | 536870976 | 0 | N/A | 27 | 3 | 0 | 9 | 0 | 8 | 3 | 8 diff --git a/VHDL/spi6502b.pnx b/VHDL/spi6502b.pnx deleted file mode 100644 index 4b243e9..0000000 --- a/VHDL/spi6502b.pnx +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - -]> - diff --git a/VHDL/spi6502b.rpt b/VHDL/spi6502b.rpt deleted file mode 100644 index 7880cd0..0000000 --- a/VHDL/spi6502b.rpt +++ /dev/null @@ -1,798 +0,0 @@ - -cpldfit: version G.38 Xilinx Inc. - Fitter Report -Design Name: spi6502b Date: 5-11-2017, 2:09AM -Device Used: XC9572XL-10-PC44 -Fitting Status: Successful - -**************************** Resource Summary **************************** - -Macrocells Product Terms Registers Pins Function Block -Used Used Used Used Inputs Used -56 /72 ( 78%) 209 /360 ( 58%) 38 /72 ( 53%) 32 /34 ( 94%) 116/216 ( 54%) - -PIN RESOURCES: - -Signal Type Required Mapped | Pin Type Used Remaining -------------------------------------|--------------------------------------- -Input : 13 13 | I/O : 26 2 -Output : 10 10 | GCK/IO : 3 0 -Bidirectional : 8 8 | GTS/IO : 2 0 -GCK : 1 1 | GSR/IO : 1 0 -GTS : 0 0 | -GSR : 0 0 | - ---- ---- - Total 32 32 - -MACROCELL RESOURCES: - -Total Macrocells Available 72 -Registered Macrocells 38 -Non-registered Macrocell driving I/O 15 - -GLOBAL RESOURCES: - -Signal 'extclk' mapped onto global clock net GCK2. -Global output enable net(s) unused. -Global set/reset net(s) unused. - -POWER DATA: - -There are 56 macrocells in high performance mode (MCHP). -There are 0 macrocells in low power mode (MCLP). -There are a total of 56 macrocells used (MC). - -End of Resource Summary - *************** Summary of Required Resources ****************** - -** LOGIC ** -Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init -Name Pt Used Mode Rate # Type Use State -$OpTx$INV$24__$INT 3 5 FB2_6 STD 37 I/O I -add_dec/XLXN_11 1 4 FB3_17 STD 22 I/O I RESET -b10 1 2 FB4_8 STD FAST 27 I/O O -b8 1 2 FB4_2 STD FAST 25 I/O O -b9 1 2 FB4_5 STD FAST 26 I/O O -cpha 5 7 FB1_18 STD (b) (b) RESET -cpol 5 7 FB1_16 STD (b) (b) RESET -cpu_Nirq 1 1 FB2_9 STD FAST 39 GSR/I/O O -cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 2 4 FB3_18 STD (b) (b) -cpu_d<0> 5 9 FB1_5 STD FAST 2 I/O I/O -cpu_d<1> 4 8 FB1_6 STD FAST 3 I/O I/O -cpu_d<2> 4 8 FB1_8 STD FAST 4 I/O I/O -cpu_d<3> 3 7 FB1_15 STD FAST 8 I/O I/O -cpu_d<4> 5 9 FB1_17 STD FAST 9 I/O I/O -cpu_d<5> 4 8 FB3_2 STD FAST 11 I/O I/O -cpu_d<6> 3 7 FB3_5 STD FAST 12 I/O I/O -cpu_d<7> 3 7 FB3_8 STD FAST 13 I/O I/O -divisor<0> 5 7 FB1_14 STD 7 GCK/I/O I RESET -divisor<1> 5 7 FB1_13 STD (b) (b) RESET -divisor<2> 5 7 FB1_12 STD (b) (b) RESET -ece 5 7 FB1_11 STD 6 GCK/I/O GCK/I RESET -frx 5 7 FB1_10 STD (b) (b) RESET -ier 5 7 FB4_18 STD (b) (b) RESET -led 1 3 FB4_14 STD FAST 29 I/O O -ng 1 3 FB3_15 STD FAST 20 I/O O -noe 2 3 FB3_9 STD FAST 14 I/O O -shiftcnt<0> 3 4 FB2_5 STD 36 I/O I RESET -shiftcnt<1> 4 5 FB4_16 STD (b) (b) RESET -shiftcnt<2> 4 6 FB4_15 STD 33 I/O (b) RESET -shiftcnt<3> 4 7 FB4_13 STD (b) (b) RESET -shiftdone 3 6 FB4_1 STD (b) (b) RESET -shifting2 2 3 FB2_3 STD (b) (b) RESET -slaveinten 5 7 FB1_9 STD 5 GCK/I/O I RESET -spi_Nsel 5 7 FB4_11 STD FAST 28 I/O O RESET -spi_mosi 11 16 FB2_2 STD FAST 35 I/O O RESET -spi_sclk 6 7 FB4_17 STD FAST 34 I/O O RESET -spidatain<0> 4 6 FB4_12 STD (b) (b) RESET -spidatain<1> 4 5 FB4_10 STD (b) (b) RESET -spidatain<2> 4 5 FB2_13 STD (b) (b) RESET -spidatain<3> 4 5 FB2_12 STD (b) (b) RESET -spidatain<4> 4 5 FB2_11 STD 40 GTS/I/O I RESET -spidatain<5> 4 5 FB2_10 STD (b) (b) RESET -spidatain<6> 4 5 FB2_8 STD 38 I/O I RESET -spidatain<7> 4 5 FB2_7 STD (b) (b) RESET -spidataout<0> 4 7 FB1_4 STD (b) (b) RESET -spidataout<1> 4 7 FB1_3 STD (b) (b) RESET -spidataout<2> 4 7 FB1_2 STD 1 I/O (b) RESET -spidataout<3> 4 7 FB1_1 STD (b) (b) RESET -spidataout<4> 4 7 FB4_9 STD (b) (b) RESET -spidataout<5> 4 7 FB4_7 STD (b) (b) RESET -spidataout<6> 4 7 FB4_6 STD (b) (b) RESET -spidataout<7> 4 7 FB4_4 STD (b) (b) RESET -start_shifting 4 7 FB4_3 STD (b) (b) RESET -start_shifting/start_shifting_RSTF__$INT 1 2 FB2_18 STD (b) (b) -tc 3 4 FB2_4 STD (b) (b) RESET -tmo 5 7 FB1_7 STD (b) (b) RESET - -** INPUTS ** -Signal Loc Pin Pin Pin -Name # Type Use -Ncs2 FB3_11 18 I/O I -a10 FB2_8 38 I/O I -a8 FB2_5 36 I/O I -a9 FB2_6 37 I/O I -cpu_Nphi2 FB1_9 5 GCK/I/O I -cpu_Nres FB3_14 19 I/O I -cpu_a<0> FB3_17 22 I/O I -cpu_a<1> FB3_16 24 I/O I -cpu_rnw FB1_14 7 GCK/I/O I -extclk FB1_11 6 GCK/I/O GCK/I -nio_sel FB2_11 40 GTS/I/O I -nio_stb FB2_15 43 I/O I -spi_int FB2_14 42 GTS/I/O I -spi_miso FB2_17 44 I/O I - -End of Resources - - *********************Function Block Resource Summary*********************** -Function # of FB Inputs Signals Total O/IO IO -Block Macrocells Used Used Pt Used Req Avail -FB1 18 31 31 82 0/5 9 -FB2 13 31 31 48 2/0 9 -FB3 7 20 20 16 2/3 9 -FB4 18 34 34 63 6/0 7 - ---- ----- ----- ----- - 56 209 10/8 34 - *********************************** FB1 *********************************** -Number of function block inputs used/remaining: 31/23 -Number of signals used by logic mapping into function block: 31 -Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin -Name Pt Pt Pt Pt Mode # Type Use -spidataout<3> 4 0 0 1 FB1_1 STD (b) (b) -spidataout<2> 4 0 0 1 FB1_2 STD 1 I/O (b) -spidataout<1> 4 0 0 1 FB1_3 STD (b) (b) -spidataout<0> 4 0 0 1 FB1_4 STD (b) (b) -cpu_d<0> 5 0 0 0 FB1_5 STD 2 I/O I/O -cpu_d<1> 4 0 0 1 FB1_6 STD 3 I/O I/O -tmo 5 0 0 0 FB1_7 STD (b) (b) -cpu_d<2> 4 0 0 1 FB1_8 STD 4 I/O I/O -slaveinten 5 0 0 0 FB1_9 STD 5 GCK/I/O I -frx 5 0 0 0 FB1_10 STD (b) (b) -ece 5 0 0 0 FB1_11 STD 6 GCK/I/O GCK/I -divisor<2> 5 0 0 0 FB1_12 STD (b) (b) -divisor<1> 5 0 0 0 FB1_13 STD (b) (b) -divisor<0> 5 0 0 0 FB1_14 STD 7 GCK/I/O I -cpu_d<3> 3 0 0 2 FB1_15 STD 8 I/O I/O -cpol 5 0 0 0 FB1_16 STD (b) (b) -cpu_d<4> 5 0 0 0 FB1_17 STD 9 I/O I/O -cpha 5 0 0 0 FB1_18 STD (b) (b) - -Signals Used by Logic in Function Block - 1: cpu_d<0>.PIN 12: cpu_a<1> 22: spidatain<0> - 2: cpu_d<1>.PIN 13: cpu_rnw 23: spidatain<1> - 3: cpu_d<2>.PIN 14: divisor<0> 24: spidatain<2> - 4: cpu_d<3>.PIN 15: divisor<1> 25: spidatain<3> - 5: cpu_d<4>.PIN 16: divisor<2> 26: spidatain<4> - 6: Ncs2 17: ece 27: spidataout<0> - 7: cpha 18: frx 28: spidataout<1> - 8: cpol 19: slaveinten 29: spidataout<2> - 9: cpu_Nphi2 20: spi_Nsel 30: spidataout<3> - 10: cpu_Nres 21: spi_int 31: tmo - 11: cpu_a<0> - -Signal 1 2 3 4 Signals FB -Name 0----+----0----+----0----+----0----+----0 Used Inputs -spidataout<3> ...X.X...XXXX................X.......... 7 7 -spidataout<2> ..X..X...XXXX...............X........... 7 7 -spidataout<1> .X...X...XXXX..............X............ 7 7 -spidataout<0> X....X...XXXX.............X............. 7 7 -cpu_d<0> .....XX.X.XXXX.....X.X.................. 9 9 -cpu_d<1> .....X.XX.XXX.X.......X................. 8 8 -tmo ...X.X...XXXX.................X......... 7 7 -cpu_d<2> .....X..X.XXX..XX......X................ 8 8 -slaveinten ....XX...XXXX.....X..................... 7 7 -frx ....XX...XXXX....X...................... 7 7 -ece ..X..X...XXXX...X....................... 7 7 -divisor<2> ..X..X...XXXX..X........................ 7 7 -divisor<1> .X...X...XXXX.X......................... 7 7 -divisor<0> X....X...XXXXX.......................... 7 7 -cpu_d<3> .....X..X.XXX...........X.....X......... 7 7 -cpol .X...X.X.XXXX........................... 7 7 -cpu_d<4> .....X..X.XXX....XX.X....X.............. 9 9 -cpha X....XX..XXXX........................... 7 7 - 0----+----1----+----2----+----3----+----4 - 0 0 0 0 -Legend: -Total Pt - Total product terms used by the macrocell signal -Imp Pt - Product terms imported from other macrocells -Exp Pt - Product terms exported to other macrocells - in direction shown -Unused Pt - Unused local product terms remaining in macrocell -Loc - Location where logic was mapped in device -Pwr Mode - Macrocell power mode -Pin Type/Use - I - Input GCK - Global Clock - O - Output GTS - Global Output Enable - (b) - Buried macrocell GSR - Global Set/Reset -X(@) - Signal used as input (wire-AND input) to the macrocell logic. - The number of Signals Used may exceed the number of FB Inputs Used due - to wire-ANDing in the switch matrix. - *********************************** FB2 *********************************** -Number of function block inputs used/remaining: 31/23 -Number of signals used by logic mapping into function block: 31 -Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin -Name Pt Pt Pt Pt Mode # Type Use -(unused) 0 0 \/5 0 FB2_1 (b) (b) -spi_mosi 11 6<- 0 0 FB2_2 STD 35 I/O O -shifting2 2 0 /\1 2 FB2_3 STD (b) (b) -tc 3 0 0 2 FB2_4 STD (b) (b) -shiftcnt<0> 3 0 0 2 FB2_5 STD 36 I/O I -$OpTx$INV$24__$INT 3 0 0 2 FB2_6 STD 37 I/O I -spidatain<7> 4 0 0 1 FB2_7 STD (b) (b) -spidatain<6> 4 0 0 1 FB2_8 STD 38 I/O I -cpu_Nirq 1 0 0 4 FB2_9 STD 39 GSR/I/O O -spidatain<5> 4 0 0 1 FB2_10 STD (b) (b) -spidatain<4> 4 0 0 1 FB2_11 STD 40 GTS/I/O I -spidatain<3> 4 0 0 1 FB2_12 STD (b) (b) -spidatain<2> 4 0 0 1 FB2_13 STD (b) (b) -(unused) 0 0 0 5 FB2_14 42 GTS/I/O I -(unused) 0 0 0 5 FB2_15 43 I/O I -(unused) 0 0 0 5 FB2_16 (b) -(unused) 0 0 0 5 FB2_17 44 I/O I -start_shifting/start_shifting_RSTF__$INT - 1 0 0 4 FB2_18 STD (b) (b) - -Signals Used by Logic in Function Block - 1: $OpTx$INV$24__$INT - 12: shiftcnt<2> 22: spidataout<0> - 2: Ncs2 13: shiftcnt<3> 23: spidataout<1> - 3: cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST - 14: shiftdone 24: spidataout<2> - 4: cpu_Nphi2 15: shifting2 25: spidataout<3> - 5: cpu_Nres 16: spidatain<1> 26: spidataout<4> - 6: cpu_a<0> 17: spidatain<2> 27: spidataout<5> - 7: cpu_a<1> 18: spidatain<3> 28: spidataout<6> - 8: ece 19: spidatain<4> 29: spidataout<7> - 9: extclk 20: spidatain<5> 30: start_shifting - 10: shiftcnt<0> 21: spidatain<6> 31: tmo - 11: shiftcnt<1> - -Signal 1 2 3 4 Signals FB -Name 0----+----0----+----0----+----0----+----0 Used Inputs -spi_mosi X...X.....XXXXX......XXXXXXXX.X......... 16 16 -shifting2 X............X...............X.......... 3 3 -tc .X...XX......X.......................... 4 4 -shiftcnt<0> X...X....X....X......................... 4 4 -$OpTx$INV$24__$INT ...X...XX.....X..............X.......... 5 5 -spidatain<7> X...X....X....X.....X................... 5 5 -spidatain<6> X...X....X....X....X.................... 5 5 -cpu_Nirq ..X..................................... 1 1 -spidatain<5> X...X....X....X...X..................... 5 5 -spidatain<4> X...X....X....X..X...................... 5 5 -spidatain<3> X...X....X....X.X....................... 5 5 -spidatain<2> X...X....X....XX........................ 5 5 -start_shifting/start_shifting_RSTF__$INT - ....X........X.......................... 2 2 - 0----+----1----+----2----+----3----+----4 - 0 0 0 0 -Legend: -Total Pt - Total product terms used by the macrocell signal -Imp Pt - Product terms imported from other macrocells -Exp Pt - Product terms exported to other macrocells - in direction shown -Unused Pt - Unused local product terms remaining in macrocell -Loc - Location where logic was mapped in device -Pwr Mode - Macrocell power mode -Pin Type/Use - I - Input GCK - Global Clock - O - Output GTS - Global Output Enable - (b) - Buried macrocell GSR - Global Set/Reset -X(@) - Signal used as input (wire-AND input) to the macrocell logic. - The number of Signals Used may exceed the number of FB Inputs Used due - to wire-ANDing in the switch matrix. - *********************************** FB3 *********************************** -Number of function block inputs used/remaining: 20/34 -Number of signals used by logic mapping into function block: 20 -Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin -Name Pt Pt Pt Pt Mode # Type Use -(unused) 0 0 0 5 FB3_1 (b) -cpu_d<5> 4 0 0 1 FB3_2 STD 11 I/O I/O -(unused) 0 0 0 5 FB3_3 (b) -(unused) 0 0 0 5 FB3_4 (b) -cpu_d<6> 3 0 0 2 FB3_5 STD 12 I/O I/O -(unused) 0 0 0 5 FB3_6 (b) -(unused) 0 0 0 5 FB3_7 (b) -cpu_d<7> 3 0 0 2 FB3_8 STD 13 I/O I/O -noe 2 0 0 3 FB3_9 STD 14 I/O O -(unused) 0 0 0 5 FB3_10 (b) -(unused) 0 0 0 5 FB3_11 18 I/O I -(unused) 0 0 0 5 FB3_12 (b) -(unused) 0 0 0 5 FB3_13 (b) -(unused) 0 0 0 5 FB3_14 19 I/O I -ng 1 0 0 4 FB3_15 STD 20 I/O O -(unused) 0 0 0 5 FB3_16 24 I/O I -add_dec/XLXN_11 1 0 0 4 FB3_17 STD 22 I/O I -cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST - 2 0 0 3 FB3_18 STD (b) (b) - -Signals Used by Logic in Function Block - 1: Ncs2 8: cpu_a<1> 15: spi_int - 2: a10 9: cpu_rnw 16: spidatain<5> - 3: a8 10: ier 17: spidatain<6> - 4: a9 11: nio_sel 18: spidatain<7> - 5: add_dec/XLXN_11 12: nio_stb 19: start_shifting - 6: cpu_Nphi2 13: shifting2 20: tc - 7: cpu_a<0> 14: slaveinten - -Signal 1 2 3 4 Signals FB -Name 0----+----0----+----0----+----0----+----0 Used Inputs -cpu_d<5> X....XXXX...X..X..X..................... 8 8 -cpu_d<6> X....XXXXX......X....................... 7 7 -cpu_d<7> X....XXXX........X.X.................... 7 7 -noe ....X.....XX............................ 3 3 -ng X.........XX............................ 3 3 -add_dec/XLXN_11 .XXX.......X............................ 4 4 -cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST - .........X...XX....X.................... 4 4 - 0----+----1----+----2----+----3----+----4 - 0 0 0 0 -Legend: -Total Pt - Total product terms used by the macrocell signal -Imp Pt - Product terms imported from other macrocells -Exp Pt - Product terms exported to other macrocells - in direction shown -Unused Pt - Unused local product terms remaining in macrocell -Loc - Location where logic was mapped in device -Pwr Mode - Macrocell power mode -Pin Type/Use - I - Input GCK - Global Clock - O - Output GTS - Global Output Enable - (b) - Buried macrocell GSR - Global Set/Reset -X(@) - Signal used as input (wire-AND input) to the macrocell logic. - The number of Signals Used may exceed the number of FB Inputs Used due - to wire-ANDing in the switch matrix. - *********************************** FB4 *********************************** -Number of function block inputs used/remaining: 34/20 -Number of signals used by logic mapping into function block: 34 -Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin -Name Pt Pt Pt Pt Mode # Type Use -shiftdone 3 0 0 2 FB4_1 STD (b) (b) -b8 1 0 0 4 FB4_2 STD 25 I/O O -start_shifting 4 0 0 1 FB4_3 STD (b) (b) -spidataout<7> 4 0 0 1 FB4_4 STD (b) (b) -b9 1 0 0 4 FB4_5 STD 26 I/O O -spidataout<6> 4 0 0 1 FB4_6 STD (b) (b) -spidataout<5> 4 0 0 1 FB4_7 STD (b) (b) -b10 1 0 0 4 FB4_8 STD 27 I/O O -spidataout<4> 4 0 0 1 FB4_9 STD (b) (b) -spidatain<1> 4 0 0 1 FB4_10 STD (b) (b) -spi_Nsel 5 0 0 0 FB4_11 STD 28 I/O O -spidatain<0> 4 0 0 1 FB4_12 STD (b) (b) -shiftcnt<3> 4 0 0 1 FB4_13 STD (b) (b) -led 1 0 0 4 FB4_14 STD 29 I/O O -shiftcnt<2> 4 0 0 1 FB4_15 STD 33 I/O (b) -shiftcnt<1> 4 0 \/1 0 FB4_16 STD (b) (b) -spi_sclk 6 1<- 0 0 FB4_17 STD 34 I/O O -ier 5 0 0 0 FB4_18 STD (b) (b) - -Signals Used by Logic in Function Block - 1: $OpTx$INV$24__$INT - 13: cpu_Nres 24: shiftdone - 2: cpu_d<0>.PIN 14: cpu_a<0> 25: shifting2 - 3: cpu_d<4>.PIN 15: cpu_a<1> 26: spi_Nsel - 4: cpu_d<5>.PIN 16: cpu_rnw 27: spi_miso - 5: cpu_d<6>.PIN 17: frx 28: spidatain<0> - 6: cpu_d<7>.PIN 18: ier 29: spidataout<4> - 7: Ncs2 19: nio_sel 30: spidataout<5> - 8: a10 20: shiftcnt<0> 31: spidataout<6> - 9: a8 21: shiftcnt<1> 32: spidataout<7> - 10: a9 22: shiftcnt<2> 33: start_shifting - 11: cpha 23: shiftcnt<3> 34: start_shifting/start_shifting_RSTF__$INT - 12: cpol - -Signal 1 2 3 4 Signals FB -Name 0----+----0----+----0----+----0----+----0 Used Inputs -shiftdone X...........X......XXXX................. 6 6 -b8 ........X.........X..................... 2 2 -start_shifting ......X......XXXX...............XX...... 7 7 -spidataout<7> .....XX.....XXXX...............X........ 7 7 -b9 .........X........X..................... 2 2 -spidataout<6> ....X.X.....XXXX..............X......... 7 7 -spidataout<5> ...X..X.....XXXX.............X.......... 7 7 -b10 .......X..........X..................... 2 2 -spidataout<4> ..X...X.....XXXX............X........... 7 7 -spidatain<1> X...........X......X....X..X............ 5 5 -spi_Nsel .X....X.....XXXX.........X.............. 7 7 -spidatain<0> X...........X......X....XXX............. 6 6 -shiftcnt<3> X...........X......XXXX.X............... 7 7 -led ........................XX......X....... 3 3 -shiftcnt<2> X...........X......XXX..X............... 6 6 -shiftcnt<1> X...........X......XX...X............... 5 5 -spi_sclk X.........XXX......X...XX............... 7 7 -ier ....X.X.....XXXX.X...................... 7 7 - 0----+----1----+----2----+----3----+----4 - 0 0 0 0 -Legend: -Total Pt - Total product terms used by the macrocell signal -Imp Pt - Product terms imported from other macrocells -Exp Pt - Product terms exported to other macrocells - in direction shown -Unused Pt - Unused local product terms remaining in macrocell -Loc - Location where logic was mapped in device -Pwr Mode - Macrocell power mode -Pin Type/Use - I - Input GCK - Global Clock - O - Output GTS - Global Output Enable - (b) - Buried macrocell GSR - Global Set/Reset -X(@) - Signal used as input (wire-AND input) to the macrocell logic. - The number of Signals Used may exceed the number of FB Inputs Used due - to wire-ANDing in the switch matrix. - ;;-----------------------------------------------------------------;; -; Implemented Equations. - - -$OpTx$INV$24__$INT <= ((ece AND NOT extclk) - OR (NOT ece AND NOT cpu_Nphi2) - OR (NOT start_shifting AND NOT shifting2)); - - - -FDCPE_add_dec/XLXN_11: FDCPE port map (add_dec/XLXN_11,add_dec/XLXN_11_D,extclk,'0','0'); -add_dec/XLXN_11_D <= (NOT nio_stb AND a9 AND a8 AND a10); - - -b10 <= (a10 AND nio_sel); - - -b8 <= (a8 AND nio_sel); - - -b9 <= (a9 AND nio_sel); - -FTCPE_cpha: FTCPE port map (cpha,cpha_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw); -cpha_T <= ((cpha AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN) - OR (NOT cpha AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN)); - -FTCPE_cpol: FTCPE port map (cpol,cpol_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw); -cpol_T <= ((cpol AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(1).PIN) - OR (NOT cpol AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(1).PIN)); - - -cpu_Nirq_I <= '0'; -cpu_Nirq <= cpu_Nirq_I when cpu_Nirq_OE = '1' else 'Z'; -cpu_Nirq_OE <= cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST; - - -cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST <= ((ier AND tc) - OR (slaveinten AND NOT spi_int)); - -FTCPE_divisor0: FTCPE port map (divisor(0),divisor_T(0),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw); -divisor_T(0) <= ((divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(0).PIN) - OR (NOT divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(0).PIN)); - -FTCPE_divisor1: FTCPE port map (divisor(1),divisor_T(1),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw); -divisor_T(1) <= ((divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(1).PIN) - OR (NOT divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(1).PIN)); - -FTCPE_divisor2: FTCPE port map (divisor(2),divisor_T(2),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw); -divisor_T(2) <= ((divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(2).PIN) - OR (NOT divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(2).PIN)); - -FTCPE_ece: FTCPE port map (ece,ece_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw); -ece_T <= ((ece AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(2).PIN) - OR (NOT ece AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(2).PIN)); - -FTCPE_frx: FTCPE port map (frx,frx_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw); -frx_T <= ((frx AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN) - OR (NOT frx AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN)); - -FTCPE_ier: FTCPE port map (ier,ier_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw); -ier_T <= ((ier AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(6).PIN) - OR (NOT ier AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(6).PIN)); - - -cpu_d_I(0) <= ((NOT Ncs2 AND cpu_rnw AND spi_Nsel AND cpu_a(1) AND - cpu_a(0) AND cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND cpha AND NOT cpu_a(1) AND cpu_a(0) AND - cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND divisor(0) AND cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND spidatain(0) AND NOT cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2)); -cpu_d(0) <= cpu_d_I(0) when cpu_d_OE(0) = '1' else 'Z'; -cpu_d_OE(0) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2); - - -cpu_d_I(1) <= ((NOT Ncs2 AND cpu_rnw AND cpol AND NOT cpu_a(1) AND cpu_a(0) AND - cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND divisor(1) AND cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND spidatain(1) AND NOT cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2)); -cpu_d(1) <= cpu_d_I(1) when cpu_d_OE(1) = '1' else 'Z'; -cpu_d_OE(1) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2); - - -cpu_d_I(2) <= ((NOT Ncs2 AND cpu_rnw AND ece AND NOT cpu_a(1) AND cpu_a(0) AND - cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND divisor(2) AND cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND spidatain(2) AND NOT cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2)); -cpu_d(2) <= cpu_d_I(2) when cpu_d_OE(2) = '1' else 'Z'; -cpu_d_OE(2) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2); - - -cpu_d_I(3) <= ((NOT Ncs2 AND cpu_rnw AND tmo AND NOT cpu_a(1) AND cpu_a(0) AND - cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND spidatain(3) AND NOT cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2)); -cpu_d(3) <= cpu_d_I(3) when cpu_d_OE(3) = '1' else 'Z'; -cpu_d_OE(3) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2); - - -cpu_d_I(4) <= ((NOT Ncs2 AND cpu_rnw AND frx AND NOT cpu_a(1) AND cpu_a(0) AND - cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND slaveinten AND cpu_a(1) AND - cpu_a(0) AND cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND spidatain(4) AND NOT cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND NOT spi_int AND - cpu_Nphi2)); -cpu_d(4) <= cpu_d_I(4) when cpu_d_OE(4) = '1' else 'Z'; -cpu_d_OE(4) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2); - - -cpu_d_I(5) <= ((NOT Ncs2 AND cpu_rnw AND spidatain(5) AND NOT cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND start_shifting AND - cpu_a(0) AND cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND cpu_a(0) AND - shifting2 AND cpu_Nphi2)); -cpu_d(5) <= cpu_d_I(5) when cpu_d_OE(5) = '1' else 'Z'; -cpu_d_OE(5) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2); - - -cpu_d_I(6) <= ((NOT Ncs2 AND cpu_rnw AND ier AND NOT cpu_a(1) AND cpu_a(0) AND - cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND spidatain(6) AND NOT cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2)); -cpu_d(6) <= cpu_d_I(6) when cpu_d_OE(6) = '1' else 'Z'; -cpu_d_OE(6) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2); - - -cpu_d_I(7) <= ((NOT Ncs2 AND cpu_rnw AND spidatain(7) AND NOT cpu_a(1) AND - NOT cpu_a(0) AND cpu_Nphi2) - OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND tc AND cpu_a(0) AND - cpu_Nphi2)); -cpu_d(7) <= cpu_d_I(7) when cpu_d_OE(7) = '1' else 'Z'; -cpu_d_OE(7) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2); - -FDCPE_spi_mosi: FDCPE port map (spi_mosi_I,spi_mosi,NOT $OpTx$INV$24__$INT,'0',NOT cpu_Nres); -spi_mosi <= ((EXP6_.EXP) - OR (shifting2.EXP) - OR (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(1) AND - NOT shiftdone AND NOT spidataout(0) AND shifting2) - OR (NOT shiftcnt(3) AND shiftcnt(2) AND shiftcnt(1) AND - NOT shiftdone AND NOT spidataout(4) AND shifting2)); -spi_mosi <= spi_mosi_I when spi_mosi_OE = '1' else 'Z'; -spi_mosi_OE <= NOT tmo; - -FDCPE_spi_sclk: FDCPE port map (spi_sclk,spi_sclk_D,NOT $OpTx$INV$24__$INT,spi_sclk_CLR,spi_sclk_PRE); -spi_sclk_D <= cpol - XOR -spi_sclk_D <= ((shiftcnt(1).EXP) - OR (cpu_Nres AND NOT cpha AND shiftcnt(0) AND NOT shiftdone AND - shifting2)); -spi_sclk_CLR <= (NOT cpu_Nres AND NOT cpol); -spi_sclk_PRE <= (NOT cpu_Nres AND cpol); - - -led <= (spi_Nsel AND NOT start_shifting AND NOT shifting2); - - -ng <= (Ncs2 AND nio_stb AND nio_sel); - - -noe <= NOT (((NOT nio_stb AND add_dec/XLXN_11) - OR (NOT nio_sel AND add_dec/XLXN_11))); - -FDCPE_shiftcnt0: FDCPE port map (shiftcnt(0),shiftcnt_D(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0'); -shiftcnt_D(0) <= (NOT shiftcnt(0) AND shifting2); - -FDCPE_shiftcnt1: FDCPE port map (shiftcnt(1),shiftcnt_D(1),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0'); -shiftcnt_D(1) <= ((shiftcnt(0) AND NOT shiftcnt(1) AND shifting2) - OR (NOT shiftcnt(0) AND shiftcnt(1) AND shifting2)); - -FTCPE_shiftcnt2: FTCPE port map (shiftcnt(2),shiftcnt_T(2),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0'); -shiftcnt_T(2) <= ((shiftcnt(2) AND NOT shifting2) - OR (shiftcnt(0) AND shiftcnt(1) AND shifting2)); - -FTCPE_shiftcnt3: FTCPE port map (shiftcnt(3),shiftcnt_T(3),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0'); -shiftcnt_T(3) <= ((shiftcnt(3) AND NOT shifting2) - OR (shiftcnt(2) AND shiftcnt(0) AND shiftcnt(1) AND - shifting2)); - -FDCPE_shiftdone: FDCPE port map (shiftdone,shiftdone_D,NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0'); -shiftdone_D <= (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(0) AND - shiftcnt(1)); - -FDCPE_shifting2: FDCPE port map (shifting2,shifting2_D,NOT $OpTx$INV$24__$INT,'0','0'); -shifting2_D <= (NOT shiftdone AND start_shifting); - -FTCPE_slaveinten: FTCPE port map (slaveinten,slaveinten_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw); -slaveinten_T <= ((slaveinten AND cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN) - OR (NOT slaveinten AND cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN)); - -FTCPE_spi_Nsel: FTCPE port map (spi_Nsel,spi_Nsel_T,Ncs2,'0',NOT cpu_Nres,NOT cpu_rnw); -spi_Nsel_T <= ((spi_Nsel AND cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN) - OR (NOT spi_Nsel AND cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN)); - -FDCPE_spidatain0: FDCPE port map (spidatain(0),spidatain_D(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(0)); -spidatain_D(0) <= (NOT spi_Nsel AND spi_miso); -spidatain_CE(0) <= (shiftcnt(0) AND shifting2); - -FDCPE_spidatain1: FDCPE port map (spidatain(1),spidatain(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(1)); -spidatain_CE(1) <= (shiftcnt(0) AND shifting2); - -FDCPE_spidatain2: FDCPE port map (spidatain(2),spidatain(1),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(2)); -spidatain_CE(2) <= (shiftcnt(0) AND shifting2); - -FDCPE_spidatain3: FDCPE port map (spidatain(3),spidatain(2),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(3)); -spidatain_CE(3) <= (shiftcnt(0) AND shifting2); - -FDCPE_spidatain4: FDCPE port map (spidatain(4),spidatain(3),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(4)); -spidatain_CE(4) <= (shiftcnt(0) AND shifting2); - -FDCPE_spidatain5: FDCPE port map (spidatain(5),spidatain(4),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(5)); -spidatain_CE(5) <= (shiftcnt(0) AND shifting2); - -FDCPE_spidatain6: FDCPE port map (spidatain(6),spidatain(5),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(6)); -spidatain_CE(6) <= (shiftcnt(0) AND shifting2); - -FDCPE_spidatain7: FDCPE port map (spidatain(7),spidatain(6),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(7)); -spidatain_CE(7) <= (shiftcnt(0) AND shifting2); - -FTCPE_spidataout0: FTCPE port map (spidataout(0),spidataout_T(0),Ncs2,'0','0',spidataout_CE(0)); -spidataout_T(0) <= ((NOT cpu_a(1) AND spidataout(0) AND NOT cpu_a(0) AND - NOT cpu_d(0).PIN) - OR (NOT cpu_a(1) AND NOT spidataout(0) AND NOT cpu_a(0) AND - cpu_d(0).PIN)); -spidataout_CE(0) <= (cpu_Nres AND NOT cpu_rnw); - -FTCPE_spidataout1: FTCPE port map (spidataout(1),spidataout_T(1),Ncs2,'0','0',spidataout_CE(1)); -spidataout_T(1) <= ((NOT cpu_a(1) AND spidataout(1) AND NOT cpu_a(0) AND - NOT cpu_d(1).PIN) - OR (NOT cpu_a(1) AND NOT spidataout(1) AND NOT cpu_a(0) AND - cpu_d(1).PIN)); -spidataout_CE(1) <= (cpu_Nres AND NOT cpu_rnw); - -FTCPE_spidataout2: FTCPE port map (spidataout(2),spidataout_T(2),Ncs2,'0','0',spidataout_CE(2)); -spidataout_T(2) <= ((NOT cpu_a(1) AND spidataout(2) AND NOT cpu_a(0) AND - NOT cpu_d(2).PIN) - OR (NOT cpu_a(1) AND NOT spidataout(2) AND NOT cpu_a(0) AND - cpu_d(2).PIN)); -spidataout_CE(2) <= (cpu_Nres AND NOT cpu_rnw); - -FTCPE_spidataout3: FTCPE port map (spidataout(3),spidataout_T(3),Ncs2,'0','0',spidataout_CE(3)); -spidataout_T(3) <= ((NOT cpu_a(1) AND spidataout(3) AND NOT cpu_a(0) AND - NOT cpu_d(3).PIN) - OR (NOT cpu_a(1) AND NOT spidataout(3) AND NOT cpu_a(0) AND - cpu_d(3).PIN)); -spidataout_CE(3) <= (cpu_Nres AND NOT cpu_rnw); - -FTCPE_spidataout4: FTCPE port map (spidataout(4),spidataout_T(4),Ncs2,'0','0',spidataout_CE(4)); -spidataout_T(4) <= ((NOT cpu_a(1) AND spidataout(4) AND NOT cpu_a(0) AND - NOT cpu_d(4).PIN) - OR (NOT cpu_a(1) AND NOT spidataout(4) AND NOT cpu_a(0) AND - cpu_d(4).PIN)); -spidataout_CE(4) <= (cpu_Nres AND NOT cpu_rnw); - -FTCPE_spidataout5: FTCPE port map (spidataout(5),spidataout_T(5),Ncs2,'0','0',spidataout_CE(5)); -spidataout_T(5) <= ((NOT cpu_a(1) AND spidataout(5) AND NOT cpu_a(0) AND - NOT cpu_d(5).PIN) - OR (NOT cpu_a(1) AND NOT spidataout(5) AND NOT cpu_a(0) AND - cpu_d(5).PIN)); -spidataout_CE(5) <= (cpu_Nres AND NOT cpu_rnw); - -FTCPE_spidataout6: FTCPE port map (spidataout(6),spidataout_T(6),Ncs2,'0','0',spidataout_CE(6)); -spidataout_T(6) <= ((NOT cpu_a(1) AND spidataout(6) AND NOT cpu_a(0) AND - NOT cpu_d(6).PIN) - OR (NOT cpu_a(1) AND NOT spidataout(6) AND NOT cpu_a(0) AND - cpu_d(6).PIN)); -spidataout_CE(6) <= (cpu_Nres AND NOT cpu_rnw); - -FTCPE_spidataout7: FTCPE port map (spidataout(7),spidataout_T(7),Ncs2,'0','0',spidataout_CE(7)); -spidataout_T(7) <= ((NOT cpu_a(1) AND spidataout(7) AND NOT cpu_a(0) AND - NOT cpu_d(7).PIN) - OR (NOT cpu_a(1) AND NOT spidataout(7) AND NOT cpu_a(0) AND - cpu_d(7).PIN)); -spidataout_CE(7) <= (cpu_Nres AND NOT cpu_rnw); - -FTCPE_start_shifting: FTCPE port map (start_shifting,start_shifting_T,Ncs2,NOT start_shifting/start_shifting_RSTF__$INT,'0'); -start_shifting_T <= ((NOT cpu_rnw AND NOT cpu_a(1) AND NOT start_shifting AND NOT cpu_a(0)) - OR (frx AND NOT cpu_a(1) AND NOT start_shifting AND NOT cpu_a(0))); - - -start_shifting/start_shifting_RSTF__$INT <= (cpu_Nres AND NOT shiftdone); - -FDCPE_tc: FDCPE port map (tc,'0',Ncs2,'0',shiftdone,tc_CE); -tc_CE <= (NOT cpu_a(1) AND NOT cpu_a(0)); - -FTCPE_tmo: FTCPE port map (tmo,tmo_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw); -tmo_T <= ((tmo AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(3).PIN) - OR (NOT tmo AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(3).PIN)); - -Register Legend: - FDCPE (Q,D,C,CLR,PRE,CE); - FTCPE (Q,D,C,CLR,PRE,CE); - LDCP (Q,D,G,CLR,PRE); - - **************************** Device Pin Out **************************** - -Device : XC9572XL-10-PC44 - - - -------------------------------- - /6 5 4 3 2 1 44 43 42 41 40 \ - | 7 39 | - | 8 38 | - | 9 37 | - | 10 36 | - | 11 XC9572XL-10-PC44 35 | - | 12 34 | - | 13 33 | - | 14 32 | - | 15 31 | - | 16 30 | - | 17 29 | - \ 18 19 20 21 22 23 24 25 26 27 28 / - -------------------------------- - - -Pin Signal Pin Signal -No. Name No. Name - 1 TIE 23 GND - 2 cpu_d<0> 24 cpu_a<1> - 3 cpu_d<1> 25 b8 - 4 cpu_d<2> 26 b9 - 5 cpu_Nphi2 27 b10 - 6 extclk 28 spi_Nsel - 7 cpu_rnw 29 led - 8 cpu_d<3> 30 TDO - 9 cpu_d<4> 31 GND - 10 GND 32 VCC - 11 cpu_d<5> 33 TIE - 12 cpu_d<6> 34 spi_sclk - 13 cpu_d<7> 35 spi_mosi - 14 noe 36 a8 - 15 TDI 37 a9 - 16 TMS 38 a10 - 17 TCK 39 cpu_Nirq - 18 Ncs2 40 nio_sel - 19 cpu_Nres 41 VCC - 20 ng 42 spi_int - 21 VCC 43 nio_stb - 22 cpu_a<0> 44 spi_miso - - -Legend : NC = Not Connected, unbonded pin - PGND = Unused I/O configured as additional Ground pin - TIE = Unused I/O floating -- must tie to VCC, GND or other signal - VCC = Dedicated Power Pin - GND = Dedicated Ground Pin - TDI = Test Data In, JTAG pin - TDO = Test Data Out, JTAG pin - TCK = Test Clock, JTAG pin - TMS = Test Mode Select, JTAG pin - PE = Port Enable pin - PROHIBITED = User reserved pin - **************************** Compiler Options **************************** - -Following is a list of all global compiler options used by the fitter run. - -Device(s) Specified : xc9572xl-10-PC44 -Optimization Method : SPEED -Multi-Level Logic Optimization : ON -Ignore Timing Specifications : OFF -Default Register Power Up Value : LOW -Keep User Location Constraints : ON -What-You-See-Is-What-You-Get : OFF -Exhaustive Fitting : OFF -Keep Unused Inputs : OFF -Slew Rate : FAST -Power Mode : STD -Set Unused I/O Pin Termination : FLOAT -Set I/O Pin Termination : KEEPER -Global Clock Optimization : ON -Global Set/Reset Optimization : ON -Global Ouput Enable Optimization : ON -Input Limit : 54 -Pterm Limit : 25 diff --git a/VHDL/spi6502b.vm6 b/VHDL/spi6502b.vm6 deleted file mode 100644 index cd64402..0000000 --- a/VHDL/spi6502b.vm6 +++ /dev/null @@ -1,3543 +0,0 @@ -NDS Database: version G.38 - -NDS_INFO | xc9500xl | 9572XL44PC | XC9572XL-10-PC44 - -DEVICE | 9572XL | 9572XL44PC | - -NETWORK | spi6502b | 0 | 0 | 16391 - -INPUT_INSTANCE | 0 | 0 | NULL | cpu_Nres_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_Nres | 4234 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | Inv+PrldLow+PinTrst+OptxMapped | int_mosi | spi6502b_COPY_0_COPY_0 | 2155889920 | 12 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<4> | 4177 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<0> | 4173 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | EXP6_.EXP | 4588 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2.EXP | 4589 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | int_mosi | 4127 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.Q | int_mosi | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 2 | 0 | MC_OE -NODE | int_mosi$OE | 4128 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.BUFOE.OUT | int_mosi | 2 | 0 | MC_OE - -SIGNAL_INSTANCE | int_mosi.SI | int_mosi | 0 | 12 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<4> | 4177 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<0> | 4173 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | EXP6_.EXP | 4588 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2.EXP | 4589 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | int_mosi.D1 | 4249 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | int_mosi.D2 | 4250 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 1 | IV_TRUE | EXP6_.EXP -SPPTERM | 1 | IV_TRUE | shifting2.EXP -SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<0> | IV_TRUE | shifting2 -SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<4> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | int_mosi.CLKF | 4251 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF -SIGNAL | NODE | int_mosi.SETF | 4252 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 5 | 9 | MC_SI_SETF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST -SIGNAL | NODE | int_mosi.TRST | 4254 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 1 | IV_FALSE | tmo - -SRFF_INSTANCE | int_mosi.REG | int_mosi | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | int_mosi.D | 4248 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | int_mosi.CLKF | 4251 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 2 | 8 | SRFF_S -SIGNAL | NODE | int_mosi.SETF | 4252 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 5 | 9 | MC_SI_SETF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | int_mosi.Q | 4255 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.REG | 0 | 8 | SRFF_Q - -BUF_INSTANCE | int_mosi.BUFOE | int_mosi | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN -SIGNAL | NODE | int_mosi.TRST | 4254 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 1 | IV_FALSE | tmo -OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT -NODE | int_mosi.BUFOE.OUT | 4253 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.BUFOE | 0 | 10 | BUF_OUT - -INPUT_INSTANCE | 0 | 0 | NULL | Ncs2_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | Ncs2 | 4235 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX - -INPUT_INSTANCE | 0 | 0 | NULL | cpu_rnw_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_rnw | 4236 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX - -INPUT_INSTANCE | 0 | 0 | NULL | N3017 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_d<0> | 4221 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<0> | 0 | 6 | OI_OUT -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX - -INPUT_INSTANCE | 0 | 0 | NULL | cpu_a_0_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_a<0> | 4244 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX - -INPUT_INSTANCE | 0 | 0 | NULL | cpu_a_1_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_a<1> | 4242 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | slavesel | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | slavesel$Q | 4131 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | slavesel.SI | slavesel | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | slavesel.D1 | 4257 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | slavesel.D2 | 4258 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | slavesel | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3017 -SPPTERM | 4 | IV_FALSE | slavesel | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3017 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | slavesel.CLKF | 4259 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF -SIGNAL | NODE | slavesel.SETF | 4260 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 5 | 9 | MC_SI_SETF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | slavesel.CE | 4261 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | slavesel.REG | slavesel | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | slavesel.D | 4256 | ? | 0 | 0 | slavesel | NULL | NULL | slavesel.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | slavesel.CLKF | 4259 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 2 | 8 | SRFF_S -SIGNAL | NODE | slavesel.SETF | 4260 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 5 | 9 | MC_SI_SETF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | slavesel.CE | 4261 | ? | 0 | 4096 | slavesel | NULL | NULL | slavesel.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | slavesel.Q | 4262 | ? | 0 | 0 | slavesel | NULL | NULL | slavesel.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | N3019 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_d<1> | 4222 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<1> | 0 | 6 | OI_OUT -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | cpol | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | cpol.SI | cpol | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | cpol.D1 | 4264 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | cpol.D2 | 4265 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3019 -SPPTERM | 4 | IV_FALSE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3019 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | cpol.CLKF | 4266 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | cpol.RSTF | 4267 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | cpol.CE | 4268 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | cpol.REG | cpol | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | cpol.D | 4263 | ? | 0 | 0 | cpol | NULL | NULL | cpol.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | cpol.CLKF | 4266 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | cpol.RSTF | 4267 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | cpol.CE | 4268 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | cpol.Q | 4269 | ? | 0 | 0 | cpol | NULL | NULL | cpol.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | N3021 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_d<2> | 4223 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<2> | 0 | 6 | OI_OUT -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | ece | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | ece.SI | ece | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | ece.D1 | 4271 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | ece.D2 | 4272 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3021 -SPPTERM | 4 | IV_FALSE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3021 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | ece.CLKF | 4273 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | ece.RSTF | 4274 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | ece.CE | 4275 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | ece.REG | ece | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | ece.D | 4270 | ? | 0 | 0 | ece | NULL | NULL | ece.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | ece.CLKF | 4273 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | ece.RSTF | 4274 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | ece.CE | 4275 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | ece.Q | 4276 | ? | 0 | 0 | ece | NULL | NULL | ece.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | cpha | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | cpha.SI | cpha | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | cpha.D1 | 4278 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | cpha.D2 | 4279 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3017 -SPPTERM | 4 | IV_FALSE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3017 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | cpha.CLKF | 4280 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | cpha.RSTF | 4281 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | cpha.CE | 4282 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | cpha.REG | cpha | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | cpha.D | 4277 | ? | 0 | 0 | cpha | NULL | NULL | cpha.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | cpha.CLKF | 4280 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | cpha.RSTF | 4281 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | cpha.CE | 4282 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | cpha.Q | 4283 | ? | 0 | 0 | cpha | NULL | NULL | cpha.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | N3025 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_d<4> | 4224 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<4> | 0 | 6 | OI_OUT -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | frx | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | frx.SI | frx | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | frx.D1 | 4285 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | frx.D2 | 4286 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3025 -SPPTERM | 4 | IV_FALSE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3025 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | frx.CLKF | 4287 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | frx.RSTF | 4288 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | frx.CE | 4289 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | frx.REG | frx | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | frx.D | 4284 | ? | 0 | 0 | frx | NULL | NULL | frx.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | frx.CLKF | 4287 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | frx.RSTF | 4288 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | frx.CE | 4289 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | frx.Q | 4290 | ? | 0 | 0 | frx | NULL | NULL | frx.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | N3029 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_d<6> | 4218 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<6> | 0 | 6 | OI_OUT -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | N3029 | 4201 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3029 | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | ier | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3029 | 4201 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3029 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | ier.SI | ier | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3029 | 4201 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3029 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | ier.D1 | 4292 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | ier.D2 | 4293 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3029 -SPPTERM | 4 | IV_FALSE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3029 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | ier.CLKF | 4294 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | ier.RSTF | 4295 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | ier.CE | 4296 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | ier.REG | ier | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | ier.D | 4291 | ? | 0 | 0 | ier | NULL | NULL | ier.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | ier.CLKF | 4294 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | ier.RSTF | 4295 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | ier.CE | 4296 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | ier.Q | 4297 | ? | 0 | 0 | ier | NULL | NULL | ier.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | slaveinten | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | slaveinten.SI | slaveinten | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | slaveinten.D1 | 4299 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | slaveinten.D2 | 4300 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | slaveinten | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3025 -SPPTERM | 4 | IV_FALSE | slaveinten | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3025 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | slaveinten.CLKF | 4301 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | slaveinten.RSTF | 4302 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | slaveinten.CE | 4303 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | slaveinten.REG | slaveinten | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | slaveinten.D | 4298 | ? | 0 | 0 | slaveinten | NULL | NULL | slaveinten.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | slaveinten.CLKF | 4301 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | slaveinten.RSTF | 4302 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | slaveinten.CE | 4303 | ? | 0 | 4096 | slaveinten | NULL | NULL | slaveinten.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | slaveinten.Q | 4304 | ? | 0 | 0 | slaveinten | NULL | NULL | slaveinten.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | N3023 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_d<3> | 4216 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<3> | 0 | 6 | OI_OUT -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | N3023 | 4199 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3023 | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | tmo | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3023 | 4199 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3023 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | tmo.SI | tmo | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3023 | 4199 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3023 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | tmo.D1 | 4306 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | tmo.D2 | 4307 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3023 -SPPTERM | 4 | IV_FALSE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3023 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | tmo.CLKF | 4308 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | tmo.RSTF | 4309 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | tmo.CE | 4310 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | tmo.REG | tmo | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | tmo.D | 4305 | ? | 0 | 0 | tmo | NULL | NULL | tmo.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | tmo.CLKF | 4308 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | tmo.RSTF | 4309 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | tmo.CE | 4310 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | tmo.Q | 4311 | ? | 0 | 0 | tmo | NULL | NULL | tmo.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | divisor<0> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<0> | 4140 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | divisor<0> | 4140 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | divisor<0>.SI | divisor<0> | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<0> | 4140 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | divisor<0>.D1 | 4313 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | divisor<0>.D2 | 4314 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3017 -SPPTERM | 4 | IV_FALSE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3017 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | divisor<0>.CLKF | 4315 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | divisor<0>.RSTF | 4316 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | divisor<0>.CE | 4317 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | divisor<0>.REG | divisor<0> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | divisor<0>.D | 4312 | ? | 0 | 0 | divisor<0> | NULL | NULL | divisor<0>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | divisor<0>.CLKF | 4315 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | divisor<0>.RSTF | 4316 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | divisor<0>.CE | 4317 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | divisor<0>.Q | 4318 | ? | 0 | 0 | divisor<0> | NULL | NULL | divisor<0>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | divisor<1> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<1> | 4141 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | divisor<1> | 4141 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | divisor<1>.SI | divisor<1> | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<1> | 4141 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | divisor<1>.D1 | 4320 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | divisor<1>.D2 | 4321 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3019 -SPPTERM | 4 | IV_FALSE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3019 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | divisor<1>.CLKF | 4322 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | divisor<1>.RSTF | 4323 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | divisor<1>.CE | 4324 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | divisor<1>.REG | divisor<1> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | divisor<1>.D | 4319 | ? | 0 | 0 | divisor<1> | NULL | NULL | divisor<1>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | divisor<1>.CLKF | 4322 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | divisor<1>.RSTF | 4323 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | divisor<1>.CE | 4324 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | divisor<1>.Q | 4325 | ? | 0 | 0 | divisor<1> | NULL | NULL | divisor<1>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | divisor<2> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<2> | 4142 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | divisor<2> | 4142 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | divisor<2>.SI | divisor<2> | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<2> | 4142 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | divisor<2>.D1 | 4327 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | divisor<2>.D2 | 4328 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3021 -SPPTERM | 4 | IV_FALSE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3021 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | divisor<2>.CLKF | 4329 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | divisor<2>.RSTF | 4330 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | divisor<2>.CE | 4331 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | divisor<2>.REG | divisor<2> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | divisor<2>.D | 4326 | ? | 0 | 0 | divisor<2> | NULL | NULL | divisor<2>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | divisor<2>.CLKF | 4329 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | divisor<2>.RSTF | 4330 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | divisor<2>.CE | 4331 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | divisor<2>.Q | 4332 | ? | 0 | 0 | divisor<2> | NULL | NULL | divisor<2>.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | spi_miso_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | spi_miso | 4237 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | spi_miso_IBUF | 4143 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_IBUF | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<0> | spi6502b_COPY_0_COPY_0 | 2155873280 | 6 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spi_miso_IBUF | 4143 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidatain<0> | 4144 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidatain<0>.SI | spidatain<0> | 0 | 6 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spi_miso_IBUF | 4143 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidatain<0>.D1 | 4334 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidatain<0>.D2 | 4335 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_FALSE | slavesel | IV_TRUE | spi_miso_IBUF -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidatain<0>.CLKF | 4336 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | spidatain<0>.RSTF | 4337 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidatain<0>.CE | 4338 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 - -SRFF_INSTANCE | spidatain<0>.REG | spidatain<0> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidatain<0>.D | 4333 | ? | 0 | 0 | spidatain<0> | NULL | NULL | spidatain<0>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidatain<0>.CLKF | 4336 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | spidatain<0>.RSTF | 4337 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidatain<0>.CE | 4338 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidatain<0>.Q | 4339 | ? | 0 | 0 | spidatain<0> | NULL | NULL | spidatain<0>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<1> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<0> | 4144 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidatain<1> | 4145 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidatain<1>.SI | spidatain<1> | 0 | 5 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<0> | 4144 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidatain<1>.D1 | 4341 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidatain<1>.D2 | 4342 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 1 | IV_TRUE | spidatain<0> -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidatain<1>.CLKF | 4343 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | spidatain<1>.RSTF | 4344 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidatain<1>.CE | 4345 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 - -SRFF_INSTANCE | spidatain<1>.REG | spidatain<1> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidatain<1>.D | 4340 | ? | 0 | 0 | spidatain<1> | NULL | NULL | spidatain<1>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidatain<1>.CLKF | 4343 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | spidatain<1>.RSTF | 4344 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidatain<1>.CE | 4345 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidatain<1>.Q | 4346 | ? | 0 | 0 | spidatain<1> | NULL | NULL | spidatain<1>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<2> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<1> | 4145 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidatain<2> | 4146 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidatain<2>.SI | spidatain<2> | 0 | 5 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<1> | 4145 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidatain<2>.D1 | 4348 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidatain<2>.D2 | 4349 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 1 | IV_TRUE | spidatain<1> -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidatain<2>.CLKF | 4350 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | spidatain<2>.RSTF | 4351 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidatain<2>.CE | 4352 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 - -SRFF_INSTANCE | spidatain<2>.REG | spidatain<2> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidatain<2>.D | 4347 | ? | 0 | 0 | spidatain<2> | NULL | NULL | spidatain<2>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidatain<2>.CLKF | 4350 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | spidatain<2>.RSTF | 4351 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidatain<2>.CE | 4352 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidatain<2>.Q | 4353 | ? | 0 | 0 | spidatain<2> | NULL | NULL | spidatain<2>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<3> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<2> | 4146 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidatain<3> | 4147 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidatain<3>.SI | spidatain<3> | 0 | 5 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<2> | 4146 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidatain<3>.D1 | 4355 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidatain<3>.D2 | 4356 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 1 | IV_TRUE | spidatain<2> -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidatain<3>.CLKF | 4357 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | spidatain<3>.RSTF | 4358 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidatain<3>.CE | 4359 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 - -SRFF_INSTANCE | spidatain<3>.REG | spidatain<3> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidatain<3>.D | 4354 | ? | 0 | 0 | spidatain<3> | NULL | NULL | spidatain<3>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidatain<3>.CLKF | 4357 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | spidatain<3>.RSTF | 4358 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidatain<3>.CE | 4359 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidatain<3>.Q | 4360 | ? | 0 | 0 | spidatain<3> | NULL | NULL | spidatain<3>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<4> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<3> | 4147 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidatain<4> | 4148 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidatain<4>.SI | spidatain<4> | 0 | 5 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<3> | 4147 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidatain<4>.D1 | 4362 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidatain<4>.D2 | 4363 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 1 | IV_TRUE | spidatain<3> -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidatain<4>.CLKF | 4364 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | spidatain<4>.RSTF | 4365 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidatain<4>.CE | 4366 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 - -SRFF_INSTANCE | spidatain<4>.REG | spidatain<4> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidatain<4>.D | 4361 | ? | 0 | 0 | spidatain<4> | NULL | NULL | spidatain<4>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidatain<4>.CLKF | 4364 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | spidatain<4>.RSTF | 4365 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidatain<4>.CE | 4366 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidatain<4>.Q | 4367 | ? | 0 | 0 | spidatain<4> | NULL | NULL | spidatain<4>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<5> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<4> | 4148 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidatain<5> | 4149 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidatain<5>.SI | spidatain<5> | 0 | 5 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<4> | 4148 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidatain<5>.D1 | 4369 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidatain<5>.D2 | 4370 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 1 | IV_TRUE | spidatain<4> -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidatain<5>.CLKF | 4371 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | spidatain<5>.RSTF | 4372 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidatain<5>.CE | 4373 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 - -SRFF_INSTANCE | spidatain<5>.REG | spidatain<5> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidatain<5>.D | 4368 | ? | 0 | 0 | spidatain<5> | NULL | NULL | spidatain<5>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidatain<5>.CLKF | 4371 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | spidatain<5>.RSTF | 4372 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidatain<5>.CE | 4373 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidatain<5>.Q | 4374 | ? | 0 | 0 | spidatain<5> | NULL | NULL | spidatain<5>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<6> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<5> | 4149 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidatain<6> | 4150 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidatain<6>.SI | spidatain<6> | 0 | 5 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<5> | 4149 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidatain<6>.D1 | 4376 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidatain<6>.D2 | 4377 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 1 | IV_TRUE | spidatain<5> -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidatain<6>.CLKF | 4378 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | spidatain<6>.RSTF | 4379 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidatain<6>.CE | 4380 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 - -SRFF_INSTANCE | spidatain<6>.REG | spidatain<6> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidatain<6>.D | 4375 | ? | 0 | 0 | spidatain<6> | NULL | NULL | spidatain<6>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidatain<6>.CLKF | 4378 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | spidatain<6>.RSTF | 4379 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidatain<6>.CE | 4380 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidatain<6>.Q | 4381 | ? | 0 | 0 | spidatain<6> | NULL | NULL | spidatain<6>.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | nio_stb_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | nio_stb | 4238 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX - -INPUT_INSTANCE | 0 | 0 | NULL | a9_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | a9 | 4239 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | a9_IBUF | 4152 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a9_IBUF | 0 | 5 | II_IMUX - -INPUT_INSTANCE | 0 | 0 | NULL | a8_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | a8 | 4240 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | a8_IBUF | 4153 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a8_IBUF | 0 | 5 | II_IMUX - -INPUT_INSTANCE | 0 | 0 | NULL | a10_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | a10 | 4241 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | a10_IBUF | 4154 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a10_IBUF | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<7> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<6> | 4150 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidatain<7> | 4155 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidatain<7>.SI | spidatain<7> | 0 | 5 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<6> | 4150 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidatain<7>.D1 | 4383 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidatain<7>.D2 | 4384 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 1 | IV_TRUE | spidatain<6> -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidatain<7>.CLKF | 4385 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | spidatain<7>.RSTF | 4386 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidatain<7>.CE | 4387 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 - -SRFF_INSTANCE | spidatain<7>.REG | spidatain<7> | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidatain<7>.D | 4382 | ? | 0 | 0 | spidatain<7> | NULL | NULL | spidatain<7>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidatain<7>.CLKF | 4385 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | spidatain<7>.RSTF | 4386 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidatain<7>.CE | 4387 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidatain<7>.Q | 4388 | ? | 0 | 0 | spidatain<7> | NULL | NULL | spidatain<7>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | int_sclk | spi6502b_COPY_0_COPY_0 | 2155873280 | 8 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1>.EXP | 4591 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.EXP | shiftcnt<1> | 4 | 0 | MC_EXPORT -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | int_sclk | 4156 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_sclk.Q | int_sclk | 0 | 0 | MC_Q - -SIGNAL_INSTANCE | int_sclk.SI | int_sclk | 0 | 8 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1>.EXP | 4591 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.EXP | shiftcnt<1> | 4 | 0 | MC_EXPORT -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | int_sclk.D1 | 4390 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 1 | IV_TRUE | cpol -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | int_sclk.D2 | 4391 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 1 | IV_TRUE | shiftcnt<1>.EXP -SPPTERM | 5 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpha | IV_TRUE | shiftcnt<0> | IV_FALSE | shiftdone | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | int_sclk.CLKF | 4392 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF -SIGNAL | NODE | int_sclk.SETF | 4393 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 5 | 9 | MC_SI_SETF -SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_TRUE | cpol -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | int_sclk.RSTF | 4394 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_FALSE | cpol - -SRFF_INSTANCE | int_sclk.REG | int_sclk | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | int_sclk.D | 4389 | ? | 0 | 0 | int_sclk | NULL | NULL | int_sclk.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | int_sclk.CLKF | 4392 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 2 | 8 | SRFF_S -SIGNAL | NODE | int_sclk.SETF | 4393 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 5 | 9 | MC_SI_SETF -SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_TRUE | cpol -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | int_sclk.RSTF | 4394 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_FALSE | cpol -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | int_sclk.Q | 4395 | ? | 0 | 0 | int_sclk | NULL | NULL | int_sclk.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | cpu_Nphi2_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_Nphi2 | 4247 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<3> | spi6502b_COPY_0_COPY_0 | 2155888640 | 7 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<3> | 4147 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | int_dout<3> | 4158 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.Q | int_dout<3> | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 2 | 0 | MC_OE -NODE | int_dout<3>$OE | 4159 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.BUFOE.OUT | int_dout<3> | 2 | 0 | MC_OE - -SIGNAL_INSTANCE | int_dout<3>.SI | int_dout<3> | 0 | 7 | 3 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<3> | 4147 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | tmo | 4139 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | int_dout<3>.D1 | 4397 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | int_dout<3>.D2 | 4398 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<3> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST -SIGNAL | NODE | int_dout<3>.TRST | 4400 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF - -SRFF_INSTANCE | int_dout<3>.REG | int_dout<3> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | int_dout<3>.D | 4396 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | int_dout<3>.Q | 4401 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.REG | 0 | 8 | SRFF_Q - -BUF_INSTANCE | int_dout<3>.BUFOE | int_dout<3> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN -SIGNAL | NODE | int_dout<3>.TRST | 4400 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT -NODE | int_dout<3>.BUFOE.OUT | 4399 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.BUFOE | 0 | 10 | BUF_OUT - -MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<5> | spi6502b_COPY_0_COPY_0 | 2155888640 | 8 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<5> | 4149 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | int_dout<5> | 4160 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.Q | int_dout<5> | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 2 | 0 | MC_OE -NODE | int_dout<5>$OE | 4161 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.BUFOE.OUT | int_dout<5> | 2 | 0 | MC_OE - -SIGNAL_INSTANCE | int_dout<5>.SI | int_dout<5> | 0 | 8 | 3 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<5> | 4149 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | int_dout<5>.D1 | 4403 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | int_dout<5>.D2 | 4404 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<5> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | start_shifting | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | shifting2 | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST -SIGNAL | NODE | int_dout<5>.TRST | 4406 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF - -SRFF_INSTANCE | int_dout<5>.REG | int_dout<5> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | int_dout<5>.D | 4402 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | int_dout<5>.Q | 4407 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.REG | 0 | 8 | SRFF_Q - -BUF_INSTANCE | int_dout<5>.BUFOE | int_dout<5> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN -SIGNAL | NODE | int_dout<5>.TRST | 4406 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT -NODE | int_dout<5>.BUFOE.OUT | 4405 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.BUFOE | 0 | 10 | BUF_OUT - -MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<6> | spi6502b_COPY_0_COPY_0 | 2155888640 | 7 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<6> | 4150 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | int_dout<6> | 4162 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.Q | int_dout<6> | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 2 | 0 | MC_OE -NODE | int_dout<6>$OE | 4163 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.BUFOE.OUT | int_dout<6> | 2 | 0 | MC_OE - -SIGNAL_INSTANCE | int_dout<6>.SI | int_dout<6> | 0 | 7 | 3 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<6> | 4150 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | int_dout<6>.D1 | 4409 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | int_dout<6>.D2 | 4410 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<6> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST -SIGNAL | NODE | int_dout<6>.TRST | 4412 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF - -SRFF_INSTANCE | int_dout<6>.REG | int_dout<6> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | int_dout<6>.D | 4408 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | int_dout<6>.Q | 4413 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.REG | 0 | 8 | SRFF_Q - -BUF_INSTANCE | int_dout<6>.BUFOE | int_dout<6> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN -SIGNAL | NODE | int_dout<6>.TRST | 4412 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT -NODE | int_dout<6>.BUFOE.OUT | 4411 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.BUFOE | 0 | 10 | BUF_OUT - -MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<7> | spi6502b_COPY_0_COPY_0 | 2155888640 | 7 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<7> | 4155 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | tc | 4172 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | int_dout<7> | 4164 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.Q | int_dout<7> | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 2 | 0 | MC_OE -NODE | int_dout<7>$OE | 4165 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.BUFOE.OUT | int_dout<7> | 2 | 0 | MC_OE - -SIGNAL_INSTANCE | int_dout<7>.SI | int_dout<7> | 0 | 7 | 3 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<7> | 4155 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | tc | 4172 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | int_dout<7>.D1 | 4415 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | int_dout<7>.D2 | 4416 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<7> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | tc | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST -SIGNAL | NODE | int_dout<7>.TRST | 4418 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF - -SRFF_INSTANCE | int_dout<7>.REG | int_dout<7> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | int_dout<7>.D | 4414 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | int_dout<7>.Q | 4419 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.REG | 0 | 8 | SRFF_Q - -BUF_INSTANCE | int_dout<7>.BUFOE | int_dout<7> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN -SIGNAL | NODE | int_dout<7>.TRST | 4418 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT -NODE | int_dout<7>.BUFOE.OUT | 4417 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.BUFOE | 0 | 10 | BUF_OUT - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | shiftcnt<3> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | shiftcnt<3>.SI | shiftcnt<3> | 0 | 7 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | shiftcnt<3>.D1 | 4421 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | shiftcnt<3>.D2 | 4422 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_TRUE | shiftcnt<3> | IV_FALSE | shifting2 -SPPTERM | 4 | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<0> | IV_TRUE | shiftcnt<1> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | shiftcnt<3>.CLKF | 4423 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | shiftcnt<3>.RSTF | 4424 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF - -SRFF_INSTANCE | shiftcnt<3>.REG | shiftcnt<3> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | shiftcnt<3>.D | 4420 | ? | 0 | 0 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | shiftcnt<3>.CLKF | 4423 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | shiftcnt<3>.RSTF | 4424 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | shiftcnt<3>.Q | 4425 | ? | 0 | 0 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | shiftcnt<2> | spi6502b_COPY_0_COPY_0 | 2155877376 | 6 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | shiftcnt<2>.SI | shiftcnt<2> | 0 | 6 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | shiftcnt<2>.D1 | 4427 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | shiftcnt<2>.D2 | 4428 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_TRUE | shiftcnt<2> | IV_FALSE | shifting2 -SPPTERM | 3 | IV_TRUE | shiftcnt<0> | IV_TRUE | shiftcnt<1> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | shiftcnt<2>.CLKF | 4429 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | shiftcnt<2>.RSTF | 4430 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF - -SRFF_INSTANCE | shiftcnt<2>.REG | shiftcnt<2> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | shiftcnt<2>.D | 4426 | ? | 0 | 0 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | shiftcnt<2>.CLKF | 4429 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | shiftcnt<2>.RSTF | 4430 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | shiftcnt<2>.Q | 4431 | ? | 0 | 0 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | shiftcnt<0> | spi6502b_COPY_0_COPY_0 | 2155873280 | 4 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | shiftcnt<0>.SI | shiftcnt<0> | 0 | 4 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | shiftcnt<0>.D1 | 4433 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | shiftcnt<0>.D2 | 4434 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_FALSE | shiftcnt<0> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | shiftcnt<0>.CLKF | 4435 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | shiftcnt<0>.RSTF | 4436 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF - -SRFF_INSTANCE | shiftcnt<0>.REG | shiftcnt<0> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | shiftcnt<0>.D | 4432 | ? | 0 | 0 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | shiftcnt<0>.CLKF | 4435 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | shiftcnt<0>.RSTF | 4436 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | shiftcnt<0>.Q | 4437 | ? | 0 | 0 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | shiftcnt<1> | spi6502b_COPY_0_COPY_0 | 2155873280 | 7 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT -NODE | shiftcnt<1>.EXP | 4591 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.EXP | shiftcnt<1> | 4 | 0 | MC_EXPORT - -SIGNAL_INSTANCE | shiftcnt<1>.SI | shiftcnt<1> | 0 | 7 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | shiftcnt<1>.D1 | 4439 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | shiftcnt<1>.D2 | 4440 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 3 | IV_TRUE | shiftcnt<0> | IV_FALSE | shiftcnt<1> | IV_TRUE | shifting2 -SPPTERM | 3 | IV_FALSE | shiftcnt<0> | IV_TRUE | shiftcnt<1> | IV_TRUE | shifting2 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | shiftcnt<1>.CLKF | 4441 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | shiftcnt<1>.RSTF | 4442 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT -SIGNAL | NODE | shiftcnt<1>.EXP | 4590 | ? | 0 | 0 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 7 | 9 | MC_SI_EXPORT -SPPTERM | 5 | IV_TRUE | cpu_Nres_IBUF | IV_TRUE | cpha | IV_FALSE | shiftcnt<0> | IV_FALSE | shiftdone | IV_TRUE | shifting2 - -SRFF_INSTANCE | shiftcnt<1>.REG | shiftcnt<1> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | shiftcnt<1>.D | 4438 | ? | 0 | 0 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | shiftcnt<1>.CLKF | 4441 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | shiftcnt<1>.RSTF | 4442 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | shiftcnt<1>.Q | 4443 | ? | 0 | 0 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | shiftdone | spi6502b_COPY_0_COPY_0 | 2155873280 | 6 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | shiftdone.SI | shiftdone | 0 | 6 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<0> | 4168 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | shiftdone.D1 | 4445 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | shiftdone.D2 | 4446 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<0> | IV_TRUE | shiftcnt<1> -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | shiftdone.CLKF | 4447 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | shiftdone.RSTF | 4448 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF - -SRFF_INSTANCE | shiftdone.REG | shiftdone | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | shiftdone.D | 4444 | ? | 0 | 0 | shiftdone | NULL | NULL | shiftdone.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | shiftdone.CLKF | 4447 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | shiftdone.RSTF | 4448 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | shiftdone.Q | 4449 | ? | 0 | 0 | shiftdone | NULL | NULL | shiftdone.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | start_shifting | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 4232 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | start_shifting.SI | start_shifting | 0 | 7 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 4232 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | start_shifting.D1 | 4451 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | start_shifting.D2 | 4452 | ? | 0 | 6144 | start_shifting | NULL | NULL | start_shifting.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_FALSE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | start_shifting | IV_FALSE | cpu_a_0_IBUF -SPPTERM | 4 | IV_TRUE | frx | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | start_shifting | IV_FALSE | cpu_a_0_IBUF -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | start_shifting.CLKF | 4453 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF -SIGNAL | NODE | start_shifting.RSTF | 4454 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | start_shifting/start_shifting_RSTF__$INT.UIM - -SRFF_INSTANCE | start_shifting.REG | start_shifting | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | start_shifting.D | 4450 | ? | 0 | 0 | start_shifting | NULL | NULL | start_shifting.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | start_shifting.CLKF | 4453 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 3 | 8 | SRFF_R -SIGNAL | NODE | start_shifting.RSTF | 4454 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 6 | 9 | MC_SI_RSTF -SPPTERM | 1 | IV_FALSE | start_shifting/start_shifting_RSTF__$INT.UIM -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | start_shifting.Q | 4455 | ? | 0 | 0 | start_shifting | NULL | NULL | start_shifting.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+OptxMapped | tc | spi6502b_COPY_0_COPY_0 | 2155873280 | 4 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | tc | 4172 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | tc.SI | tc | 0 | 4 | 5 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | tc.D1 | 4457 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | tc.D2 | 4458 | ? | 0 | 6144 | tc | NULL | NULL | tc.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | tc.CLKF | 4459 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF -SIGNAL | NODE | tc.SETF | 4460 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 5 | 9 | MC_SI_SETF -SPPTERM | 1 | IV_TRUE | shiftdone -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | tc.CE | 4461 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF - -SRFF_INSTANCE | tc.REG | tc | 0 | 4 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | tc.D | 4456 | ? | 0 | 0 | tc | NULL | NULL | tc.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | tc.CLKF | 4459 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 2 | 8 | SRFF_S -SIGNAL | NODE | tc.SETF | 4460 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 5 | 9 | MC_SI_SETF -SPPTERM | 1 | IV_TRUE | shiftdone -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | tc.CE | 4461 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | tc.Q | 4462 | ? | 0 | 0 | tc | NULL | NULL | tc.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<0> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<0> | 4173 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidataout<0> | 4173 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidataout<0>.SI | spidataout<0> | 0 | 7 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<0> | 4173 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3017 | 4196 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3017 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidataout<0>.D1 | 4464 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidataout<0>.D2 | 4465 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<0> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3017 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<0> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3017 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidataout<0>.CLKF | 4466 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidataout<0>.CE | 4467 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | spidataout<0>.REG | spidataout<0> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidataout<0>.D | 4463 | ? | 0 | 0 | spidataout<0> | NULL | NULL | spidataout<0>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidataout<0>.CLKF | 4466 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidataout<0>.CE | 4467 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidataout<0>.Q | 4468 | ? | 0 | 0 | spidataout<0> | NULL | NULL | spidataout<0>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<1> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<1> | 4174 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidataout<1> | 4174 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidataout<1>.SI | spidataout<1> | 0 | 7 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<1> | 4174 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3019 | 4197 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3019 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidataout<1>.D1 | 4470 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidataout<1>.D2 | 4471 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<1> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3019 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<1> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3019 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidataout<1>.CLKF | 4472 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidataout<1>.CE | 4473 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | spidataout<1>.REG | spidataout<1> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidataout<1>.D | 4469 | ? | 0 | 0 | spidataout<1> | NULL | NULL | spidataout<1>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidataout<1>.CLKF | 4472 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidataout<1>.CE | 4473 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidataout<1>.Q | 4474 | ? | 0 | 0 | spidataout<1> | NULL | NULL | spidataout<1>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<2> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<2> | 4175 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidataout<2> | 4175 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidataout<2>.SI | spidataout<2> | 0 | 7 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<2> | 4175 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3021 | 4198 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3021 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidataout<2>.D1 | 4476 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidataout<2>.D2 | 4477 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<2> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3021 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<2> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3021 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidataout<2>.CLKF | 4478 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidataout<2>.CE | 4479 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | spidataout<2>.REG | spidataout<2> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidataout<2>.D | 4475 | ? | 0 | 0 | spidataout<2> | NULL | NULL | spidataout<2>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidataout<2>.CLKF | 4478 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidataout<2>.CE | 4479 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidataout<2>.Q | 4480 | ? | 0 | 0 | spidataout<2> | NULL | NULL | spidataout<2>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<3> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<3> | 4176 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3023 | 4199 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3023 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidataout<3> | 4176 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidataout<3>.SI | spidataout<3> | 0 | 7 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<3> | 4176 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3023 | 4199 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3023 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidataout<3>.D1 | 4482 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidataout<3>.D2 | 4483 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<3> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3023 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<3> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3023 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidataout<3>.CLKF | 4484 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidataout<3>.CE | 4485 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | spidataout<3>.REG | spidataout<3> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidataout<3>.D | 4481 | ? | 0 | 0 | spidataout<3> | NULL | NULL | spidataout<3>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidataout<3>.CLKF | 4484 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidataout<3>.CE | 4485 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidataout<3>.Q | 4486 | ? | 0 | 0 | spidataout<3> | NULL | NULL | spidataout<3>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<4> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<4> | 4177 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidataout<4> | 4177 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidataout<4>.SI | spidataout<4> | 0 | 7 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<4> | 4177 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3025 | 4200 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3025 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidataout<4>.D1 | 4488 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidataout<4>.D2 | 4489 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<4> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3025 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<4> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3025 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidataout<4>.CLKF | 4490 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidataout<4>.CE | 4491 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | spidataout<4>.REG | spidataout<4> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidataout<4>.D | 4487 | ? | 0 | 0 | spidataout<4> | NULL | NULL | spidataout<4>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidataout<4>.CLKF | 4490 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidataout<4>.CE | 4491 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidataout<4>.Q | 4492 | ? | 0 | 0 | spidataout<4> | NULL | NULL | spidataout<4>.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | N3027 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_d<5> | 4217 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<5> | 0 | 6 | OI_OUT -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | N3027 | 4203 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3027 | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<5> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<5> | 4178 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3027 | 4203 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3027 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidataout<5> | 4178 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidataout<5>.SI | spidataout<5> | 0 | 7 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<5> | 4178 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3027 | 4203 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3027 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidataout<5>.D1 | 4494 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidataout<5>.D2 | 4495 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<5> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3027 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<5> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3027 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidataout<5>.CLKF | 4496 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidataout<5>.CE | 4497 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | spidataout<5>.REG | spidataout<5> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidataout<5>.D | 4493 | ? | 0 | 0 | spidataout<5> | NULL | NULL | spidataout<5>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidataout<5>.CLKF | 4496 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidataout<5>.CE | 4497 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidataout<5>.Q | 4498 | ? | 0 | 0 | spidataout<5> | NULL | NULL | spidataout<5>.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<6> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<6> | 4179 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3029 | 4201 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3029 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidataout<6> | 4179 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidataout<6>.SI | spidataout<6> | 0 | 7 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<6> | 4179 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3029 | 4201 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3029 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidataout<6>.D1 | 4500 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidataout<6>.D2 | 4501 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<6> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3029 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<6> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3029 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidataout<6>.CLKF | 4502 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidataout<6>.CE | 4503 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | spidataout<6>.REG | spidataout<6> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidataout<6>.D | 4499 | ? | 0 | 0 | spidataout<6> | NULL | NULL | spidataout<6>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidataout<6>.CLKF | 4502 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidataout<6>.CE | 4503 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidataout<6>.Q | 4504 | ? | 0 | 0 | spidataout<6> | NULL | NULL | spidataout<6>.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | N3031 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | cpu_d<7> | 4219 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<7> | 0 | 6 | OI_OUT -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | N3031 | 4202 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3031 | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | spidataout<7> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<7> | 4180 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3031 | 4202 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3031 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | spidataout<7> | 4180 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | spidataout<7>.SI | spidataout<7> | 0 | 7 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<7> | 4180 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | N3031 | 4202 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3031 | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | spidataout<7>.D1 | 4506 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | spidataout<7>.D2 | 4507 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | spidataout<7> | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3031 -SPPTERM | 4 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | spidataout<7> | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3031 -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | spidataout<7>.CLKF | 4508 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE -SIGNAL | NODE | spidataout<7>.CE | 4509 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF - -SRFF_INSTANCE | spidataout<7>.REG | spidataout<7> | 0 | 3 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | spidataout<7>.D | 4505 | ? | 0 | 0 | spidataout<7> | NULL | NULL | spidataout<7>.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | spidataout<7>.CLKF | 4508 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_TRUE | Ncs2_IBUF -INPUT_NODE_TYPE | 4 | 8 | SRFF_CE -SIGNAL | NODE | spidataout<7>.CE | 4509 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 10 | 9 | MC_SI_CE -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | spidataout<7>.Q | 4510 | ? | 0 | 0 | spidataout<7> | NULL | NULL | spidataout<7>.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | nio_sel_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | nio_sel | 4243 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | OptxMapped | ng_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 3 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | ng_OBUF | 4182 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ng_OBUF.Q | ng_OBUF | 0 | 0 | MC_Q - -SIGNAL_INSTANCE | ng_OBUF.SI | ng_OBUF | 0 | 3 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | ng_OBUF.D1 | 4512 | ? | 0 | 4096 | ng_OBUF | NULL | NULL | ng_OBUF.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | ng_OBUF.D2 | 4513 | ? | 0 | 4096 | ng_OBUF | NULL | NULL | ng_OBUF.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 3 | IV_TRUE | Ncs2_IBUF | IV_TRUE | nio_stb_IBUF | IV_TRUE | nio_sel_IBUF - -SRFF_INSTANCE | ng_OBUF.REG | ng_OBUF | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | ng_OBUF.D | 4511 | ? | 0 | 0 | ng_OBUF | NULL | NULL | ng_OBUF.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | ng_OBUF.Q | 4514 | ? | 0 | 0 | ng_OBUF | NULL | NULL | ng_OBUF.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<0> | spi6502b_COPY_0_COPY_0 | 2155888640 | 9 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<0> | 4144 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<0> | 4140 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | int_dout<0> | 4183 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.Q | int_dout<0> | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 2 | 0 | MC_OE -NODE | int_dout<0>$OE | 4184 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.BUFOE.OUT | int_dout<0> | 2 | 0 | MC_OE - -SIGNAL_INSTANCE | int_dout<0>.SI | int_dout<0> | 0 | 9 | 3 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<0> | 4144 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<0> | 4140 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpha | 4135 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | int_dout<0>.D1 | 4516 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | int_dout<0>.D2 | 4517 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slavesel | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<0> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST -SIGNAL | NODE | int_dout<0>.TRST | 4519 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF - -SRFF_INSTANCE | int_dout<0>.REG | int_dout<0> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | int_dout<0>.D | 4515 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | int_dout<0>.Q | 4520 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.REG | 0 | 8 | SRFF_Q - -BUF_INSTANCE | int_dout<0>.BUFOE | int_dout<0> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN -SIGNAL | NODE | int_dout<0>.TRST | 4519 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT -NODE | int_dout<0>.BUFOE.OUT | 4518 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.BUFOE | 0 | 10 | BUF_OUT - -MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<1> | spi6502b_COPY_0_COPY_0 | 2155888640 | 8 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<1> | 4145 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<1> | 4141 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | int_dout<1> | 4185 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.Q | int_dout<1> | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 2 | 0 | MC_OE -NODE | int_dout<1>$OE | 4186 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.BUFOE.OUT | int_dout<1> | 2 | 0 | MC_OE - -SIGNAL_INSTANCE | int_dout<1>.SI | int_dout<1> | 0 | 8 | 3 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<1> | 4145 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpol | 4133 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<1> | 4141 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | int_dout<1>.D1 | 4522 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | int_dout<1>.D2 | 4523 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<1> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST -SIGNAL | NODE | int_dout<1>.TRST | 4525 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF - -SRFF_INSTANCE | int_dout<1>.REG | int_dout<1> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | int_dout<1>.D | 4521 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | int_dout<1>.Q | 4526 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.REG | 0 | 8 | SRFF_Q - -BUF_INSTANCE | int_dout<1>.BUFOE | int_dout<1> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN -SIGNAL | NODE | int_dout<1>.TRST | 4525 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT -NODE | int_dout<1>.BUFOE.OUT | 4524 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.BUFOE | 0 | 10 | BUF_OUT - -MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<2> | spi6502b_COPY_0_COPY_0 | 2155888640 | 8 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<2> | 4146 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<2> | 4142 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | int_dout<2> | 4187 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.Q | int_dout<2> | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 2 | 0 | MC_OE -NODE | int_dout<2>$OE | 4188 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.BUFOE.OUT | int_dout<2> | 2 | 0 | MC_OE - -SIGNAL_INSTANCE | int_dout<2>.SI | int_dout<2> | 0 | 8 | 3 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<2> | 4146 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | divisor<2> | 4142 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | int_dout<2>.D1 | 4528 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | int_dout<2>.D2 | 4529 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<2> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST -SIGNAL | NODE | int_dout<2>.TRST | 4531 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF - -SRFF_INSTANCE | int_dout<2>.REG | int_dout<2> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | int_dout<2>.D | 4527 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | int_dout<2>.Q | 4532 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.REG | 0 | 8 | SRFF_Q - -BUF_INSTANCE | int_dout<2>.BUFOE | int_dout<2> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN -SIGNAL | NODE | int_dout<2>.TRST | 4531 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT -NODE | int_dout<2>.BUFOE.OUT | 4530 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.BUFOE | 0 | 10 | BUF_OUT - -INPUT_INSTANCE | 0 | 0 | NULL | spi_int_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | spi_int | 4246 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | spi_int_IBUF | 4204 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX - -MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<4> | spi6502b_COPY_0_COPY_0 | 2155888640 | 9 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<4> | 4148 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spi_int_IBUF | 4204 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | int_dout<4> | 4189 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.Q | int_dout<4> | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 2 | 0 | MC_OE -NODE | int_dout<4>$OE | 4190 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.BUFOE.OUT | int_dout<4> | 2 | 0 | MC_OE - -SIGNAL_INSTANCE | int_dout<4>.SI | int_dout<4> | 0 | 9 | 3 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | Ncs2_IBUF | 4129 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_rnw_IBUF | 4130 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidatain<4> | 4148 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_1_IBUF | 4157 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_a_0_IBUF | 4191 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spi_int_IBUF | 4204 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | frx | 4136 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | int_dout<4>.D1 | 4534 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | int_dout<4>.D2 | 4535 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slaveinten | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<4> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF -SPPTERM | 6 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | spi_int_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST -SIGNAL | NODE | int_dout<4>.TRST | 4537 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF - -SRFF_INSTANCE | int_dout<4>.REG | int_dout<4> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | int_dout<4>.D | 4533 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | int_dout<4>.Q | 4538 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.REG | 0 | 8 | SRFF_Q - -BUF_INSTANCE | int_dout<4>.BUFOE | int_dout<4> | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN -SIGNAL | NODE | int_dout<4>.TRST | 4537 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 3 | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_Nphi2_IBUF -OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT -NODE | int_dout<4>.BUFOE.OUT | 4536 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.BUFOE | 0 | 10 | BUF_OUT - -MACROCELL_INSTANCE | PrldLow+OptxMapped | shifting2 | spi6502b_COPY_0_COPY_0 | 2155873280 | 8 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<1> | 4174 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT -NODE | shifting2.EXP | 4589 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT - -SIGNAL_INSTANCE | shifting2.SI | shifting2 | 0 | 8 | 4 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<1> | 4174 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | shifting2.D1 | 4540 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | shifting2.D2 | 4541 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_FALSE | shiftdone | IV_TRUE | start_shifting -OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF -SIGNAL | NODE | shifting2.CLKF | 4542 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT -SIGNAL | NODE | shifting2.EXP | 4587 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.SI | 7 | 9 | MC_SI_EXPORT -SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<1> | IV_TRUE | shifting2 - -SRFF_INSTANCE | shifting2.REG | shifting2 | 0 | 2 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | shifting2.D | 4539 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -SIGNAL | NODE | shifting2.CLKF | 4542 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 3 | 9 | MC_SI_CLKF -SPPTERM | 1 | IV_FALSE | $OpTx$INV$24__$INT.UIM -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | shifting2.Q | 4543 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.REG | 0 | 8 | SRFF_Q - -INPUT_INSTANCE | 0 | 0 | NULL | extclk_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 2 -INPUT_NODE_TYPE | 0 | 5 | II_IN -NODE | extclk | 4245 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE -OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX -NODE | extclk_IBUF | 4193 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 3 | 5 | II_FCLK -NODE | FCLKIO_0 | 4194 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 3 | 5 | II_FCLK - -MACROCELL_INSTANCE | Inv+PrldLow+OptxMapped | add_dec/XLXN_11 | spi6502b_COPY_0_COPY_0 | 2155873536 | 5 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a9_IBUF | 4152 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a9_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a8_IBUF | 4153 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a8_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a10_IBUF | 4154 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a10_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | FCLKIO_0 | 4194 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 3 | 5 | II_FCLK -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | add_dec/XLXN_11 | 4195 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | add_dec/XLXN_11.Q | add_dec/XLXN_11 | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | add_dec/XLXN_11.SI | add_dec/XLXN_11 | 0 | 4 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a9_IBUF | 4152 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a9_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a8_IBUF | 4153 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a8_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a10_IBUF | 4154 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a10_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | add_dec/XLXN_11.D1 | 4545 | ? | 0 | 4096 | add_dec/XLXN_11 | NULL | NULL | add_dec/XLXN_11.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | add_dec/XLXN_11.D2 | 4546 | ? | 0 | 4096 | add_dec/XLXN_11 | NULL | NULL | add_dec/XLXN_11.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 4 | IV_FALSE | nio_stb_IBUF | IV_TRUE | a9_IBUF | IV_TRUE | a8_IBUF | IV_TRUE | a10_IBUF - -SRFF_INSTANCE | add_dec/XLXN_11.REG | add_dec/XLXN_11 | 0 | 2 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | add_dec/XLXN_11.D | 4544 | ? | 0 | 0 | add_dec/XLXN_11 | NULL | NULL | add_dec/XLXN_11.XOR | 0 | 7 | ALU_F -INPUT_NODE_TYPE | 1 | 8 | SRFF_C -NODE | FCLKIO_0 | 4194 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 3 | 5 | II_FCLK -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | add_dec/XLXN_11.Q | 4547 | ? | 0 | 0 | add_dec/XLXN_11 | NULL | NULL | add_dec/XLXN_11.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | OptxMapped | b10_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 2 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a10_IBUF | 4154 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a10_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | b10_OBUF | 4206 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b10_OBUF.Q | b10_OBUF | 0 | 0 | MC_Q - -SIGNAL_INSTANCE | b10_OBUF.SI | b10_OBUF | 0 | 2 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a10_IBUF | 4154 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a10_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | b10_OBUF.D1 | 4549 | ? | 0 | 4096 | b10_OBUF | NULL | NULL | b10_OBUF.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | b10_OBUF.D2 | 4550 | ? | 0 | 4096 | b10_OBUF | NULL | NULL | b10_OBUF.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_TRUE | a10_IBUF | IV_TRUE | nio_sel_IBUF - -SRFF_INSTANCE | b10_OBUF.REG | b10_OBUF | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | b10_OBUF.D | 4548 | ? | 0 | 0 | b10_OBUF | NULL | NULL | b10_OBUF.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | b10_OBUF.Q | 4551 | ? | 0 | 0 | b10_OBUF | NULL | NULL | b10_OBUF.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | OptxMapped | b8_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 2 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a8_IBUF | 4153 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a8_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | b8_OBUF | 4207 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b8_OBUF.Q | b8_OBUF | 0 | 0 | MC_Q - -SIGNAL_INSTANCE | b8_OBUF.SI | b8_OBUF | 0 | 2 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a8_IBUF | 4153 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a8_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | b8_OBUF.D1 | 4553 | ? | 0 | 4096 | b8_OBUF | NULL | NULL | b8_OBUF.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | b8_OBUF.D2 | 4554 | ? | 0 | 4096 | b8_OBUF | NULL | NULL | b8_OBUF.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_TRUE | a8_IBUF | IV_TRUE | nio_sel_IBUF - -SRFF_INSTANCE | b8_OBUF.REG | b8_OBUF | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | b8_OBUF.D | 4552 | ? | 0 | 0 | b8_OBUF | NULL | NULL | b8_OBUF.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | b8_OBUF.Q | 4555 | ? | 0 | 0 | b8_OBUF | NULL | NULL | b8_OBUF.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | OptxMapped | b9_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 2 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a9_IBUF | 4152 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a9_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | b9_OBUF | 4208 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b9_OBUF.Q | b9_OBUF | 0 | 0 | MC_Q - -SIGNAL_INSTANCE | b9_OBUF.SI | b9_OBUF | 0 | 2 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | a9_IBUF | 4152 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | a9_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | b9_OBUF.D1 | 4557 | ? | 0 | 4096 | b9_OBUF | NULL | NULL | b9_OBUF.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | b9_OBUF.D2 | 4558 | ? | 0 | 4096 | b9_OBUF | NULL | NULL | b9_OBUF.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_TRUE | a9_IBUF | IV_TRUE | nio_sel_IBUF - -SRFF_INSTANCE | b9_OBUF.REG | b9_OBUF | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | b9_OBUF.D | 4556 | ? | 0 | 0 | b9_OBUF | NULL | NULL | b9_OBUF.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | b9_OBUF.Q | 4559 | ? | 0 | 0 | b9_OBUF | NULL | NULL | b9_OBUF.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | OptxMapped | led_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 3 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | led_OBUF | 4209 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | led_OBUF.Q | led_OBUF | 0 | 0 | MC_Q - -SIGNAL_INSTANCE | led_OBUF.SI | led_OBUF | 0 | 3 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slavesel | 4132 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | led_OBUF.D1 | 4561 | ? | 0 | 4096 | led_OBUF | NULL | NULL | led_OBUF.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | led_OBUF.D2 | 4562 | ? | 0 | 4096 | led_OBUF | NULL | NULL | led_OBUF.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 3 | IV_TRUE | slavesel | IV_FALSE | start_shifting | IV_FALSE | shifting2 - -SRFF_INSTANCE | led_OBUF.REG | led_OBUF | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | led_OBUF.D | 4560 | ? | 0 | 0 | led_OBUF | NULL | NULL | led_OBUF.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | led_OBUF.Q | 4563 | ? | 0 | 0 | led_OBUF | NULL | NULL | led_OBUF.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | Inv+OptxMapped | noe_OBUF | spi6502b_COPY_0_COPY_0 | 2155872512 | 3 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | add_dec/XLXN_11 | 4195 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | add_dec/XLXN_11.Q | add_dec/XLXN_11 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | noe_OBUF | 4210 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | noe_OBUF.Q | noe_OBUF | 0 | 0 | MC_Q - -SIGNAL_INSTANCE | noe_OBUF.SI | noe_OBUF | 0 | 3 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_sel_IBUF | 4181 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_sel_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | add_dec/XLXN_11 | 4195 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | add_dec/XLXN_11.Q | add_dec/XLXN_11 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | nio_stb_IBUF | 4151 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | nio_stb_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | noe_OBUF.D1 | 4565 | ? | 0 | 4096 | noe_OBUF | NULL | NULL | noe_OBUF.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | noe_OBUF.D2 | 4566 | ? | 0 | 4096 | noe_OBUF | NULL | NULL | noe_OBUF.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_FALSE | nio_stb_IBUF | IV_TRUE | add_dec/XLXN_11 -SPPTERM | 2 | IV_FALSE | nio_sel_IBUF | IV_TRUE | add_dec/XLXN_11 - -SRFF_INSTANCE | noe_OBUF.REG | noe_OBUF | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | noe_OBUF.D | 4564 | ? | 0 | 0 | noe_OBUF | NULL | NULL | noe_OBUF.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | noe_OBUF.Q | 4567 | ? | 0 | 0 | noe_OBUF | NULL | NULL | noe_OBUF.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | FbkInv+PinTrst+Merge+OptxMapped | cpu_Nirq_OBUFE | spi6502b_COPY_0_COPY_0 | 2155923456 | 1 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 4233 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 0 | 0 | MC_Q -NODE | cpu_Nirq_OBUFE$Q | 4211 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.Q | cpu_Nirq_OBUFE | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 2 | 0 | MC_OE -NODE | cpu_Nirq_OBUFE$OE | 4212 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.BUFOE.OUT | cpu_Nirq_OBUFE | 2 | 0 | MC_OE - -SIGNAL_INSTANCE | cpu_Nirq_OBUFE.SI | cpu_Nirq_OBUFE | 0 | 1 | 3 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 4233 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | cpu_Nirq_OBUFE.D1 | 4569 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | cpu_Nirq_OBUFE.D2 | 4570 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST -SIGNAL | NODE | cpu_Nirq_OBUFE.TRST | 4572 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 1 | IV_TRUE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM - -SRFF_INSTANCE | cpu_Nirq_OBUFE.REG | cpu_Nirq_OBUFE | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | cpu_Nirq_OBUFE.D | 4568 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | cpu_Nirq_OBUFE.Q | 4573 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.REG | 0 | 8 | SRFF_Q - -BUF_INSTANCE | cpu_Nirq_OBUFE.BUFOE | cpu_Nirq_OBUFE | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN -SIGNAL | NODE | cpu_Nirq_OBUFE.TRST | 4572 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 4 | 9 | MC_SI_TRST -SPPTERM | 1 | IV_TRUE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM -OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT -NODE | cpu_Nirq_OBUFE.BUFOE.OUT | 4571 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.BUFOE | 0 | 10 | BUF_OUT - -OUTPUT_INSTANCE | 0 | spi_mosi | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | int_mosi | 4127 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.Q | int_mosi | 0 | 0 | MC_Q -INPUT_NODE_TYPE | 2 | 6 | OI_OE -NODE | int_mosi$OE | 4128 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.BUFOE.OUT | int_mosi | 2 | 0 | MC_OE -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | spi_mosi | 4213 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_mosi | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | spi_Nsel | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | slavesel$Q | 4131 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel.Q | slavesel | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | spi_Nsel | 4214 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_Nsel | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | spi_sclk | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | int_sclk | 4156 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_sclk.Q | int_sclk | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | spi_sclk | 4215 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_sclk | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | cpu_d<3> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | int_dout<3> | 4158 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.Q | int_dout<3> | 0 | 0 | MC_Q -INPUT_NODE_TYPE | 2 | 6 | OI_OE -NODE | int_dout<3>$OE | 4159 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.BUFOE.OUT | int_dout<3> | 2 | 0 | MC_OE -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | cpu_d<3> | 4216 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<3> | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | cpu_d<5> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | int_dout<5> | 4160 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.Q | int_dout<5> | 0 | 0 | MC_Q -INPUT_NODE_TYPE | 2 | 6 | OI_OE -NODE | int_dout<5>$OE | 4161 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.BUFOE.OUT | int_dout<5> | 2 | 0 | MC_OE -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | cpu_d<5> | 4217 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<5> | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | cpu_d<6> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | int_dout<6> | 4162 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.Q | int_dout<6> | 0 | 0 | MC_Q -INPUT_NODE_TYPE | 2 | 6 | OI_OE -NODE | int_dout<6>$OE | 4163 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.BUFOE.OUT | int_dout<6> | 2 | 0 | MC_OE -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | cpu_d<6> | 4218 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<6> | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | cpu_d<7> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | int_dout<7> | 4164 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.Q | int_dout<7> | 0 | 0 | MC_Q -INPUT_NODE_TYPE | 2 | 6 | OI_OE -NODE | int_dout<7>$OE | 4165 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.BUFOE.OUT | int_dout<7> | 2 | 0 | MC_OE -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | cpu_d<7> | 4219 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<7> | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | ng | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | ng_OBUF | 4182 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ng_OBUF.Q | ng_OBUF | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | ng | 4220 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | ng | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | cpu_d<0> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | int_dout<0> | 4183 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.Q | int_dout<0> | 0 | 0 | MC_Q -INPUT_NODE_TYPE | 2 | 6 | OI_OE -NODE | int_dout<0>$OE | 4184 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.BUFOE.OUT | int_dout<0> | 2 | 0 | MC_OE -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | cpu_d<0> | 4221 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<0> | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | cpu_d<1> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | int_dout<1> | 4185 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.Q | int_dout<1> | 0 | 0 | MC_Q -INPUT_NODE_TYPE | 2 | 6 | OI_OE -NODE | int_dout<1>$OE | 4186 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.BUFOE.OUT | int_dout<1> | 2 | 0 | MC_OE -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | cpu_d<1> | 4222 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<1> | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | cpu_d<2> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | int_dout<2> | 4187 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.Q | int_dout<2> | 0 | 0 | MC_Q -INPUT_NODE_TYPE | 2 | 6 | OI_OE -NODE | int_dout<2>$OE | 4188 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.BUFOE.OUT | int_dout<2> | 2 | 0 | MC_OE -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | cpu_d<2> | 4223 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<2> | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | cpu_d<4> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | int_dout<4> | 4189 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.Q | int_dout<4> | 0 | 0 | MC_Q -INPUT_NODE_TYPE | 2 | 6 | OI_OE -NODE | int_dout<4>$OE | 4190 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.BUFOE.OUT | int_dout<4> | 2 | 0 | MC_OE -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | cpu_d<4> | 4224 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<4> | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | b10 | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | b10_OBUF | 4206 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b10_OBUF.Q | b10_OBUF | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | b10 | 4225 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | b10 | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | b8 | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | b8_OBUF | 4207 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b8_OBUF.Q | b8_OBUF | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | b8 | 4226 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | b8 | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | b9 | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | b9_OBUF | 4208 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | b9_OBUF.Q | b9_OBUF | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | b9 | 4227 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | b9 | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | led | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | led_OBUF | 4209 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | led_OBUF.Q | led_OBUF | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | led | 4228 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | led | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | noe | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | noe_OBUF | 4210 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | noe_OBUF.Q | noe_OBUF | 0 | 0 | MC_Q -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | noe | 4229 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | noe | 0 | 6 | OI_OUT - -OUTPUT_INSTANCE | 0 | cpu_Nirq | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 -INPUT_NODE_TYPE | 0 | 6 | OI_IN -NODE | cpu_Nirq_OBUFE$Q | 4211 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.Q | cpu_Nirq_OBUFE | 0 | 0 | MC_Q -INPUT_NODE_TYPE | 2 | 6 | OI_OE -NODE | cpu_Nirq_OBUFE$OE | 4212 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.BUFOE.OUT | cpu_Nirq_OBUFE | 2 | 0 | MC_OE -OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT -NODE | cpu_Nirq | 4230 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nirq | 0 | 6 | OI_OUT - -MACROCELL_INSTANCE | SoftPfbk | $OpTx$INV$24__$INT | spi6502b_COPY_0_COPY_0 | 2181038080 | 5 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | extclk_IBUF | 4193 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | $OpTx$INV$24__$INT.UIM | 4231 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$24__$INT.Q | $OpTx$INV$24__$INT | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | $OpTx$INV$24__$INT.SI | $OpTx$INV$24__$INT | 0 | 5 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ece | 4134 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nphi2_IBUF | 4205 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | extclk_IBUF | 4193 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | start_shifting | 4171 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | $OpTx$INV$24__$INT.D1 | 4575 | ? | 0 | 4096 | $OpTx$INV$24__$INT | NULL | NULL | $OpTx$INV$24__$INT.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | $OpTx$INV$24__$INT.D2 | 4576 | ? | 0 | 4096 | $OpTx$INV$24__$INT | NULL | NULL | $OpTx$INV$24__$INT.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_TRUE | ece | IV_FALSE | extclk_IBUF -SPPTERM | 2 | IV_FALSE | ece | IV_FALSE | cpu_Nphi2_IBUF -SPPTERM | 2 | IV_FALSE | start_shifting | IV_FALSE | shifting2 - -SRFF_INSTANCE | $OpTx$INV$24__$INT.REG | $OpTx$INV$24__$INT | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | $OpTx$INV$24__$INT.D | 4574 | ? | 0 | 0 | $OpTx$INV$24__$INT | NULL | NULL | $OpTx$INV$24__$INT.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | $OpTx$INV$24__$INT.Q | 4577 | ? | 0 | 0 | $OpTx$INV$24__$INT | NULL | NULL | $OpTx$INV$24__$INT.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | SoftPfbk | start_shifting/start_shifting_RSTF__$INT | spi6502b_COPY_0_COPY_0 | 2181038080 | 2 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 4232 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | start_shifting/start_shifting_RSTF__$INT.SI | start_shifting/start_shifting_RSTF__$INT | 0 | 2 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | cpu_Nres_IBUF | 4126 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | start_shifting/start_shifting_RSTF__$INT.D1 | 4579 | ? | 0 | 4096 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | start_shifting/start_shifting_RSTF__$INT.D2 | 4580 | ? | 0 | 4096 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | shiftdone - -SRFF_INSTANCE | start_shifting/start_shifting_RSTF__$INT.REG | start_shifting/start_shifting_RSTF__$INT | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | start_shifting/start_shifting_RSTF__$INT.D | 4578 | ? | 0 | 0 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | start_shifting/start_shifting_RSTF__$INT.Q | 4581 | ? | 0 | 0 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | SoftPfbk | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | spi6502b_COPY_0_COPY_0 | 2181038080 | 4 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | tc | 4172 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spi_int_IBUF | 4204 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM -NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 4233 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM - -SIGNAL_INSTANCE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 0 | 4 | 2 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | ier | 4137 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | tc | 4172 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | slaveinten | 4138 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten.Q | slaveinten | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spi_int_IBUF | 4204 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_IBUF | 0 | 5 | II_IMUX -OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 -SIGNAL | NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D1 | 4583 | ? | 0 | 4096 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | 1 | 9 | MC_SI_D1 -SPPTERM | 0 | IV_ZERO -OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 -SIGNAL | NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D2 | 4584 | ? | 0 | 4096 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | 2 | 9 | MC_SI_D2 -SPPTERM | 2 | IV_TRUE | ier | IV_TRUE | tc -SPPTERM | 2 | IV_TRUE | slaveinten | IV_FALSE | spi_int_IBUF - -SRFF_INSTANCE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.REG | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 0 | 1 | 1 -INPUT_NODE_TYPE | 0 | 8 | SRFF_D -NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D | 4582 | ? | 0 | 0 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.XOR | 0 | 7 | ALU_F -OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q -NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | 4585 | ? | 0 | 0 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.REG | 0 | 8 | SRFF_Q - -MACROCELL_INSTANCE | NULL | EXP6_ | spi6502b_COPY_0_COPY_0 | 2147483648 | 10 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<2> | 4175 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<3> | 4176 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<5> | 4178 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<6> | 4179 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<7> | 4180 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT -NODE | EXP6_.EXP | 4588 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT - -SIGNAL_INSTANCE | EXP6_.SI | EXP6_ | 0 | 10 | 1 -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<3> | 4166 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<2> | 4167 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftcnt<1> | 4169 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shiftdone | 4170 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<2> | 4175 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | shifting2 | 4192 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<3> | 4176 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<5> | 4178 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<6> | 4179 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM -INPUT_NODE_TYPE | 1 | 100 | NOTYPE -NODE | spidataout<7> | 4180 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM -OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT -SIGNAL | NODE | EXP6_.EXP | 4586 | ? | 0 | 0 | EXP6_ | NULL | NULL | EXP6_.SI | 7 | 9 | MC_SI_EXPORT -SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<2> | IV_TRUE | shifting2 -SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<3> | IV_TRUE | shifting2 -SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<5> | IV_TRUE | shifting2 -SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<6> | IV_TRUE | shifting2 -SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<7> | IV_TRUE | shifting2 - -FB_INSTANCE | FOOBAR1_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0 -FBPIN | 1 | spidataout<3> | 1 | NULL | 0 | NULL | 0 -FBPIN | 2 | spidataout<2> | 1 | NULL | 0 | NULL | 0 | 1 | 49152 -FBPIN | 3 | spidataout<1> | 1 | NULL | 0 | NULL | 0 -FBPIN | 4 | spidataout<0> | 1 | NULL | 0 | NULL | 0 -FBPIN | 5 | int_dout<0> | 1 | N3017 | 1 | cpu_d<0> | 1 | 2 | 49152 -FBPIN | 6 | int_dout<1> | 1 | N3019 | 1 | cpu_d<1> | 1 | 3 | 49152 -FBPIN | 7 | tmo | 1 | NULL | 0 | NULL | 0 -FBPIN | 8 | int_dout<2> | 1 | N3021 | 1 | cpu_d<2> | 1 | 4 | 49152 -FBPIN | 9 | slaveinten | 1 | cpu_Nphi2_IBUF | 0 | NULL | 0 | 5 | 57344 -FBPIN | 10 | frx | 1 | NULL | 0 | NULL | 0 -FBPIN | 11 | ece | 1 | extclk_IBUF | 0 | NULL | 0 | 6 | 57344 -FBPIN | 12 | divisor<2> | 1 | NULL | 0 | NULL | 0 -FBPIN | 13 | divisor<1> | 1 | NULL | 0 | NULL | 0 -FBPIN | 14 | divisor<0> | 1 | cpu_rnw_IBUF | 0 | NULL | 0 | 7 | 57344 -FBPIN | 15 | int_dout<3> | 1 | N3023 | 1 | cpu_d<3> | 1 | 8 | 49152 -FBPIN | 16 | cpol | 1 | NULL | 0 | NULL | 0 -FBPIN | 17 | int_dout<4> | 1 | N3025 | 1 | cpu_d<4> | 1 | 9 | 49152 -FBPIN | 18 | cpha | 1 | NULL | 0 | NULL | 0 - -FB_INSTANCE | FOOBAR2_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0 -FBPIN | 1 | EXP6_ | 1 | NULL | 0 | NULL | 0 -FBPIN | 2 | int_mosi | 1 | NULL | 0 | spi_mosi | 1 | 35 | 49152 -FBPIN | 3 | shifting2 | 1 | NULL | 0 | NULL | 0 -FBPIN | 4 | tc | 1 | NULL | 0 | NULL | 0 -FBPIN | 5 | shiftcnt<0> | 1 | a8_IBUF | 0 | NULL | 0 | 36 | 49152 -FBPIN | 6 | $OpTx$INV$24__$INT | 1 | a9_IBUF | 0 | NULL | 0 | 37 | 49152 -FBPIN | 7 | spidatain<7> | 1 | NULL | 0 | NULL | 0 -FBPIN | 8 | spidatain<6> | 1 | a10_IBUF | 0 | NULL | 0 | 38 | 49152 -FBPIN | 9 | cpu_Nirq_OBUFE | 1 | NULL | 0 | cpu_Nirq | 1 | 39 | 51200 -FBPIN | 10 | spidatain<5> | 1 | NULL | 0 | NULL | 0 -FBPIN | 11 | spidatain<4> | 1 | nio_sel_IBUF | 0 | NULL | 0 | 40 | 53248 -FBPIN | 12 | spidatain<3> | 1 | NULL | 0 | NULL | 0 -FBPIN | 13 | spidatain<2> | 1 | NULL | 0 | NULL | 0 -FBPIN | 14 | NULL | 0 | spi_int_IBUF | 0 | NULL | 0 | 42 | 53248 -FBPIN | 15 | NULL | 0 | nio_stb_IBUF | 0 | NULL | 0 | 43 | 49152 -FBPIN | 17 | NULL | 0 | spi_miso_IBUF | 0 | NULL | 0 | 44 | 49152 -FBPIN | 18 | start_shifting/start_shifting_RSTF__$INT | 1 | NULL | 0 | NULL | 0 - -FB_INSTANCE | FOOBAR3_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0 -FBPIN | 2 | int_dout<5> | 1 | N3027 | 1 | cpu_d<5> | 1 | 11 | 49152 -FBPIN | 5 | int_dout<6> | 1 | N3029 | 1 | cpu_d<6> | 1 | 12 | 49152 -FBPIN | 8 | int_dout<7> | 1 | N3031 | 1 | cpu_d<7> | 1 | 13 | 49152 -FBPIN | 9 | noe_OBUF | 1 | NULL | 0 | noe | 1 | 14 | 49152 -FBPIN | 11 | NULL | 0 | Ncs2_IBUF | 0 | NULL | 0 | 18 | 49152 -FBPIN | 14 | NULL | 0 | cpu_Nres_IBUF | 0 | NULL | 0 | 19 | 49152 -FBPIN | 15 | ng_OBUF | 1 | NULL | 0 | ng | 1 | 20 | 49152 -FBPIN | 16 | NULL | 0 | cpu_a_1_IBUF | 0 | NULL | 0 | 24 | 49152 -FBPIN | 17 | add_dec/XLXN_11 | 1 | cpu_a_0_IBUF | 0 | NULL | 0 | 22 | 49152 -FBPIN | 18 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | NULL | 0 | NULL | 0 - -FB_INSTANCE | FOOBAR4_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0 -FBPIN | 1 | shiftdone | 1 | NULL | 0 | NULL | 0 -FBPIN | 2 | b8_OBUF | 1 | NULL | 0 | b8 | 1 | 25 | 49152 -FBPIN | 3 | start_shifting | 1 | NULL | 0 | NULL | 0 -FBPIN | 4 | spidataout<7> | 1 | NULL | 0 | NULL | 0 -FBPIN | 5 | b9_OBUF | 1 | NULL | 0 | b9 | 1 | 26 | 49152 -FBPIN | 6 | spidataout<6> | 1 | NULL | 0 | NULL | 0 -FBPIN | 7 | spidataout<5> | 1 | NULL | 0 | NULL | 0 -FBPIN | 8 | b10_OBUF | 1 | NULL | 0 | b10 | 1 | 27 | 49152 -FBPIN | 9 | spidataout<4> | 1 | NULL | 0 | NULL | 0 -FBPIN | 10 | spidatain<1> | 1 | NULL | 0 | NULL | 0 -FBPIN | 11 | slavesel | 1 | NULL | 0 | spi_Nsel | 1 | 28 | 49152 -FBPIN | 12 | spidatain<0> | 1 | NULL | 0 | NULL | 0 -FBPIN | 13 | shiftcnt<3> | 1 | NULL | 0 | NULL | 0 -FBPIN | 14 | led_OBUF | 1 | NULL | 0 | led | 1 | 29 | 49152 -FBPIN | 15 | shiftcnt<2> | 1 | NULL | 0 | NULL | 0 | 33 | 49152 -FBPIN | 16 | shiftcnt<1> | 1 | NULL | 0 | NULL | 0 -FBPIN | 17 | int_sclk | 1 | NULL | 0 | spi_sclk | 1 | 34 | 49152 -FBPIN | 18 | ier | 1 | NULL | 0 | NULL | 0 - -FB_INSTANCE | INPUTPINS_FOOBAR5_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0 - -BUSINFO | CPU_A<1:0> | 2 | 0 | 0 | cpu_a<0> | 1 | cpu_a<1> | 0 -BUSINFO | CPU_D<7:0> | 8 | 0 | 2 | cpu_d<0> | 7 | cpu_d<1> | 6 | cpu_d<2> | 5 | cpu_d<3> | 4 | cpu_d<4> | 3 | cpu_d<5> | 2 | cpu_d<6> | 1 | cpu_d<7> | 0 - -FB_ORDER_OF_INPUTS | FOOBAR1_ | 0 | spidataout<3> | NULL | 1 | spidataout<2> | NULL | 2 | spidataout<1> | NULL | 3 | spidataout<0> | NULL | 4 | cpu_d<3> | 8 -FB_ORDER_OF_INPUTS | FOOBAR1_ | 6 | tmo | NULL | 8 | slaveinten | NULL | 9 | spidatain<1> | NULL | 10 | ece | NULL | 11 | divisor<2> | NULL -FB_ORDER_OF_INPUTS | FOOBAR1_ | 12 | divisor<1> | NULL | 13 | divisor<0> | NULL | 17 | cpu_Nres | 19 | 21 | spidatain<4> | NULL | 22 | spi_int | 42 -FB_ORDER_OF_INPUTS | FOOBAR1_ | 29 | cpu_d<0> | 2 | 31 | cpu_rnw | 7 | 32 | cpu_d<4> | 9 | 33 | cpu_d<1> | 3 | 36 | cpu_a<0> | 22 -FB_ORDER_OF_INPUTS | FOOBAR1_ | 39 | cpu_a<1> | 24 | 40 | cpu_d<2> | 4 | 41 | spidatain<2> | NULL | 42 | slavesel | NULL | 43 | cpha | NULL -FB_ORDER_OF_INPUTS | FOOBAR1_ | 44 | spidatain<0> | NULL | 45 | frx | NULL | 47 | Ncs2 | 18 | 50 | spidatain<3> | NULL | 52 | cpol | NULL -FB_ORDER_OF_INPUTS | FOOBAR1_ | 53 | cpu_Nphi2 | 5 - -FB_IMUX_INDEX | FOOBAR1_ | 0 | 1 | 2 | 3 | 130 | -1 | 6 | -1 | 8 | 63 | 10 | 11 | 12 | 13 | -1 | -1 | -1 | 125 | -1 | -1 | -1 | 28 | 98 | -1 | -1 | -1 | -1 | -1 | -1 | 108 | -1 | 126 | 132 | 110 | -1 | -1 | 121 | -1 | -1 | 111 | 114 | 30 | 64 | 17 | 65 | 9 | -1 | 131 | -1 | -1 | 29 | -1 | 15 | 120 - - -FB_ORDER_OF_INPUTS | FOOBAR2_ | 0 | shiftdone | NULL | 2 | start_shifting | NULL | 3 | spidataout<7> | NULL | 5 | spidataout<6> | NULL | 7 | spidatain<6> | NULL -FB_ORDER_OF_INPUTS | FOOBAR2_ | 9 | spidatain<5> | NULL | 10 | spidatain<4> | NULL | 11 | spidatain<3> | NULL | 12 | spidatain<2> | NULL | 14 | extclk | 6 -FB_ORDER_OF_INPUTS | FOOBAR2_ | 15 | shiftcnt<1> | NULL | 17 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | NULL | 18 | cpu_a<1> | 24 | 27 | shiftcnt<2> | NULL | 28 | cpu_Nres | 19 -FB_ORDER_OF_INPUTS | FOOBAR2_ | 31 | $OpTx$INV$24__$INT.UIM | NULL | 33 | spidataout<3> | NULL | 36 | spidataout<4> | NULL | 37 | spidataout<1> | NULL | 38 | spidatain<1> | NULL -FB_ORDER_OF_INPUTS | FOOBAR2_ | 39 | tmo | NULL | 40 | shiftcnt<0> | NULL | 43 | cpu_a<0> | 22 | 44 | spidataout<2> | NULL | 46 | spidataout<0> | NULL -FB_ORDER_OF_INPUTS | FOOBAR2_ | 47 | Ncs2 | 18 | 48 | shifting2 | NULL | 49 | spidataout<5> | NULL | 50 | ece | NULL | 51 | shiftcnt<3> | NULL -FB_ORDER_OF_INPUTS | FOOBAR2_ | 53 | cpu_Nphi2 | 5 - -FB_IMUX_INDEX | FOOBAR2_ | 54 | -1 | 56 | 57 | -1 | 59 | -1 | 25 | -1 | 27 | 28 | 29 | 30 | -1 | 122 | 69 | -1 | 53 | 111 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 68 | 125 | -1 | -1 | 23 | -1 | 0 | -1 | -1 | 62 | 2 | 63 | 6 | 22 | -1 | -1 | 121 | 1 | -1 | 3 | 131 | 20 | 60 | 10 | 66 | -1 | 120 - - -FB_ORDER_OF_INPUTS | FOOBAR3_ | 0 | cpu_rnw | 7 | 2 | shifting2 | NULL | 3 | tc | NULL | 5 | Ncs2 | 18 | 6 | spidatain<7> | NULL -FB_ORDER_OF_INPUTS | FOOBAR3_ | 8 | a8 | 36 | 10 | a9 | 37 | 12 | a10 | 38 | 16 | add_dec/XLXN_11 | NULL | 17 | ier | NULL -FB_ORDER_OF_INPUTS | FOOBAR3_ | 18 | cpu_a<1> | 24 | 22 | spi_int | 42 | 28 | spidatain<6> | NULL | 36 | cpu_a<0> | 22 | 41 | slaveinten | NULL -FB_ORDER_OF_INPUTS | FOOBAR3_ | 43 | start_shifting | NULL | 45 | nio_stb | 43 | 50 | nio_sel | 40 | 52 | spidatain<5> | NULL | 53 | cpu_Nphi2 | 5 - -FB_IMUX_INDEX | FOOBAR3_ | 126 | -1 | 20 | 21 | -1 | 131 | 24 | -1 | 80 | -1 | 82 | -1 | 84 | -1 | -1 | -1 | 52 | 71 | 111 | -1 | -1 | -1 | 98 | -1 | -1 | -1 | -1 | -1 | 25 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 121 | -1 | -1 | -1 | -1 | 8 | -1 | 56 | -1 | 102 | -1 | -1 | -1 | -1 | 92 | -1 | 27 | 120 - - -FB_ORDER_OF_INPUTS | FOOBAR4_ | 0 | shiftdone | NULL | 2 | shifting2 | NULL | 3 | spidataout<7> | NULL | 4 | shiftcnt<0> | NULL | 5 | Ncs2 | 18 -FB_ORDER_OF_INPUTS | FOOBAR4_ | 6 | spidataout<5> | NULL | 8 | spidataout<4> | NULL | 9 | frx | NULL | 10 | slavesel | NULL | 11 | spidatain<0> | NULL -FB_ORDER_OF_INPUTS | FOOBAR4_ | 12 | shiftcnt<3> | NULL | 13 | cpu_a<0> | 22 | 14 | shiftcnt<2> | NULL | 15 | cpol | NULL | 16 | cpu_d<7> | 13 -FB_ORDER_OF_INPUTS | FOOBAR4_ | 17 | cpha | NULL | 19 | spi_miso | 44 | 21 | cpu_d<6> | 12 | 23 | a8 | 36 | 26 | $OpTx$INV$24__$INT.UIM | NULL -FB_ORDER_OF_INPUTS | FOOBAR4_ | 28 | a9 | 37 | 29 | cpu_d<0> | 2 | 30 | spidataout<6> | NULL | 31 | cpu_rnw | 7 | 32 | a10 | 38 -FB_ORDER_OF_INPUTS | FOOBAR4_ | 35 | shiftcnt<1> | NULL | 39 | cpu_a<1> | 24 | 42 | cpu_d<5> | 11 | 43 | start_shifting | NULL | 44 | cpu_d<4> | 9 -FB_ORDER_OF_INPUTS | FOOBAR4_ | 46 | cpu_Nres | 19 | 47 | ier | NULL | 50 | nio_sel | 40 | 53 | start_shifting/start_shifting_RSTF__$INT.UIM | NULL - -FB_IMUX_INDEX | FOOBAR4_ | 54 | -1 | 20 | 57 | 22 | 131 | 60 | -1 | 62 | 9 | 64 | 65 | 66 | 121 | 68 | 15 | 142 | 17 | -1 | 104 | -1 | 138 | -1 | 80 | -1 | -1 | 23 | -1 | 82 | 108 | 59 | 126 | 84 | -1 | -1 | 69 | -1 | -1 | -1 | 111 | -1 | -1 | 134 | 56 | 132 | -1 | 125 | 71 | -1 | -1 | 92 | -1 | -1 | 35 - - -GLOBAL_FCLK | extclk | 1 | 1 diff --git a/VHDL/spi6502b.xml b/VHDL/spi6502b.xml deleted file mode 100644 index 8efeb2e..0000000 --- a/VHDL/spi6502b.xml +++ /dev/null @@ -1,3 +0,0 @@ - - -spi6502b.rptC:/Xilinx/xc9500xl/data/xc9572xl.chpspi6502b.mfd
diff --git a/VHDL/spi6502b_build.xml b/VHDL/spi6502b_build.xml deleted file mode 100644 index b0ba209..0000000 --- a/VHDL/spi6502b_build.xml +++ /dev/null @@ -1,205 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/VHDL/tmperr.err b/VHDL/tmperr.err deleted file mode 100644 index e69de29..0000000 diff --git a/VHDL/userlang.tpl b/VHDL/userlang.tpl deleted file mode 100644 index 7f80404..0000000 --- a/VHDL/userlang.tpl +++ /dev/null @@ -1,6 +0,0 @@ -[Verilog.User Templates] -type=folder -[VHDL.User Templates] -type=folder -[ABEL.User Templates] -type=folder diff --git a/_ngo/netlist.lst b/_ngo/netlist.lst deleted file mode 100644 index 42a41ae..0000000 --- a/_ngo/netlist.lst +++ /dev/null @@ -1,2 +0,0 @@ -C:\sources\AppleIISd\spi6502b.ngc 1494461294 -OK diff --git a/address_decoder._u_ b/address_decoder._u_ deleted file mode 100644 index e69de29..0000000 diff --git a/address_decoder.lfp b/address_decoder.lfp deleted file mode 100644 index 273ab0b..0000000 --- a/address_decoder.lfp +++ /dev/null @@ -1,15 +0,0 @@ -# begin LFP file C:\sources\AppleIISd\address_decoder.lfp -designfile address_decoder.ngd -INST "address_decoder" COLOR=15 ; -NET "OE" COLOR=6 ; -NET "IO_STB" COLOR=6 ; -NET "IO_SEL" COLOR=6 ; -NET "extclk" COLOR=6 ; -NET "A10_B" COLOR=6 ; -NET "A10" COLOR=6 ; -NET "A9_B" COLOR=6 ; -NET "A9" COLOR=6 ; -NET "A8_B" COLOR=6 ; -NET "A8" COLOR=6 ; -INST "XLXI_16" COLOR=7 ; -INST "XLXI_16/U0" COLOR=7 ; diff --git a/address_decoder.ucf b/address_decoder.ucf deleted file mode 100644 index a6d30f8..0000000 --- a/address_decoder.ucf +++ /dev/null @@ -1,19 +0,0 @@ -#PACE: Start of Constraints generated by PACE - -#PACE: Start of PACE I/O Pin Assignments -NET "A10" LOC = "P37" ; -NET "A10_B" LOC = "P38" ; -NET "A8" LOC = "P27" ; -NET "A8_B" LOC = "P29" ; -NET "A9" LOC = "P33" ; -NET "A9_B" LOC = "P36" ; -NET "extclk" LOC = "p6" ; -NET "IO_SEL" LOC = "P39" ; -NET "IO_STB" LOC = "P40" ; -NET "OE" LOC = "P1" ; - -#PACE: Start of PACE Area Constraints - -#PACE: Start of PACE Prohibit Constraints - -#PACE: End of Constraints generated by PACE diff --git a/address_decoder.vhf b/address_decoder.vhf deleted file mode 100644 index a83b4cf..0000000 --- a/address_decoder.vhf +++ /dev/null @@ -1,288 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (c) 1995-2003 Xilinx, Inc. --- All Right Reserved. --------------------------------------------------------------------------------- --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version : 6.3.03i --- \ \ Application : --- / / Filename : address_decoder.vhf --- /___/ /\ Timestamp : 05/11/2017 02:05:37 --- \ \ / \ --- \___\/\___\ --- ---Command: ---Design Name: FD_MXILINX_address_decoder --- - -library ieee; -use ieee.std_logic_1164.ALL; -use ieee.numeric_std.ALL; --- synopsys translate_off -library UNISIM; -use UNISIM.Vcomponents.ALL; --- synopsys translate_on - -entity FD_MXILINX_address_decoder is - port ( C : in std_logic; - D : in std_logic; - Q : out std_logic); -end FD_MXILINX_address_decoder; - -architecture BEHAVIORAL of FD_MXILINX_address_decoder is - attribute BOX_TYPE : string ; - signal XLXN_4 : std_logic; - component GND - port ( G : out std_logic); - end component; - attribute BOX_TYPE of GND : component is "BLACK_BOX"; - - component FDCP - port ( C : in std_logic; - CLR : in std_logic; - D : in std_logic; - PRE : in std_logic; - Q : out std_logic); - end component; - attribute BOX_TYPE of FDCP : component is "BLACK_BOX"; - -begin - I_36_43 : GND - port map (G=>XLXN_4); - - U0 : FDCP - port map (C=>C, - CLR=>XLXN_4, - D=>D, - PRE=>XLXN_4, - Q=>Q); - -end BEHAVIORAL; - - --------------------------------------------------------------------------------- --- Copyright (c) 1995-2003 Xilinx, Inc. --- All Right Reserved. --------------------------------------------------------------------------------- --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version : 6.3.03i --- \ \ Application : --- / / Filename : address_decoder.vhf --- /___/ /\ Timestamp : 05/11/2017 02:05:37 --- \ \ / \ --- \___\/\___\ --- ---Command: ---Design Name: FDRS_MXILINX_address_decoder --- - -library ieee; -use ieee.std_logic_1164.ALL; -use ieee.numeric_std.ALL; --- synopsys translate_off -library UNISIM; -use UNISIM.Vcomponents.ALL; --- synopsys translate_on - -entity FDRS_MXILINX_address_decoder is - port ( C : in std_logic; - D : in std_logic; - R : in std_logic; - S : in std_logic; - Q : out std_logic); -end FDRS_MXILINX_address_decoder; - -architecture BEHAVIORAL of FDRS_MXILINX_address_decoder is - attribute BOX_TYPE : string ; - attribute HU_SET : string ; - signal XLXN_6 : std_logic; - signal XLXN_7 : std_logic; - signal XLXN_8 : std_logic; - component AND2B1 - port ( I0 : in std_logic; - I1 : in std_logic; - O : out std_logic); - end component; - attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX"; - - component OR2 - port ( I0 : in std_logic; - I1 : in std_logic; - O : out std_logic); - end component; - attribute BOX_TYPE of OR2 : component is "BLACK_BOX"; - - component FD_MXILINX_address_decoder - port ( C : in std_logic; - D : in std_logic; - Q : out std_logic); - end component; - - attribute HU_SET of U0 : label is "U0_0"; -begin - I_36_112 : AND2B1 - port map (I0=>R, - I1=>S, - O=>XLXN_6); - - I_36_113 : AND2B1 - port map (I0=>R, - I1=>D, - O=>XLXN_8); - - I_36_120 : OR2 - port map (I0=>XLXN_6, - I1=>XLXN_8, - O=>XLXN_7); - - U0 : FD_MXILINX_address_decoder - port map (C=>C, - D=>XLXN_7, - Q=>Q); - -end BEHAVIORAL; - - --------------------------------------------------------------------------------- --- Copyright (c) 1995-2003 Xilinx, Inc. --- All Right Reserved. --------------------------------------------------------------------------------- --- ____ ____ --- / /\/ / --- /___/ \ / Vendor: Xilinx --- \ \ \/ Version : 6.3.03i --- \ \ Application : --- / / Filename : address_decoder.vhf --- /___/ /\ Timestamp : 05/11/2017 02:05:37 --- \ \ / \ --- \___\/\___\ --- ---Command: ---Design Name: address_decoder --- - -library ieee; -use ieee.std_logic_1164.ALL; -use ieee.numeric_std.ALL; --- synopsys translate_off -library UNISIM; -use UNISIM.Vcomponents.ALL; --- synopsys translate_on - -entity address_decoder is - port ( A8 : in std_logic; - A9 : in std_logic; - A10 : in std_logic; - CLK : in std_logic; - NIO_SEL : in std_logic; - NIO_STB : in std_logic; - A8_B : out std_logic; - A9_B : out std_logic; - A10_B : out std_logic; - NOE : out std_logic); -end address_decoder; - -architecture BEHAVIORAL of address_decoder is - attribute BOX_TYPE : string ; - attribute HU_SET : string ; - signal XLXN_4 : std_logic; - signal XLXN_10 : std_logic; - signal XLXN_11 : std_logic; - signal XLXN_14 : std_logic; - signal XLXN_19 : std_logic; - component NAND2 - port ( I0 : in std_logic; - I1 : in std_logic; - O : out std_logic); - end component; - attribute BOX_TYPE of NAND2 : component is "BLACK_BOX"; - - component FDRS_MXILINX_address_decoder - port ( C : in std_logic; - D : in std_logic; - R : in std_logic; - S : in std_logic; - Q : out std_logic); - end component; - - component VCC - port ( P : out std_logic); - end component; - attribute BOX_TYPE of VCC : component is "BLACK_BOX"; - - component AND2 - port ( I0 : in std_logic; - I1 : in std_logic; - O : out std_logic); - end component; - attribute BOX_TYPE of AND2 : component is "BLACK_BOX"; - - component INV - port ( I : in std_logic; - O : out std_logic); - end component; - attribute BOX_TYPE of INV : component is "BLACK_BOX"; - - component AND4B1 - port ( I0 : in std_logic; - I1 : in std_logic; - I2 : in std_logic; - I3 : in std_logic; - O : out std_logic); - end component; - attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX"; - - attribute HU_SET of XLXI_16 : label is "XLXI_16_1"; -begin - XLXI_13 : NAND2 - port map (I0=>NIO_SEL, - I1=>NIO_STB, - O=>XLXN_4); - - XLXI_14 : NAND2 - port map (I0=>XLXN_11, - I1=>XLXN_4, - O=>NOE); - - XLXI_16 : FDRS_MXILINX_address_decoder - port map (C=>CLK, - D=>XLXN_14, - R=>XLXN_10, - S=>XLXN_19, - Q=>XLXN_11); - - XLXI_17 : VCC - port map (P=>XLXN_14); - - XLXI_18 : AND2 - port map (I0=>A10, - I1=>NIO_SEL, - O=>A10_B); - - XLXI_19 : AND2 - port map (I0=>A9, - I1=>NIO_SEL, - O=>A9_B); - - XLXI_20 : AND2 - port map (I0=>A8, - I1=>NIO_SEL, - O=>A8_B); - - XLXI_22 : INV - port map (I=>NIO_SEL, - O=>XLXN_19); - - XLXI_23 : AND4B1 - port map (I0=>NIO_STB, - I1=>A10, - I2=>A9, - I3=>A8, - O=>XLXN_10); - -end BEHAVIORAL; - - diff --git a/address_decoder_html/fit/applet.js b/address_decoder_html/fit/applet.js deleted file mode 100644 index d255dd2..0000000 --- a/address_decoder_html/fit/applet.js +++ /dev/null @@ -1,128 +0,0 @@ - var tmpStr = ""; - var waitWin; - - function openWait() { - waitWin = window.open("wait.htm", "wait", - "toolbar=no,location=no,"+ - "directories=no,status=no,menubar=no,scrollbars=no,"+ - "resizable=no,width=300,height=50" ); - } - - function closeWait() { if (waitWin) waitWin.close(); } - - function setMsg(msg){ - - parent.leftnav.setAppletMsg( msg ); - // now send it reload forces - // call to applet paint - location.reload(); - } - - function getMsg(){ - - return( parent.leftnav.getAppletMsg() ); - } - - function resetMsg(){ parent.leftnav.setAppletMsg(""); } - - function printAppletPkg() { - if( isNS() ){ - setMsg("cmd printPkg "); - } - else{ - document.ChipViewerApplet.PrintPkg(); - } - } - - function showAppletGraphicMC(mc) { - if( isNS() ){ - setMsg("cmd showMac " + mc); - } - else{ - document.ChipViewerApplet.ShowMac(mc); - } - } - - function ShowMC() { showAppletGraphicMC(tmpStr); } - - function showAppletGraphicFB(fb) { - if( isNS() ){ - setMsg("cmd showFB " + fb); - } - else{ - document.ChipViewerApplet.ShowFB(fb); - } - } - - function showAppletGraphicPin(pin) { - if( isNS() ){ - setMsg("cmd showPin " + pin); - } - else{ - document.ChipViewerApplet.ShowPin(pin); - } - } - - function ShowFB() { showAppletGraphicFB(tmpStr); } - - function isNS() { - return ((navigator.appName.indexOf("Netscape") >= 0) && (parseFloat(navigator.appVersion) < 5) ) ? true : false; - } - - function isIE(){ - var agt=navigator.userAgent.toLowerCase(); - return( ( (agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1) ) ? true: false ); - } - - function waitUntilOK() { - if (!waitWin) openWait(); - if (isNS()) { - if (document.ChipViewerApplet.isActive()) closeWait(); - else settimeout("waitUntilOK()",100); - } - else { - if (document.ChipViewerApplet.readyState == 4) closeWait(); - else settimeout("waitUntilOK()",100); - } - } - - - // check that the applet if file has been generated - // this can only be done if the applets been loaded. - function fileExists(fileName){ - - if( document.ChipViewerApplet.readyState != 4 ) { - window.alert("Navigation disabled until the applet is loaded." ); - } - if( isIE() ){ - if( parent.leftnav.getAppletPermission() == 1 ){ - if( document.ChipViewerApplet.TestFileExists(fileName) == 1 ){ - window.alert("file exist tests true" ); - return( true ); - } - } - else{ - window.alert("file exist returns true no permission" ); - return( true ); - } - } - else{ - return( true ); - } - window.alert("file exist returns false" ); - return( false ); - } - - - - function setPermission(){ - - if( isIE() ){ - if( document.ChipViewerApplet.granted() ){ - parent.leftnav.setAppletPermission(); - } - } - else{ - return( true ); - } - } diff --git a/address_decoder_html/fit/appletref.htm b/address_decoder_html/fit/appletref.htm deleted file mode 100644 index 968eb0a..0000000 --- a/address_decoder_html/fit/appletref.htm +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - - - - - - diff --git a/address_decoder_html/fit/asciidoc.htm b/address_decoder_html/fit/asciidoc.htm deleted file mode 100644 index 3455598..0000000 --- a/address_decoder_html/fit/asciidoc.htm +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - -Text Report - - - - - - - - - - - - - - - - - - - - - - - - -

Text Report

- -

Selecting Text - Report from the left-hand frame will give you a printable text version - of the fitter report.  It - contains sections similar to those of the XML report (a summary section, - errors and warnings, mapped logic, function blocks, function block details, - a text-graphical display of the pinout, and a summary of compiler options), - but it is not easily navigable.  It - is best to use the text report only when you need to print out a hard - copy of the fitter results.

- - - - diff --git a/address_decoder_html/fit/backtop.jpg b/address_decoder_html/fit/backtop.jpg deleted file mode 100644 index c537825..0000000 Binary files a/address_decoder_html/fit/backtop.jpg and /dev/null differ diff --git a/address_decoder_html/fit/beginstraight.gif b/address_decoder_html/fit/beginstraight.gif deleted file mode 100644 index 1a75177..0000000 Binary files a/address_decoder_html/fit/beginstraight.gif and /dev/null differ diff --git a/address_decoder_html/fit/blank.gif b/address_decoder_html/fit/blank.gif deleted file mode 100644 index 1d11fa9..0000000 Binary files a/address_decoder_html/fit/blank.gif and /dev/null differ diff --git a/address_decoder_html/fit/blank.htm b/address_decoder_html/fit/blank.htm deleted file mode 100644 index 18ecdcb..0000000 --- a/address_decoder_html/fit/blank.htm +++ /dev/null @@ -1 +0,0 @@ - diff --git a/address_decoder_html/fit/briefview.jpg b/address_decoder_html/fit/briefview.jpg deleted file mode 100644 index 3006953..0000000 Binary files a/address_decoder_html/fit/briefview.jpg and /dev/null differ diff --git a/address_decoder_html/fit/check.htm b/address_decoder_html/fit/check.htm deleted file mode 100644 index 4dc9562..0000000 --- a/address_decoder_html/fit/check.htm +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/address_decoder_html/fit/checkNS4.htm b/address_decoder_html/fit/checkNS4.htm deleted file mode 100644 index 349d05d..0000000 --- a/address_decoder_html/fit/checkNS4.htm +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/address_decoder_html/fit/contact.gif b/address_decoder_html/fit/contact.gif deleted file mode 100644 index 418b282..0000000 Binary files a/address_decoder_html/fit/contact.gif and /dev/null differ diff --git a/address_decoder_html/fit/coolrunnerII_logo.jpg b/address_decoder_html/fit/coolrunnerII_logo.jpg deleted file mode 100644 index 1b57ddc..0000000 Binary files a/address_decoder_html/fit/coolrunnerII_logo.jpg and /dev/null differ diff --git a/address_decoder_html/fit/coolrunner_logo.jpg b/address_decoder_html/fit/coolrunner_logo.jpg deleted file mode 100644 index 01e20a5..0000000 Binary files a/address_decoder_html/fit/coolrunner_logo.jpg and /dev/null differ diff --git a/address_decoder_html/fit/education.gif b/address_decoder_html/fit/education.gif deleted file mode 100644 index 07e9507..0000000 Binary files a/address_decoder_html/fit/education.gif and /dev/null differ diff --git a/address_decoder_html/fit/endmkt.gif b/address_decoder_html/fit/endmkt.gif deleted file mode 100644 index 15371dc..0000000 Binary files a/address_decoder_html/fit/endmkt.gif and /dev/null differ diff --git a/address_decoder_html/fit/eqns.js b/address_decoder_html/fit/eqns.js deleted file mode 100644 index 3d35fc4..0000000 --- a/address_decoder_html/fit/eqns.js +++ /dev/null @@ -1,902 +0,0 @@ -var eqnType = 0; -var spcStr = " "; -var nlStr = "
"; -var tabStr = spcStr + spcStr + spcStr + spcStr + spcStr; -var nlTabStr = nlStr + tabStr; -var rClrS = ""; -var rClrE = ""; -var cClrS = ""; -var cClrE = ""; - -var abelOper = new Array(); -abelOper["GND"] = new Array("Gnd"); -abelOper["VCC"] = new Array("Vcc"); -abelOper["NOT"] = new Array(rClrS + "!" + rClrE); -abelOper["AND"] = new Array(rClrS + "*" + rClrE); -abelOper["OR"] = new Array(rClrS + "#" + rClrE); -abelOper["XOR"] = new Array(rClrS + "$" + rClrE); -abelOper["EQUAL_COLON"] = new Array(":= "); -abelOper["EQUAL"] = new Array("= "); -abelOper["ASSIGN"] = new Array(""); -abelOper["OPEN_NEGATE"] = new Array("("); -abelOper["CLOSE_NEGATE"] = new Array(")"); -abelOper["OPEN_PTERM"] = new Array(""); -abelOper["CLOSE_PTERM"] = new Array(""); -abelOper["OPEN_BRACE"] = new Array("<"); -abelOper["CLOSE_BRACE"] = new Array(">"); -abelOper["INVALID_OPEN_BRACE"] = new Array("<"); -abelOper["INVALID_CLOSE_BRACE"] = new Array(">"); - -abelOper["ENDLN"] = new Array(";"); -abelOper["COMMENT"] = new Array("//"); -abelOper["IMPORT"] = new Array(";Imported pterms "); -abelOper["GCK_COM"] = new Array("GCK"); -abelOper["GTS_COM"] = new Array("GTS"); -abelOper["GSR_COM"] = new Array("GSR"); -abelOper["START_EQN"] = new Array(""); -abelOper["END_EQN"] = new Array(""); - -abelOper["_I"] = new Array(".I"); -abelOper["_T"] = new Array(".T"); -abelOper["_D"] = new Array(".D"); -abelOper["_C"] = new Array(".CLK"); -abelOper["_LH"] = new Array(".LH"); -abelOper["_CLR"] = new Array(".AR"); -abelOper["_PRE"] = new Array(".AP"); -abelOper["_CE"] = new Array(".CE"); -abelOper["_OE"] = new Array(".OE"); - -abelOper["OE_START"] = new Array(" <= "); -abelOper["OE_WHEN"] = new Array(" when "); -abelOper["OE_EQUAL"] = new Array(" = "); -abelOper["OE_ELSE"] = new Array(" else "); -abelOper["B0"] = new Array("'0'"); -abelOper["B1"] = new Array("'1'"); -abelOper["BZ"] = new Array("'Z'"); - -abelOper["FD"] = new Array(".D"); -abelOper["FT"] = new Array(".T"); -abelOper["FDD"] = new Array(".D"); -abelOper["FTD"] = new Array(".T"); -abelOper["LD"] = new Array(".LH"); -abelOper["Q"] = new Array(".Q"); - -var vhdlOper = new Array(); -vhdlOper["GND"] = new Array("'0'"); -vhdlOper["VCC"] = new Array("'1'"); -vhdlOper["NOT"] = new Array(rClrS + "NOT " + rClrE); -vhdlOper["AND"] = new Array(rClrS + "AND" + rClrE); -vhdlOper["OR"] = new Array(rClrS + "OR" + rClrE); -vhdlOper["XOR"] = new Array(rClrS + "XOR" + rClrE); -vhdlOper["EQUAL_COLON"] = new Array("<= "); -vhdlOper["EQUAL"] = new Array("<= "); -vhdlOper["ASSIGN"] = new Array(""); -vhdlOper["OPEN_NEGATE"] = new Array("("); -vhdlOper["CLOSE_NEGATE"] = new Array(")"); -vhdlOper["OPEN_PTERM"] = new Array("("); -vhdlOper["CLOSE_PTERM"] = new Array(")"); -vhdlOper["OPEN_BRACE"] = new Array("("); -vhdlOper["CLOSE_BRACE"] = new Array(")"); -vhdlOper["INVALID_OPEN_BRACE"] = new Array("<"); -vhdlOper["INVALID_CLOSE_BRACE"] = new Array(">"); - -vhdlOper["ENDLN"] = new Array(";"); -vhdlOper["COMMENT"] = new Array("--"); -vhdlOper["IMPORT"] = new Array(""); -vhdlOper["GCK_COM"] = new Array("GCK"); -vhdlOper["GTS_COM"] = new Array("GTS"); -vhdlOper["GSR_COM"] = new Array("GSR"); -vhdlOper["START_EQN"] = new Array(rClrS + "port map" + rClrE + " ("); -vhdlOper["END_EQN"] = new Array(")"); - -vhdlOper["_I"] = new Array("_I"); -vhdlOper["_T"] = new Array("_T"); -vhdlOper["_D"] = new Array("_D"); -vhdlOper["_C"] = new Array("_C"); -vhdlOper["_LH"] = new Array("_C"); -vhdlOper["_CLR"] = new Array("_CLR"); -vhdlOper["_PRE"] = new Array("_PRE"); -vhdlOper["_CE"] = new Array("_CE"); -vhdlOper["_OE"] = new Array("_OE"); - -vhdlOper["OE_START"] = new Array(" <= "); -vhdlOper["OE_WHEN"] = new Array(" when "); -vhdlOper["OE_EQUAL"] = new Array(" = "); -vhdlOper["OE_ELSE"] = new Array(" else "); -vhdlOper["B0"] = new Array("'0'"); -vhdlOper["B1"] = new Array("'1'"); -vhdlOper["BZ"] = new Array("'Z'"); - -vhdlOper["FD"] = new Array("FDCPE"); -vhdlOper["FT"] = new Array("FTCPE"); -vhdlOper["FDD"] = new Array("FDDCPE"); -vhdlOper["FTD"] = new Array("FTDCPE"); -vhdlOper["LD"] = new Array("LDCP"); -vhdlOper["Q"] = new Array(""); - -var verOper = new Array(); -verOper["GND"] = new Array("1'b0"); -verOper["VCC"] = new Array("1'b1"); -verOper["NOT"] = new Array(rClrS + "!" + rClrE); -verOper["AND"] = new Array(rClrS + "&&" + rClrE); -verOper["OR"] = new Array(rClrS + "||" + rClrE); -verOper["XOR"] = new Array(rClrS + "XOR" + rClrE); -verOper["EQUAL_COLON"] = new Array("= "); -verOper["EQUAL"] = new Array("= "); -verOper["ASSIGN"] = new Array("assign "); -verOper["OPEN_NEGATE"] = new Array("("); -verOper["CLOSE_NEGATE"] = new Array(")"); -verOper["OPEN_PTERM"] = new Array("("); -verOper["CLOSE_PTERM"] = new Array(")"); -verOper["OPEN_BRACE"] = new Array("["); -verOper["CLOSE_BRACE"] = new Array("]"); -verOper["INVALID_OPEN_BRACE"] = new Array("<"); -verOper["INVALID_CLOSE_BRACE"] = new Array(">"); - -verOper["ENDLN"] = new Array(";"); -verOper["COMMENT"] = new Array("//"); -verOper["IMPORT"] = new Array(""); -verOper["GCK_COM"] = new Array("GCK"); -verOper["GTS_COM"] = new Array("GTS"); -verOper["GSR_COM"] = new Array("GSR"); -verOper["START_EQN"] = new Array(" ("); -verOper["END_EQN"] = new Array(")"); - -verOper["_I"] = new Array("_I"); -verOper["_T"] = new Array("_T"); -verOper["_D"] = new Array("_D"); -verOper["_C"] = new Array("_C"); -verOper["_LH"] = new Array("_C"); -verOper["_CLR"] = new Array("_CLR"); -verOper["_PRE"] = new Array("_PRE"); -verOper["_CE"] = new Array("_CE"); -verOper["_OE"] = new Array("_OE"); - -verOper["OE_START"] = new Array(" = "); -verOper["OE_WHEN"] = new Array(" ? "); -verOper["OE_EQUAL"] = new Array(""); -verOper["OE_ELSE"] = new Array(" : "); -verOper["B0"] = new Array("1'b0"); -verOper["B1"] = new Array("1'b1"); -verOper["BZ"] = new Array("1'bz"); - -verOper["FD"] = new Array("FDCPE"); -verOper["FT"] = new Array("FTCPE"); -verOper["FDD"] = new Array("FDDCPE"); -verOper["FTD"] = new Array("FTDCPE"); -verOper["LD"] = new Array("LDCP"); -verOper["Q"] = new Array(""); - -var operator = abelOper; - -var pterms = new Array(); -var d1 = new Array(); -var d2 = new Array(); -var clk = new Array(); -var set = new Array(); -var rst = new Array(); -var trst = new Array(); -var d1imp = new Array(); -var d2imp = new Array(); -var clkimp = new Array(); -var setimp = new Array(); -var rstimp = new Array(); -var trstimp = new Array(); -var gblclk = new Array(); -var gblset = new Array(); -var gblrst = new Array(); -var gbltrst = new Array(); -var ce = new Array(); -var ceimp = new Array(); -var prld = new Array(); -var specSig = new Array(); -var clkNegs = new Array(); -var setNegs = new Array(); -var rstNegs = new Array(); -var trstNegs = new Array(); -var ceNegs = new Array(); -var fbnand = new Array(); -var inreg = new Array(); - -var dOneLit = true; - -function setOper(type) { - if (type == "1") { operator = vhdlOper; eqnType = 1; } - else if (type == "2") { operator = verOper; eqnType = 2; } - else { operator = abelOper; eqnType = 0; } -} - -function isXC95() { - if (device.indexOf("95") != -1) return true; - return false; -} - -function is9500() { - if ((device.indexOf("95") != -1) && - (device.indexOf("XL") == -1) && - (device.indexOf("XV") == -1)) return true; - return false; -} - -function retSigType(s) { - var sigType = sigTypes[s]; - var str = operator["Q"]; - if (sigType == "D") str = operator["FD"]; - else if (sigType == "T") str = operator["FT"]; - else if (sigType.indexOf("LATCH") != -1) str = operator["LD"]; - else if (sigType.indexOf("DDEFF") != -1) str = operator["FDD"]; - else if (sigType.indexOf("DEFF") != -1) str = operator["FD"]; - else if (sigType.indexOf("DDFF") != -1) str = operator["FDD"]; - else if (sigType.indexOf("TDFF") != -1) str = operator["FTD"]; - else if (sigType.indexOf("DFF") != -1) str = operator["FD"]; - else if (sigType.indexOf("TFF") != -1) str = operator["FT"]; - return str; -} - -function retSigIndex(signal) { - for (s=0; s 1) str += operator["OPEN_PTERM"]; - for (p=0; p0) str += " " + operator["AND"] + " "; - var neg = 0; - if (sig.indexOf("/") != -1) { - sig = sig.substring(1, sig.length); - str += operator["NOT"]; - neg = 1; - } - - str += retSigName(sig); - } - if (pterms[pt].length > 1) str += operator["CLOSE_PTERM"]; - - return str; -} - -function retFBMC(str) { - return str.substring(0,str.length-2); -} - -function retD1D2(signal) { - var str = ""; - - dOneLit = true; - if (d1[signal]) { - var currImp = ""; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(d1[signal][i]); - } - - if (d2[signal]) str += nlTabStr + operator["XOR"]+ spcStr; - } - - if (d2[signal]) { - var currImp = ""; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(d2[signal][i]); - } - } - - if (str == "GND") str = operator["GND"]; - else if (str == "VCC") str = operator["VCC"]; - else if (!isOneLiteral(str)) { - dOneLit = false; - - var type = retSigType(retSigIndex(signal)); - if ((type == operator["FD"]) || - (type == operator["FDD"])) type = operator["_D"]; - else if ((type == operator["FT"]) || - (type == operator["FTD"])) type = operator["_T"]; - else if (type == operator["LD"] && eqnType) type = "_D"; - - var tmpStr = updateName(retSigName(signal), type); - tmpStr += spcStr + operator["EQUAL_COLON"]; - var idx = retSigIndex(signal); - if (eqnType && sigNegs[idx] == "ON") tmpStr += operator["NOT"] + operator["OPEN_NEGATE"]; - str = tmpStr + str; - if (eqnType && sigNegs[idx] == "ON") str += operator["CLOSE_NEGATE"]; - str += operator["ENDLN"]; - - } - - return str; -} - -function retClk(signal) { - var str = ""; - - if (clk[signal]) { - if (clk[signal].length == 1) { - var pterm = retPterm(clk[signal][0]); - if (clkNegs[signal]) { - str += operator["NOT"]; - if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"]; - } - str += pterm; - if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"]; - } - else { - if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; - var currImp = ""; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(clk[signal][i]); - } - if (clkNegs[signal]) str += operator["CLOSE_NEGATE"]; - str += operator["ENDLN"]; - } - } - else if (gblclk[signal]) { - if (gblclk[signal].length == 1) { - var pterm = retPterm(gblclk[signal][0]); - if (clkNegs[signal]) { - str += operator["NOT"]; - if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"]; - } - str += pterm; - if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"]; - } - else { - if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(gblclk[signal][i]); - } - if (clkNegs[signal]) str += operator["CLOSE_NEGATE"]; - str += operator["ENDLN"] + tabStr + cClrS + - operator["COMMENT"] + spcStr + operator["GCK_COM"] + cClrE; - } - } - else if (eqnType) str += operator["B0"]; - - return str; -} - -function retRst(signal) { - var str = ""; - - if (rst[signal]) { - if (rst[signal].length == 1) { - var currImp; - if (!eqnType && rstimp[signal] && (rstimp[signal][0] == "1")) { - if (currImp != retFBMC(rst[signal][0])) { - currImp = retFBMC(rst[signal][0]); - str += nlStr + operator["IMPORT"] + currImp; - } - } - if (rstNegs[signal]) str += operator["NOT"]; - str += retPterm(rst[signal][0]); - } - else { - var currImp = ""; - if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(rst[signal][i]); - } - if (rstNegs[signal]) str += operator["CLOSE_NEGATE"]; - str += operator["ENDLN"]; - } - } - else if (gblrst[signal]) { - if (gblrst[signal].length == 1) { - if (rstNegs[signal]) str += operator["NOT"]; - str += retPterm(gblrst[signal][0]); - } - else { - if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(gblrst[signal][i]); - } - if (rstNegs[signal]) str += operator["CLOSE_NEGATE"]; - str += operator["ENDLN"] + tabStr + cClrS + - operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE; - } - } - else if (eqnType) str += operator["B0"]; - - return str; -} - -function retSet(signal) { - var str = ""; - - if (set[signal]) { - if (set[signal].length == 1) { - var currImp = ""; - if (!eqnType && setimp[signal] && (setimp[signal][0] == "1")) { - if (currImp != retFBMC(set[signal][0])) { - currImp = retFBMC(set[signal][0]); - str += nlStr + operator["IMPORT"] + currImp; - } - } - if (setNegs[signal]) str += operator["NOT"]; - str += retPterm(set[signal][0]); - } - else { - var currImp = ""; - if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(set[signal][i]); - } - if (setNegs[signal]) str += operator["CLOSE_NEGATE"]; - str += operator["ENDLN"]; - } - } - else if (gblset[signal]) { - if (gblset[signal].length == 1) { - if (setNegs[signal]) str += operator["NOT"]; - str += retPterm(gblset[signal][0]); - } - else { - if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(gblset[signal][i]); - } - if (setNegs[signal]) str += operator["CLOSE_NEGATE"]; - str += operator["ENDLN"] + tabStr + cClrS + - operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE; - } - } - else if (eqnType) str += operator["B0"]; - - return str; -} - -function retCE(signal) { - var str = ""; - - if (ce[signal]) { - if (ce[signal].length == 1) { - var currImp = ""; - if (!eqnType && ceimp[signal] && (ceimp[signal][0] == "1")) { - if (currImp != retFBMC(ce[signal][0])) { - currImp = retFBMC(ce[signal][0]); - str += nlStr + operator["IMPORT"] + currImp; - } - } - if (ceNegs[signal]) str += operator["NOT"]; - str += retPterm(ce[signal][0]); - } - else { - var currImp = ""; - if (ceNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(ce[signal][i]); - } - if (ceNegs[signal]) str += operator["CLOSE_NEGATE"]; - str += operator["ENDLN"]; - } - } - else if (eqnType) str += operator["B1"]; - - return str; -} - -function retTrst(signal) { - var str = ""; - if (trst[signal]) { - if (trstNegs[signal]) - str += operator["NOT"] + operator["OPEN_NEGATE"]; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(trst[signal][i]); - } - if (trstNegs[signal]) str += operator["CLOSE_NEGATE"]; - } - else if (gbltrst[signal]) { - if (trstNegs[signal]) - str += operator["NOT"] + operator["OPEN_NEGATE"]; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(gbltrst[signal][i]); - } - if (trstNegs[signal]) str += operator["CLOSE_NEGATE"]; - } - - str += operator["ENDLN"]; - return str; -} - -function retEqn(signal) { - var str = inregStr = ""; - var iStr = qStr = ""; - var dStr = dEqn = ""; - var cStr = cEqn = ""; - var clrStr = clrEqn = ""; - var preStr = preEqn = ""; - var ceStr = ceEqn = ""; - var oeStr = oeEqn = ""; - var sigName = retSigName(signal); - - var type = retSigType(retSigIndex(signal)); - - if (gbltrst[signal] || trst[signal]) iStr = operator["_I"]; - if (eqnType) qStr = updateName(sigName, iStr); - - if (inreg[signal]) { - if (!eqnType) - inregStr = operator["COMMENT"] + " Direct Input Register" + nlStr; - dStr = retSigName(inreg[signal][0]); - } - else dStr = retD1D2(signal); - if (eqnType && !dOneLit) { - dEqn = dStr; - dStr = dStr.substring(0,dStr.indexOf(operator["EQUAL_COLON"])); - } - else if (!eqnType) { - if (!dOneLit) dStr = dStr.substring(dStr.indexOf(operator["EQUAL_COLON"])+2); - if (sigNegs[retSigIndex(signal)] == "ON") dEqn += operator["NOT"]; - dEqn += sigName; - if ((type == operator["FT"]) || - (type == operator["FTD"])) dEqn += operator["_T"]; - else if ((type == operator["FD"]) || - (type == operator["FTD"])|| - (type == operator["LD"])) dEqn += operator["_D"]; - dEqn += " "; - if ((type != operator["Q"]) && (type != operator["LD"])) - dEqn += operator["EQUAL_COLON"]; - else dEqn += operator["EQUAL"]; - dEqn += dStr; - if (dOneLit) dEqn += operator["ENDLN"]; - } - - cStr = retClk(signal); - if (eqnType && !isOneLiteral(cStr)){ - cEqn = cStr; - if (cEqn.indexOf(operator["ENDLN"]) == -1) - cEqn += operator["ENDLN"]; - cStr = updateName(sigName, operator["_C"]); - } - else if (!eqnType && cStr) { - cEqn += cStr; - cStr = tabStr + sigName; - if (type == operator["LD"]) cStr += operator["_LH"]; - else cStr += operator["_C"]; - if (cEqn.indexOf(operator["ENDLN"]) == -1) - cEqn += operator["ENDLN"]; - if (gblclk[signal]) cEqn += tabStr + operator["COMMENT"] + " " + operator["GCK_COM"]; - } - - clrStr = retRst(signal); - if (eqnType && !isOneLiteral(clrStr)){ - clrEqn = clrStr; - if (cEqn.indexOf(operator["ENDLN"]) == -1) - clrEqn += operator["ENDLN"]; - clrStr = updateName(sigName, operator["_CLR"]); - } - else if (!eqnType && clrStr) { - clrEqn += clrStr; - clrStr = tabStr + sigName + operator["_CLR"]; - if (clrEqn.indexOf(operator["ENDLN"]) == -1) - clrEqn += operator["ENDLN"]; - if (gblrst[signal]) clrEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"]; - } - - preStr = retSet(signal); - if (eqnType && !isOneLiteral(preStr)){ - preEqn = preStr; - if (cEqn.indexOf(operator["ENDLN"]) == -1) - preEqn += operator["ENDLN"]; - preStr = updateName(sigName, operator["_PRE"]); - } - else if (!eqnType && preStr) { - preEqn += preStr; - preStr = tabStr + sigName + operator["_PRE"]; - if (preEqn.indexOf(operator["ENDLN"]) == -1) - preEqn += operator["ENDLN"]; - if (gblset[signal]) preEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"]; - } - - if (!is9500()) { - ceStr = retCE(signal); - if (eqnType && !isOneLiteral(ceStr)){ - ceEqn = ceStr; - if (cEqn.indexOf(operator["ENDLN"]) == -1) - ceEqn += operator["ENDLN"]; - ceStr = updateName(sigName, operator["_CE"]); - } - else if (!eqnType && ceStr) { - ceEqn += ceStr; - ceStr = tabStr + sigName + operator["_CE"]; - if (ceEqn.indexOf(operator["ENDLN"]) == -1) - ceEqn += operator["ENDLN"]; - } - } - - if (eqnType && trst[signal]) oeEqn = retTrst(signal) - else if (!eqnType && (trst[signal] || gbltrst[signal])) oeEqn = retTrst(signal); - - - var newline = false; - if (type == "") { - str += operator["ASSIGN"] + qStr + " " + operator["EQUAL"]; - if (dOneLit) str += dStr; - else str += dEqn.substring(dEqn.indexOf(operator["EQUAL"])+2); - if (oeEqn != "") { - var oeStr = updateName(sigName, operator["_OE"]); - if (eqnType == 1) { - str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr + - operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] + - operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"]; - } - else if (eqnType == 2) { - str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] + - oeStr + operator["OE_WHEN"] + qStr + - operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"]; - } - str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn; - } - } - else { - if (eqnType == 1) { - str += type + "_" + removePar(retSigName(signal)) + - ": " + type + " " + operator["START_EQN"] + - qStr + ", " + dStr + ", " + cStr + ", " + - clrStr + ", " + preStr; - if (!is9500() && (type != operator["LD"])) str += ", " + ceStr; - str += operator["END_EQN"] + operator["ENDLN"]; - newline = true; - } - else if (eqnType == 2) { - str += type + " " + - type + "_" + removePar(retSigName(signal)) + - operator["START_EQN"] + - qStr + ", " + dStr + ", " + cStr + ", " + - clrStr + ", " + preStr; - if (!is9500() && (type != operator["LD"])) str += ", " + ceStr; - str += operator["END_EQN"] + operator["ENDLN"]; - newline = true; - } - - if (dEqn != "") { - if (newline) str += nlStr; - if (inregStr) str += inregStr; - str += operator["ASSIGN"] + dEqn; - } - - if (cEqn != "") { - if (newline || !eqnType) str += nlStr; - str += operator["ASSIGN"] + cStr + " " + operator["EQUAL"] + " " + cEqn; - } - - if (clrEqn != "") { - if (newline || !eqnType) str += nlStr; - str += operator["ASSIGN"] + clrStr + " " + operator["EQUAL"] + " " + clrEqn; - } - - - if (preEqn != "") { - if (newline || !eqnType) str += nlStr; - str += operator["ASSIGN"] + preStr + " " + operator["EQUAL"] + " " + preEqn; - } - - if (ceEqn != "") { - if (newline || !eqnType) str += nlStr; - str += operator["ASSIGN"] + ceStr + " " + operator["EQUAL"] + " " + ceEqn; - } - - if (oeEqn != "") { - if (eqnType == 1) { - var oeStr = updateName(sigName, operator["_OE"]); - str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr + - operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] + - operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"]; - str += nlStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn; - } - else if (eqnType == 2) { - var oeStr = updateName(sigName, operator["_OE"]); - str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] + oeStr + operator["OE_WHEN"] + qStr + - operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"]; - str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn; - } - else { - var oeStr = sigName + operator["_OE"]; - if (gbltrst[signal]) - oeEqn += tabStr + operator["COMMENT"] + " " + operator["GTS_COM"]; - str += nlStr + tabStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn; - } - } - } - - return str; -} - -function retFamily() { - var family = "xc9500"; - if (device.indexOf("XC2C") != -1) { - if (device.indexOf("S") != -1) family = "cr2s"; - else family = "xbr"; - } - else if (device.indexOf("XCR3") != -1) family = "xpla3"; - else { - if (device.indexOf("XL") != -1) family = "xc9500xl"; - if (device.indexOf("XV") != -1) family = "xc9500xv"; - } - - return family; -} - -function retDesign() { return design; } - -function getPterm(pt, type) { - if (type) return type + " = " + retPterm(pt); - return "PT" + pt.substring(pt.indexOf('_')+1,pt.length) + " = " + retPterm(pt); -} - -function getPRLDName(prld) { - if (eqnType != 0) return prld; - else if (prld == "VCC") return "S"; - return "R"; -} - -function retFbnand(signal) { - var str = operator["COMMENT"] + spcStr + "Foldback NAND"; - str += nlStr + retSigName(signal) + spcStr + operator["EQUAL"] + spcStr; - for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; - str += retPterm(fbnand[signal][i]); - } - - return str; -} - -function getEqn(signal) { return retEqn(signal); } - -function retUimPterm(pt) { - var str = ""; - if (!uimPterms[pt]) return pt; - for (p=0; p0) str += spcStr + operator["AND"] + spcStr; - var sig = uimPterms[pt][p]; - if (sig.indexOf("/") != -1) sig = sig.substring(1, sig.length); - - str += retSigName(sig); - } - return str; -} - -function retUimEqn(signal) { - var str = operator["COMMENT"] + spcStr + "FC Node" + nlStr; - var neg = 0; - if (uimSigNegs[s] == "ON") str += operator["NOT"]; - str += retSigName(signal) + spcStr + operator["EQUAL"]; - str += retUimPterm(signal) + ";"; - - return str; -} - -function retLegend(url) { - var str = ""; - if (!eqnType && !isXC95()) { - str = "Legend: " + "<" + "signame" + ">" + ".COMB = combinational node mapped to "; - str += "the same physical macrocell as the FastInput \"signal\" (not logically related)"; - } - else if (eqnType) { - str = "Register Legend:"; - if (is9500()) { - str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE);"; - str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE);"; - str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);"; - } - else if (retFamily() == "xbr") { - str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);"; - str += nlTabStr + "FDDCPE (Q,D,C,CLR,PRE,CE);"; - str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);"; - str += nlTabStr + "FTDCPE (Q,D,C,CLR,PRE,CE);"; - str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);"; - } - else { - str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);"; - str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);"; - str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);"; - } - } - return str; -} - diff --git a/address_decoder_html/fit/equations.gif b/address_decoder_html/fit/equations.gif deleted file mode 100644 index d81602d..0000000 Binary files a/address_decoder_html/fit/equations.gif and /dev/null differ diff --git a/address_decoder_html/fit/equations.htm b/address_decoder_html/fit/equations.htm deleted file mode 100644 index 39141d2..0000000 --- a/address_decoder_html/fit/equations.htm +++ /dev/null @@ -1,13 +0,0 @@ - - - - - - - diff --git a/address_decoder_html/fit/equationsdoc.htm b/address_decoder_html/fit/equationsdoc.htm deleted file mode 100644 index e335b77..0000000 --- a/address_decoder_html/fit/equationsdoc.htm +++ /dev/null @@ -1,53 +0,0 @@ - - - - - - - - - - -Equations - - - - - - - - - - - - - - - - - - - - - - -

Equations

- -

The Equations - page provides a list of equations organized by signal name.  You - can use the pulldown menu in the left-hand frame of the page to select - ABEL, VHDL, or Verilog as your language of display.

- -

- - - - diff --git a/address_decoder_html/fit/errors.js b/address_decoder_html/fit/errors.js deleted file mode 100644 index 9df6118..0000000 --- a/address_decoder_html/fit/errors.js +++ /dev/null @@ -1,41 +0,0 @@ -var infoList = new Array(); -var warnList = new Array(); -var errorList = new Array(); - -function updateError(type) { - with (document.options) { - switch (type) { - case 0: - if (info.checked) parent.leftnav.document.options.info.value = 1; - else parent.leftnav.document.options.info.value = 0; - break; - - case 1: - if (warn.checked) parent.leftnav.document.options.warn.value = 1; - else parent.leftnav.document.options.warn.value = 0; - break; - - case 2: - if (error.checked) parent.leftnav.document.options.error.value = 1; - else parent.leftnav.document.options.error.value = 0; - break; - } - } - - parent.leftnav.showError(); -} - -function init() { - if (!document.options) return; - with (document.options) { - if (parent.leftnav.document.options.info.value == 1) info.checked = 1; - else info.checked = 0; - if (parent.leftnav.document.options.warn.value == 1) warn.checked = 1; - else warn.checked = 0; - if (parent.leftnav.document.options.error.value == 1) error.checked = 1; - else error.checked = 0; - - } -} - -function showError(url) { parent.leftnav.showErrorLink(url); } diff --git a/address_decoder_html/fit/errors1.gif b/address_decoder_html/fit/errors1.gif deleted file mode 100644 index 7908568..0000000 Binary files a/address_decoder_html/fit/errors1.gif and /dev/null differ diff --git a/address_decoder_html/fit/errors2.gif b/address_decoder_html/fit/errors2.gif deleted file mode 100644 index 6a3df4c..0000000 Binary files a/address_decoder_html/fit/errors2.gif and /dev/null differ diff --git a/address_decoder_html/fit/errorsdoc.htm b/address_decoder_html/fit/errorsdoc.htm deleted file mode 100644 index 460449a..0000000 --- a/address_decoder_html/fit/errorsdoc.htm +++ /dev/null @@ -1,91 +0,0 @@ - - - - - - - - - - -Errors - - - - - - - - - - - - - - - - - - - - - - - - -

Errors/Warnings

- -

The Errors/Warnings - section of the report lists all of the error, warning, and information - messages generated by the fitter. By default, this section will display - the number of each kind of message you have and the full text of the messages, - but checkboxes at the top of the screen allow you to filter message details - as you choose.

- -

Checking all - the boxes will give you a display like this:

- -

- -

Deselecting - the Warning box in this particular example would result in this less detailed - display:

- -

- - - - diff --git a/address_decoder_html/fit/fb.gif b/address_decoder_html/fit/fb.gif deleted file mode 100644 index 9783d6a..0000000 Binary files a/address_decoder_html/fit/fb.gif and /dev/null differ diff --git a/address_decoder_html/fit/fb1.gif b/address_decoder_html/fit/fb1.gif deleted file mode 100644 index 5d8b734..0000000 Binary files a/address_decoder_html/fit/fb1.gif and /dev/null differ diff --git a/address_decoder_html/fit/fbs.js b/address_decoder_html/fit/fbs.js deleted file mode 100644 index 8e97ea6..0000000 --- a/address_decoder_html/fit/fbs.js +++ /dev/null @@ -1,9 +0,0 @@ -function showFBApplet(fb) { parent.leftnav.showAppletFB(fb); } -function showFB(fb) { parent.leftnav.showFB(fb); } -function showMC(mc) { parent.leftnav.showAppletMC(mc); } -function showPT(pterm, type) { parent.leftnav.showPterm(pterm, type); } -function showPin(pin) { parent.leftnav.showAppletPin(pin); } -function showEqn(sig) { parent.leftnav.showEqn(sig); } -function showFBDetail(fb) { parent.leftnav.showFB(fb); } -function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); } -function showTop() { parent.leftnav.showTop(); } diff --git a/address_decoder_html/fit/fbs_FBdoc.htm b/address_decoder_html/fit/fbs_FBdoc.htm deleted file mode 100644 index 5d529aa..0000000 --- a/address_decoder_html/fit/fbs_FBdoc.htm +++ /dev/null @@ -1,307 +0,0 @@ - - - - - - - - - - -Function Block Specifics - - - - - - - - - - - - - - - - - - - - - - - - -

Function Block Specifics

- -

To access specific - details for a particular function block, click on that function block - in either the Mapped Logic, Mapped - Inputs, or Function - Blocks sections of the fitter report.  The - function block details page displays a table of details about the particular - function block you selected, a view button you can click to show a graphical - display of the function block, and a pulldown menu you can use to select - other function blocks to see.

- -

The Table

- -

The View

- -

- -

The Table

- -The table - at the top of the function block details page provides the following information - about the function block: - -
    - -
  • The - signal name
    • -
- -

Note: Clicking on - a signal name will open a new window with the equations for that signal. -

- -
    - -
  • The - total product terms used
    • - -
  •  A - list of product terms
    • -
- -

Note: Clicking on - a  product - term will open a new window with the equations for that term.

- -
    - -
  • The - macrocell number in which the function block is located
    • -
- -

Note: Clicking on the underscored macrocell - number will provide a graphical display of the macrocell that looks like - this:

- -

.

- -
    - -
  • The - power mode
    • - -
  • The - pin number
    • -
- -
    - -

  • Note: - Clicking on the underscored pin number will provide the pin layout diagram - for the highlighted pin.  Rolling - your mouse over the colored pin will pop up a tooltip with the signal - name assigned to the pin, the I/O standard,  the - I/O style, the slew rate, and/or any constraints assigned to the pin:

    • -
- -

- -
    - -
  • The - pin type
    • - -
  • The - pin use
    • -
- -

Note: Moving your - mouse cursor over an "I" in the Pin Use column will display - that input signal as a tooltip.

- -Below the - resource table you will find a list of signals used by logic in the function - block you are viewing.  The - list displays output signals as links.  Clicking - on an output signal link will open a new window showing the equations - for that signal. - -
  - - -

Note:  There - is also a button below the table.  Click - this button to open a new window describing all of the acronyms used in - the function block table.  You - can select either brief descriptions or more detailed descriptions by - clicking the "Verbose" button at the top of the window. -

- -

The View

- -

When you click - on the button above the table, a new window will open with - a graphical display of the function block you are examining.  The - pins are all color-coded: input pins are green, output pins are blue, - and clocks are magenta:

- -

- -

Right-click - anywhere within the window to pull up a menu that allows you to zoom in - or out for easier viewing.  

- -

This menu also - allows you choose to see all of the input connections, all of the output - connections, or both at once.  Like - the pins, the signals are color-coded: inputs are red, outputs are yellow, - and macrocell connections are aqua:

- -

- -

To examine - the signals of single pins, simply click the pin whose signals you wish - to see.  To - examine multiple pins without having to see everything at once, hold down - the control key while you click the pins you want to view.

- -

To view the - signals for individual macrocells:

- -
    - -

  • Click - the inside edge of the macrocell to display its macrocell connections - and inputs.

    • - -

  • Click - the outer edge to display its output signals

    • - -

  • Click - in the center to display everything

    • - -

  • Double - click in the center to open a new window with a detailed macrocell diagram

    • -
- -

 

- - - - diff --git a/address_decoder_html/fit/fbsdoc.htm b/address_decoder_html/fit/fbsdoc.htm deleted file mode 100644 index 04a25ff..0000000 --- a/address_decoder_html/fit/fbsdoc.htm +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - - - - - -Function Blocks - - - - - - - - - - - - - - - - - - - - - - - - -

Function Blocks

- -The Function - Blocks page provides a summary of all function blocks' resources. Clicking - on one of the function blocks in the summary table will display the specific details for that function block.   - -
  - - -
The summary table - contains the following:   - -
    - -
  • The - function block
    • - -
  • The - number of macrocell used
    • - -
  • The - number of function block inputs used
    • - -
  • The - number of product terms used
    • - -
  • The - pins used
    • - -
  • The - local control terms used
    • - -
  • The - number of foldback NANDs used (CoolRunner only)
    • -
- - - - diff --git a/address_decoder_html/fit/fbview.jpg b/address_decoder_html/fit/fbview.jpg deleted file mode 100644 index 7f43c68..0000000 Binary files a/address_decoder_html/fit/fbview.jpg and /dev/null differ diff --git a/address_decoder_html/fit/functionblock.gif b/address_decoder_html/fit/functionblock.gif deleted file mode 100644 index 524cdd4..0000000 Binary files a/address_decoder_html/fit/functionblock.gif and /dev/null differ diff --git a/address_decoder_html/fit/genmsg.htm b/address_decoder_html/fit/genmsg.htm deleted file mode 100644 index 0146e6d..0000000 --- a/address_decoder_html/fit/genmsg.htm +++ /dev/null @@ -1,17 +0,0 @@ - - - - - genmsg - - -  -
  -
-
-This file is currently being generated. Please recheck the link after some -time for this report data.
-
- - - diff --git a/address_decoder_html/fit/header.gif b/address_decoder_html/fit/header.gif deleted file mode 100644 index 526171b..0000000 Binary files a/address_decoder_html/fit/header.gif and /dev/null differ diff --git a/address_decoder_html/fit/home.gif b/address_decoder_html/fit/home.gif deleted file mode 100644 index d441184..0000000 Binary files a/address_decoder_html/fit/home.gif and /dev/null differ diff --git a/address_decoder_html/fit/index.htm b/address_decoder_html/fit/index.htm deleted file mode 100644 index 831ba39..0000000 --- a/address_decoder_html/fit/index.htm +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - - - - - - diff --git a/address_decoder_html/fit/leftnav.js b/address_decoder_html/fit/leftnav.js deleted file mode 100644 index b06978e..0000000 --- a/address_decoder_html/fit/leftnav.js +++ /dev/null @@ -1,176 +0,0 @@ -var noAppletOnClicked = 1; -var appletMsg = ""; -var waitWin; -var oldIn = oldOut = oldGbl = oldIsp = oldVcc = oldGnd = oldProhibit = oldUnuse = oldNc = 1; -var oldInfo = oldWarn = oldError = 1; -var verbose = 0; -var dispPage, mapLogPage, mapInPage, unLogPage, unInPage; -var javaPermission = 0; -var abelEqn = vhdlEqn = verEqn = ""; - -function IsNS() { - return ((navigator.appName.indexOf("Netscape") >= 0) && - (parseFloat(navigator.appVersion) >= 4)) ? true : false; -} - -function openWait() { - waitWin = window.open("wait.htm", "wait", - "toolbar=no,location=no,"+ - "directories=no,status=no,menubar=no,scrollbars=no,"+ - "resizable=no,width=300,height=50" ); -} - -function closeWait() { if (waitWin) waitWin.close(); } - -function popHTML(name, str) { - document.options.htmlStr.value = str; - if (name.indexOf(":") > -1) - name = name.substring(0,name.indexOf(":")) + "_COLON_" + - name.substring(name.indexOf(":")+1,name.length); - if (name.indexOf(".") > -1) - name = name.substring(0,name.indexOf(".")) + "_DOT_" + - name.substring(name.indexOf(".")+1,name.length); - var win = window.open("result.htm", "win_"+name, - "toolbar=no,location=no,"+ - "directories=no,status=no,menubar=no,scrollbars=yes,"+ - "resizable=yes,width=300,height=200" ); - win.focus(); -} - -function setAppletPermission() { appletPermission = 1; } -function getAppletPermission() { return( appletPermission); } -function getAppletMsg() { return(appletMsg); } -function setAppletMsg(msg) { appletMsg = msg; } - - -function showHTML(page, html) { - - dispPage = html; - document.options.currPage.value = page; - parent.content.location.href = html; -} - -function showTop() { showHTML(document.options.currPage.value, dispPage); } - -function setVerbose(value) { verbose = value; } - -function showLegend(url, w, h) { - if (verbose == 1) { - url = url.substring(0,name.indexOf(".htm")) + "V.htm"; - } - var win = window.open(url, 'win', - 'toolbar=no,location=no,directories=no,status=no,menubar=no,scrollbars=yes,resizable=yes,width='+w+',height='+h); - win.focus(); -} - -function showSummary() { showHTML("summary", "summary.htm"); } -function showOptions() { showHTML("options", "options.htm"); } -function showFBSum() { showHTML("fbs", "fbs.htm"); } -function showFB(fb) { showHTML("fbs_FB", "fbs_"+fb+".htm"); } -function showPinOut() { showHTML("pins", "pins.htm"); } -function showError() { showHTML("errors", "errs.htm"); } - -function showEqnAll() { - openWait(); - parent.eqns.setOper(currEqnType); - if (currEqnType == defEqnType) showHTML("equations", "defeqns.htm"); - else if (currEqnType == 0) { - if (abelEqn == "") abelEqn = parent.eqns.getEqnList(); - document.options.htmlStr.value = abelEqn; - showHTML("equations", "equations.htm"); - } - else if (currEqnType == 1) { - if (vhdlEqn == "") vhdlEqn = parent.eqns.getEqnList(); - document.options.htmlStr.value = vhdlEqn; - showHTML("equations", "equations.htm"); - } - else { - if (verEqn == "") verEqn = parent.eqns.getEqnList(); - document.options.htmlStr.value = verEqn; - showHTML("equations", "equations.htm"); - } - closeWait(); -} - -function showEqn(sig) { - popHTML(sig, parent.eqns.getEqn(sig)); -} - -function showPterm(pterm, type) { - popHTML(pterm, parent.eqns.getPterm(pterm, type)); -} - -function showAscii() { showHTML("ascii", "ascii.htm"); } -function showTiming() { showHTML("time", "time.htm"); } - -function showHelp() { - var helpDoc = document.options.currPage.value + "doc.htm"; - popWin(helpDoc); -} - -function getMapParam(type) { - var paramStr = ""; - switch(type) { - case 1: paramStr += "10"; break; - case 2: paramStr += "01"; break; - case 3: paramStr += "11"; break; - case 4: paramStr += "02"; break; - case 5: paramStr += "12"; break; - default: paramStr += "00"; - } - - return paramStr; -} - -function showMappedLogics(type) { - showHTML("maplogic", "maplogic_" + getMapParam(type) + ".htm"); -} - -function showMappedInputs(type) { - showHTML("mapinput", "mapinput_" + getMapParam(type) + ".htm"); -} - -function showUnMappedLogics(type) { - showHTML("unmaplogic", "unmaplogic_" + getMapParam(type) + ".htm"); -} - -function showUnMappedInputs(type) { - showHTML("unmapinput", "unmapinput_" + getMapParam(type) + ".htm"); -} - -function doEqnFormat() { - var type = document.options.eqnType.options[document.options.eqnType.options.selectedIndex].value; - currEqnType = type; - parent.eqns.setOper(currEqnType); - if (document.options.currPage.value == "equations") showEqnAll(); -} - -function showNoAppletAlert() { - window.alert("No Applet supported for this session!!!"); -} - -function showAppletMC(mc) { - if (parent.applets) parent.applets.showAppletGraphicMC(mc); - else showNoAppletAlert(); -} - -function showAppletFB(fb) { - if (parent.applets) parent.applets.showAppletGraphicFB(fb); - else showNoAppletAlert(); -} - -function showAppletPin(pin) { - if (parent.applets) parent.applets.showAppletGraphicPin(pin); - else showNoAppletAlert(); -} - -function printAppletPkg() { - if (parent.applets) parent.applets.printAppletPkg(); - else showNoAppletAlert(); -} - -function popWin(url) { - var win = window.open(url, 'win', - 'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600'); - win.focus(); -} diff --git a/address_decoder_html/fit/legend.gif b/address_decoder_html/fit/legend.gif deleted file mode 100644 index 0aad0eb..0000000 Binary files a/address_decoder_html/fit/legend.gif and /dev/null differ diff --git a/address_decoder_html/fit/legend.jpg b/address_decoder_html/fit/legend.jpg deleted file mode 100644 index 1d04af0..0000000 Binary files a/address_decoder_html/fit/legend.jpg and /dev/null differ diff --git a/address_decoder_html/fit/logic_legXC95.htm b/address_decoder_html/fit/logic_legXC95.htm deleted file mode 100644 index e253a0b..0000000 --- a/address_decoder_html/fit/logic_legXC95.htm +++ /dev/null @@ -1,2 +0,0 @@ -
-
diff --git a/address_decoder_html/fit/logic_legXbr.htm b/address_decoder_html/fit/logic_legXbr.htm deleted file mode 100644 index 9883d2d..0000000 --- a/address_decoder_html/fit/logic_legXbr.htm +++ /dev/null @@ -1,15 +0,0 @@ -
-I/O Style - OD    - OpenDrain
-          - PU    - Pullup
-          - KPR   - Keeper
-          - S     - SchmittTrigger
-          - DG    - DataGate
-Reg Use   - LATCH - Transparent latch
-          - DFF   - D-flip-flop
-          - DEFF  - D-flip-flop with clock enable
-          - TFF   - T-flip-flop
-          - TDFF  - Dual-edge-triggered T-flip-flop
-          - DDFF  - Dual-edge-triggered flip-flop
-          - DDEFF - Dual-edge-triggered flip-flop with clock enable
-          /S (after any above flop/latch type) indicates initial state is Set
-
diff --git a/address_decoder_html/fit/logic_legXpla3.htm b/address_decoder_html/fit/logic_legXpla3.htm deleted file mode 100644 index c0e6f4a..0000000 --- a/address_decoder_html/fit/logic_legXpla3.htm +++ /dev/null @@ -1,3 +0,0 @@ -
-Legend: PU  - Pull Up
-
diff --git a/address_decoder_html/fit/macrocell.gif b/address_decoder_html/fit/macrocell.gif deleted file mode 100644 index ec9e68e..0000000 Binary files a/address_decoder_html/fit/macrocell.gif and /dev/null differ diff --git a/address_decoder_html/fit/mapinputdoc.htm b/address_decoder_html/fit/mapinputdoc.htm deleted file mode 100644 index 9f7a3c9..0000000 --- a/address_decoder_html/fit/mapinputdoc.htm +++ /dev/null @@ -1,158 +0,0 @@ - - - - - - - - - - -Mapped Inputs - - - - - - - - - - - - - - - - - - - - - - - - -

Mapped Inputs

- -Like the - Mapped Logic section, the Mapped Inputs - section of the report displays a table detailing the resources allocated - by the fitter to mapped inputs.  Again, - the table can be sorted by Signal Name, Function Block, or Pin Number - by clicking on the appropriate table headings.   - -
  - - -
The inputs table - contains the following: - -
    - -
  • The - input signal name
    • - -
  • The - function block number
    • -
- -

Note: - Clicking on the function block will provide a detailed table of all the - block's resources and a graphical display of the function block diagram - (see Function Block Specifics for more details).

- -
    - -
  • The - macrocell number
    • -
- -
    - -

  • Note: - Clicking on the underscored macrocell number will provide a graphical - display of the macrocell that looks like this:

    • - -
  • .The pin number
    • -
- -

Note: Clicking on - the underscored pin number will provide the pin layout diagram for the - highlighted pin.  Rolling - your mouse over the colored pin will pop up a tooltip with the signal - name assigned to the pin, the I/O standard,  the - I/O style, the slew rate, and/or any constraints assigned to the pin:

- -

- -

 

- -
    - -
  • The - pin type
    • - -
  • The - pin use
    • - -
  • The - I/O standard
    • - -
  • The - I/O style
    • -
- - - - diff --git a/address_decoder_html/fit/maplogic.js b/address_decoder_html/fit/maplogic.js deleted file mode 100644 index e40c8f2..0000000 --- a/address_decoder_html/fit/maplogic.js +++ /dev/null @@ -1,23 +0,0 @@ -function showFB(fb) { parent.leftnav.showFB(fb); } -function showMC(mc) { parent.leftnav.showAppletMC(mc); } -function showEqn(sig) { parent.leftnav.showEqn(sig); } -function showPin(pin) { parent.leftnav.showAppletPin(pin); } -function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); } -function showTop() { parent.leftnav.showTop(); } - -function Sort(x) { - switch (x) { - case 0: parent.leftnav.showMappedLogics(0); break; - case 1: parent.leftnav.showMappedLogics(2); break; - case 2: parent.leftnav.showMappedLogics(4); break; - case 10: parent.leftnav.showMappedInputs(0); break; - case 11: parent.leftnav.showMappedInputs(2); break; - case 12: parent.leftnav.showMappedInputs(4); break; - case 20: parent.leftnav.showUnMappedLogics(0); break; - case 21: parent.leftnav.showUnMappedLogics(2); break; - case 22: parent.leftnav.showUnMappedLogics(4); break; - case 30: parent.leftnav.showUnMappedInputs(0); break; - case 31: parent.leftnav.showUnMappedInputs(2); break; - case 32: parent.leftnav.showUnMappedInputs(4); break; - } -} diff --git a/address_decoder_html/fit/maplogicdoc.htm b/address_decoder_html/fit/maplogicdoc.htm deleted file mode 100644 index efed6ca..0000000 --- a/address_decoder_html/fit/maplogicdoc.htm +++ /dev/null @@ -1,185 +0,0 @@ - - - - - - - - - - -Mapped Logic - - - - - - - - - - - - - - - - - - - - - - - - -

Mapped Logic

- -The Mapped - Logic section provides a table listing resources allocated by the fitter - to mapped logic. The page will appear in your browser sorted by Signal - Name, but you can choose to sort it by Signal Name, Function Block, and - Pin Number by clicking on the appropriate table headers. - -
  - - -
The Mapped Logic - table contains the following: - -
    - -
  • The - output signal name
    • -
- -

Note: Clicking on - the signal name will open a new window with the equations for that signal. -

- -
    - -
  • The - total number of product terms
    • - -
  • The - number of signals used
    • - -
  • The - function block number
    • -
- -

Note: - Clicking on the function block will provide a detailed table of all the - block's resources and a graphical display of the function block diagram - (see Function Block Specifics for more details). -

- -
    - -
  • The - macrocell number
    • -
- -

Note: - Clicking on the underscored macrocell number will provide a graphical - display of the macrocell that looks like this:

- -

.

- -
    - -
  • The - slew rate
    • - -
  • The - pin number
    • -
- -

Note: - Clicking on the underscored pin number will provide the pin layout diagram - for the highlighted pin.  Rolling - your mouse over the colored pin will pop up a tooltip with the signal - name assigned to the pin, the I/O standard,  the - I/O style, the slew rate, and/or any constraints assigned to the pin:

- -

- -
    - -
  • The - pin type
    • - -
  • The - pin use
    • - -
  • The - input register use
    • - -
  • The - I/O standard
    • - -
  • The - I/O style
    • -
- - - - diff --git a/address_decoder_html/fit/newappletref.htm b/address_decoder_html/fit/newappletref.htm deleted file mode 100644 index 186e949..0000000 --- a/address_decoder_html/fit/newappletref.htm +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - - - - - - diff --git a/address_decoder_html/fit/next.jpg b/address_decoder_html/fit/next.jpg deleted file mode 100644 index b8bbb99..0000000 Binary files a/address_decoder_html/fit/next.jpg and /dev/null differ diff --git a/address_decoder_html/fit/ns4plugin.js b/address_decoder_html/fit/ns4plugin.js deleted file mode 100644 index 0292ee1..0000000 --- a/address_decoder_html/fit/ns4plugin.js +++ /dev/null @@ -1,55 +0,0 @@ - -function checkJre(){ - -var agt=navigator.userAgent.toLowerCase(); -var is_major = parseInt(navigator.appVersion); - - -var is_nav = ((agt.indexOf('mozilla')!=-1) && (agt.indexOf('spoofer')== -1) -&& (agt.indexOf('compatible') == -1) && (agt.indexOf('opera')== -1) -&& (agt.indexOf('webtv')==-1) && (agt.indexOf('hotjava')== -1)); -var is_nav4up = (is_nav && (is_major >= 4)); - -var pluginDetected = false; - -// we can check for plugin existence only when browser is 'is_ie5up' or 'is_nav4up' -if(is_nav4up) { - - // Refresh 'navigator.plugins' to get newly installed plugins. - // Use 'navigator.plugins.refresh(false)' to refresh plugins - // without refreshing open documents (browser windows) - if(navigator.plugins) { - navigator.plugins.refresh(false); - } - - // check for Java plugin in installed plugins - if(navigator.mimeTypes) { - // window.alert( navigator.mimeTypes.length); - for (i=0; i < navigator.mimeTypes.length; i++) { - // window.alert( navigator.mimeTypes[i].type); - if( (navigator.mimeTypes[ i].type != null) - &&(navigator.mimeTypes[ i].type.indexOf( - "application/x-java-applet;jpi-version=1.4") != -1) ) { - //window.alert("Found"); - pluginDetected = true; - break; - } - - } - } - -} - -if (pluginDetected) { - // show applet page - document.location.href="appletref.htm"; - -} else if (confirm("Java Plugin 1.4+ not found, Do you want to download it?\n" + - "if you choose not to install the plugin the reports graphical applets will not be available.")) { - document.location.href=XilinxD; -} else { - document.location.href="appletref.htm"; -} - -} - diff --git a/address_decoder_html/fit/optionsdoc.htm b/address_decoder_html/fit/optionsdoc.htm deleted file mode 100644 index f1ee543..0000000 --- a/address_decoder_html/fit/optionsdoc.htm +++ /dev/null @@ -1,760 +0,0 @@ - - - - - - - - - - -Compiler Options - - - - - - - - - - - - - - - - - - - - - - - - -

Compiler Options

- -

The Compiler - Options page provides all the fitter options settings for the device family - the fitter has selected.

- -

Fitter Options

- -

Basic Tab

- -

XPLA3 Advanced - Options

- -

CoolRunner-II - Advanced Options

- -

XC9500/XL/XV - Advanced Options

- -

Basic - Tab

- -

The CPLD devices - have the following fitter Implementation - Options available in - the Basic tab:

- -
    - -

  • Use - Multi-Level Logic Optimization

    • -
- -

This option simplifies the total number - of logic expressions in a design, and then collapses the logic in order - to meet user objectives such as density, speed and timing constraints. - This optimization targets CPLD architecture, making it possible to collapse - to the macrocell limits, reduce levels of logic, and minimize the total - number of p-terms.

- -

Multi-level Logic Optimization optimizes - all combinatorial logic arcs spanning from an input pad or register output - to an output pad or register input.

- -

Multi-level Logic Optimization operates - on combinatorial logic according to the following rules.

- -

If timing constraints are set, the program - optimizes for speed to meet timing constraints.

- -

If timing constraints are not set, the - program optimizes either for speed or density, depending on the user setting - for the Use Timing Optimization - option.

- -
    - -
      - -
        - -

      • If - Use Timing Optimization is turned - on, the combinatorial logic will be mapped for speed.

        • - -

      • If - Use Timing Optimization is turned - off, the combinatorial logic will be mapped for density. The goal of optimization - will then be to reduce the total number of p-terms.

        • -
      -
    -
- -

Logic - marked with the NOREDUCE property will not be extracted or optimized.

- -

By - default, this option is on.

- -
    - -

  • Use Timing Constraints -- This - option instructs the fitter use Timing Constraints when fitting the design. -  If this - box is not checked, the fitter will ignore timing constraints, if necessary.

    • - -

  • Enable WYSIWYG - Mode -- (CoolRunner only) The - goal of the WYSIWYG options is to have a netlist reflect the user's specifications, - as much as possible. All the nodes declared in the HDL design are preserved. - By default, this property is set to Off (Checkbox is not checked) When - this property is On (checkbox is checked), XST:

    • - -
      - -

    • Preserves - all the user internal signals (nodes)

      • - -

    • Creates - source_node constraints in NGC file for all these nodes.

      • - -

    • Skips - the design optimization (collapse, factorization). Only the Boolean equation - minimization is performed.

      • -
    - -

  • Optimization Style-- The Optimization - Method allows you to select from one of two basic optimization strategies: - Density or Speed. - Density focuses on solely - on density, and Speed focuses - solely on speed.

    • - -

  • Location Constraints -- The Try selection - will attempt to fit the design with the pin assignments specified in the - design source. If the design cannot be fit with these pin assignments, - the fitter will remove the location constraints and attempt to fit the - design with no location constraints. A warning message will tell the user - if the location constraints have been removed.

    • - -
      - -

    • The - Try selection will attempt - to fit the design with the pin assignments specified in the design source. - If the design cannot be fit with these pin assignments, the fitter will - ignore the pin assignments.

      • -
    - -

  • The - On selection will attempt to fit - the design with the pin assignments specified in the design source. If - the design cannot be fit with these pin assignments, the fitter will notify - the user that the device could not fit. It will not unlock the pins under - this option.

    • - -

  • The - Off selection will attempt to - fit the design and will ignore the pin assignments specified in the design - source. If the design can be fit with no pre-assigned pins, the fitter - will assign pins, which can be viewed in the fitter report (filename.fit). - The user should take these pin assignments and incorporate them back into - the design source file. The user will be notified whether the fitting - operation was successful.

    • - -

  • Output - Slew Rate -- Use this option - to control the default output slew rate. You can control the transition - time of device output pins by setting the slew rate to Slow or Fast. Limiting - the slew rate (Slow) reduces output switching surges in the device. The - default is Fast.

    • -
- -

Note: - Any explicit slew rate control properties in the design or constraints - file take precedence over this Output Slew Rate setting.

- -
    - -

  • FF Initial State -- Sets - the initial state for all Flip-Flops.  The - options are Low, High and FPGA.

    • - -

  • Collapsing - P-Term Limit -- This option - controls the degree to which the fitter flattens a design netlist. A logic - gate can collapse forward into a subsequent gate only if the number of - product terms in the resulting logic function does not exceed the p-term - limit. If the path delay of a logic function is not acceptable, increase - the p-term limit to allow the larger functions to be further flattened. - Choose a number from 3 to 48.

    • - -

  • Collapsing - Input Limit -- This is a - secondary option for controlling the degree to which the fitter flattens - a design netlist. A logic gate can collapse forward into a subsequent - gate only if the number of inputs in the resulting logic function does - not exceed the input limit. If the design fails to fit the target device - because flattening uses up too many of the function block inputs, decrease - the input limit to prevent flattening of certain high fan-in functions. -  

    • -
- -

XPLA Advanced - Options

- -

The - following options are available under XPLA Implementation - Options, Advanced tab.

- -
    - -

  • Enable Fast - Input Registers -- Enables the use - of the Fast Input path in XPLA3 devices.

    • - -

  • Enable Use - of Foldback NANDs -- When selected, - the software will use foldback NANDs. This increases the capability to - fit a design, sometimes at the expense of speed.

    • - -

  • Reserve JTAG Pins for ISP -- Checking - this box will instruct the fitter to reserve JTAG pins.

    • -
- -

CoolRunner-II - Advanced Options

- -

The following - options are found under the Advanced tab for CoolRunner-II devices.

- -
    - -

  • Use - Global Clock(s) -- Select this option - to allow the fitter to assign input pins used as clocks to dedicated global - clock (GCK) pins of the device. If this option is disabled, only pins - identified with the BUFG=CLK property in the design (or UCF file) will - be assigned to GCK device pins. By default, this option is on. -

    • - -

  • Use Global Output Enable(s) -- Select - this option to allow the fitter to assign input pins used as output enable - control to dedicated global OE (GTS) pins of the device. If this option - is disabled, only pins identified with the BUFG=OE property in the design - (or UCF file) will be assigned to GTS device pins. By default, this option - is on.

    • - -

  • Use Global Set/Reset -- Select this - option to allow the fitter to assign input pins used as register asynchronous - reset or preset control to the dedicated global set/reset (GSR) pin of - the device. If this option is disabled, only a pin identified with the - BUFG=SR property in the design (or UCF file) will be assigned to the GSR - device pin. By default, this option is on.

    • - -

  • Enable Fast Input Registers -- Enables - fast input registers.

    • - -

  • Ignore DATA_GATE Attributes -- Data - Gate is a power saving property that can be used in CoolRunner-II designs. -  This option - allows you to turn Data Gate off in case you want the fitter to ignore - data gate.

    • - -

  • Tristate Outputs Termination Node -- - The Tristate Output Termination Mode globally sets all tristate outputs - to the specified termination mode. By default, this field is set to Pullup.. -  The options - are Pullup, Keeper and Float.

    • - -

  • Create Programmable Ground Pins on Unused I/O - -- The Create Programmable GND Pins on Unused I/O property controls the - option to indicate that you want all unused I/O pads to be configured - as ground pins. This can reduce ground bounce. By default, this option - is set to ground.  The - options are Ground, Pullup, Keeper and Float.

    • - -
  • -

    Default - Output Voltage Standard -- set a default voltage standard for CoolRunner-II - device pins.

    - -

    IOSTANDARD - names supported by CoolRunner-II are:

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    -

    I/O Standard

    		 -

    VCCIO

    		 -

    Input VREF

    		 -

    Board Termination Voltage (VTT)

    -

    LVTTL

    		-

    3.3V

    		 -

    N/A

    		 -

    N/A

    -

    LVCMOS33

    		 -

    3.3V

    		 -

    N/A

    		 -

    N/A

    -

    LVCMOS25

    		 -

    2.5V

    		 -

    N/A

    		 -

    N/A

    -

    LVCMOS18

    		 -

    1.8V

    		 -

    N/A

    		 -

    N/A

    -

    LVCMOS15

    		 -

    1.5V

    		 -

    N/A

    		 -

    N/A

    -

    HSTL_I

    		 -

    1.5V

    		 -

    0.75V

    		 -

    0.75V

    -

    SSTL2_I

    		 -

    2.5V

    		 -

    1.25V

    		 -

    1.25V

    -

    SSTL3_I

    		 -

    3.3V

    		 -

    1.5V

    		 -

    1.5V

    - -

    The software - automatically groups outputs with similar IOSTANDARD settings into the - same bank when no location constraints are specified.

    -
    • -
- -

XC9500/XL/XV - Advanced Options

- -

The following - options are found under the Advanced tab for XC9500/XL/XV.  Note - that additional options for XC9500 only are also described below.

- -
    - -

  • Use - Global Clock(s) -- Select this option - to allow the fitter to assign input pins used as clocks to dedicated global - clock (GCK) pins of the device. If this option is disabled, only pins - identified with the BUFG=CLK property in the design (or UCF file) will - be assigned to GCK device pins. By default, this option is on. -

    • - -

  • Use Global Output Enable(s) -- Select - this option to allow the fitter to assign input pins used as output enable - control to dedicated global OE (GTS) pins of the device. If this option - is disabled, only pins identified with the BUFG=OE property in the design - (or UCF file) will be assigned to GTS device pins. By default, this option - is on.

    • - -

  • Use Global Set/Reset -- Select this - option to allow the fitter to assign input pins used as register asynchronous - reset or preset control to the dedicated global set/reset (GSR) pin of - the device. If this option is disabled, only a pin identified with the - BUFG=SR property in the design (or UCF file) will be assigned to the GSR - device pin. By default, this option is on.

    • - -

  • Create Programmable Ground Pins on Unused I/O - -- Select this option to indicate that you want all unused I/O pads to - be configured as ground pins. This can reduce ground bounce. By default, - this option is off.

    • - -

  • Macrocell Power Setting -- Use this - option to control device power consumption. Select Low or Standard to - set the default power mode for the macrocells used to implement the design. - Select Timing Driven to automatically reduce power on paths covered by - timing specifications that can meet speed requirements while operating - in low power. The default is Standard, which results in highest speed.

    • -
- -

Note: Any explicit power control (PWR_MODE) - properties in the design or constraints file take precedence over this - Macrocell Power Setting.

- -
    - -

  • Enable FASTConnect/UIM Optimization (XC9500 - only) -- Enables optimization of the FASTConnect/UIM for XC9500 - devices.

    • - -

  • Use - Local Feedback (XC9500 only)

    • -
- -

Select this option to enable the software - to use local macrocell feedback whenever possible. The local feedback - path, running from each macrocell output to an input of the same function - block, has shorter propagation delay than the global feedback path. The - fitter always tries to use local macrocell feedback (if possible) to satisfy - timing constraints. This option allows the fitter to use local feedback - to generally improve timing on remaining paths. Using local feedback can - speed up your design but could also make it difficult to maintain the - same timing after a design change. By default, this option is on.

- - - -
- - -

Note: - To force the fitter to use local feedback, manually map both - the source and load functions into the same function block using the property - LOC=FBnn, - then apply a timespec across the path. 

- - - -
- - -

Note: - The XC9536 device does not have local feedback.

- - - -
- - -
    - -

  • Use - Pin Feedback (XC9500 only)

    • -
- -

Select this option to enable the software - to use I/O pin feedback whenever possible. The pin feedback path has slightly - shorter propagation delay than the global feedback path. If this option - is enabled, the software uses the pin feedback path instead of the global - feedback path for macrocell signals that do not drive 3-state outputs - or slew-rate-limited outputs, and where the associated I/O pin is not - used as input-only. By default, this option is on.

- - - - diff --git a/address_decoder_html/fit/paths.js b/address_decoder_html/fit/paths.js deleted file mode 100644 index 22107b3..0000000 --- a/address_decoder_html/fit/paths.js +++ /dev/null @@ -1,37 +0,0 @@ -rootURL = "http://www.xilinx.com/"; -prodURL = "xlnx/xil_prodcat_product.jsp?title="; -cpldURL = "CPLD+Products"; -xbrURL = "coolrunner2_page"; -xpla3URL = "xpla3_page"; -xc9500URL = "xc9500_page"; -xc9500xlURL = "xc9500xl_page"; -xc9500xvURL = "xc9500xv_page"; -marketURL= "esp"; -supportURL = "http://www.support.xilinx.com/"; -educationURL = "support/education-home.htm"; -buyURL = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront"; -contactURL = "company/contact.htm"; -searchURL = "company/search.htm"; - -docURL = rootURL + "xlnx/xweb/xil_publications_display.jsp?" + - "iLanguageID=1" + - "&category=/Data+Sheets/CPLD+Device+Families/"; -doc95URL = docURL + "XC9500"; -doc95xlURL = docURL + "XC9500XL"; -doc95xvURL = docURL + "XC9500XV"; -docXpla3URL = docURL + "CoolRunner+XPLA3"; -docXbrURL = docURL + "CoolRunner-II"; -docCr2sURL = docURL + "CoolRunner-IIS"; - -var messages = new Array(); -messages["fastinreg"] = "Direct Input Register"; -messages["inreg"] = "Direct Input Register"; -messages["fbnand"] = "Foldback NAND"; -messages["fcnode"] = "FC node"; -messages["LATCH"] = "Transparent latch"; -messages["DFF"] = "D-flip-flop"; -messages["DEFF"] = "D-flip-flop with clock enable"; -messages["TFF"] = "T-flip-flop"; -messages["TDFF"] = "Dual-edge-triggered T-flip-flop"; -messages["DDFF"] = "Dual-edge-triggered flip-flop"; -messages["DDEFF"] = "Dual-edge-triggered flip-flop with clock enable"; diff --git a/address_decoder_html/fit/pin.gif b/address_decoder_html/fit/pin.gif deleted file mode 100644 index f110f3d..0000000 Binary files a/address_decoder_html/fit/pin.gif and /dev/null differ diff --git a/address_decoder_html/fit/pin_legXC95.htm b/address_decoder_html/fit/pin_legXC95.htm deleted file mode 100644 index db88bcb..0000000 --- a/address_decoder_html/fit/pin_legXC95.htm +++ /dev/null @@ -1,13 +0,0 @@ -
-Legend :  NC  = Not Connected, unbonded pin
-         PGND = Unused I/O configured as additional Ground pin
-         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
-         VCC  = Dedicated Power Pin
-         GND  = Dedicated Ground Pin
-         TDI  = Test Data In, JTAG pin
-         TDO  = Test Data Out, JTAG pin
-         TCK  = Test Clock, JTAG pin
-         TMS  = Test Mode Select, JTAG pin
-         PE   = Port Enable pin
-  PROHIBITED  = User reserved pin
-
diff --git a/address_decoder_html/fit/pin_legXbr.htm b/address_decoder_html/fit/pin_legXbr.htm deleted file mode 100644 index c70585b..0000000 --- a/address_decoder_html/fit/pin_legXbr.htm +++ /dev/null @@ -1,20 +0,0 @@ -
-Legend :  NC  = Not Connected, unbonded pin
-        PGND  = Unused I/O configured as additional Ground pin
-         KPR  = Unused I/O with weak keeper (leave unconnected)
-         WPU  = Unused I/O with weak pull up (leave unconnected)
-         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
-         VCC  = Dedicated Power Pin
-      VCCAUX  = Power supply for JTAG pins
-   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
-   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
-   VCCIO-1.8  = I/O supply voltage for LVCMOS18
-   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
-        VREF  = Reference voltage for indicated input standard
-         GND  = Dedicated Ground Pin
-         TDI  = Test Data In, JTAG pin
-         TDO  = Test Data Out, JTAG pin
-         TCK  = Test Clock, JTAG pin
-         TMS  = Test Mode Select, JTAG pin
-  PROHIBITED  = User reserved pin
-
diff --git a/address_decoder_html/fit/pin_legXpla3.htm b/address_decoder_html/fit/pin_legXpla3.htm deleted file mode 100644 index 8dad55d..0000000 --- a/address_decoder_html/fit/pin_legXpla3.htm +++ /dev/null @@ -1,13 +0,0 @@ -
-Legend :  NC  = Not Connected, unbonded pin
-          PE  = Port Enable pin
-         WPU  = Unused with Internal Weak Pull Up
-         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
-         VCC  = Dedicated Power Pin
-         GND  = Dedicated Ground Pin
-         TDI  = Test Data In, JTAG pin
-         TDO  = Test Data Out, JTAG pin
-         TCK  = Test Clock, JTAG pin
-         TMS  = Test Mode Select, JTAG pin
-  PROHIBITED  = User reserved pin
-
diff --git a/address_decoder_html/fit/pindiagram.gif b/address_decoder_html/fit/pindiagram.gif deleted file mode 100644 index 504bb2b..0000000 Binary files a/address_decoder_html/fit/pindiagram.gif and /dev/null differ diff --git a/address_decoder_html/fit/pins.js b/address_decoder_html/fit/pins.js deleted file mode 100644 index 591e563..0000000 --- a/address_decoder_html/fit/pins.js +++ /dev/null @@ -1,62 +0,0 @@ -var specSig = new Array(); -var pins = new Array(); -var pinsAssign = new Array(); -var prohibit = new Array(); -var unusedStr = "WPU"; -var gndStr = "GND"; -var vccStr = "VCC"; -var tdiStr = "TDI"; -var tdoStr = "TDO"; -var tmsStr = "TMS"; -var tckStr = "TCK"; - -function showPin(pin) { parent.leftnav.showAppletPin(pin); } - -function printPage() { window.print(); parent.leftnav.printAppletPkg(); } - -function showEqn(signal) { parent.leftnav.showEqn(signal); } - -function updatePin(type) { - with (document.options) { - switch (type) { - case 0: - if (inp.checked) parent.leftnav.document.options.inOn.value = 1; - else parent.leftnav.document.options.inOn.value = 0; - break; - - case 1: - if (out.checked) parent.leftnav.document.options.outOn.value = 1; - else parent.leftnav.document.options.outOn.value = 0; - break; - - case 2: - if (glb.checked) parent.leftnav.document.options.glbOn.value = 1; - else parent.leftnav.document.options.glbOn.value = 0; - break; - - case 3: - if (isp.checked) parent.leftnav.document.options.ispOn.value = 1; - else parent.leftnav.document.options.ispOn.value = 0; - break; - - case 4: - if (vcc.checked) parent.leftnav.document.options.vccOn.value = 1; - else parent.leftnav.document.options.vccOn.value = 0; - break; - - case 5: - if (gnd.checked) parent.leftnav.document.options.gndOn.value = 1; - else parent.leftnav.document.options.gndOn.value = 0; - break; - - case 6: - if (unuse.checked) parent.leftnav.document.options.unuseOn.value = 1; - else parent.leftnav.document.options.unuseOn.value = 0; - break; - } - } - - parent.leftnav.showPinOut(); -} - -function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); } diff --git a/address_decoder_html/fit/pinsdoc.htm b/address_decoder_html/fit/pinsdoc.htm deleted file mode 100644 index 9da2708..0000000 --- a/address_decoder_html/fit/pinsdoc.htm +++ /dev/null @@ -1,265 +0,0 @@ - - - - - - - - - - -Pin List - - - - - - - - - - - - - - - - - - - - - - - - -

Pin List

- -

The Pin List - page lists each pin of your design with its pin type and associated signal. -  Check boxes - at the top of the table allow you to select and deselect which pin types - you want displayed in the table (the default view will display all of - them).

- -

Note: -  There is - a button below the table.  Click - this button to open a new window describing all of the acronyms used in - the function block table.  You - can select either brief descriptions or more detailed descriptions by - clicking the "Verbose" button at the top of the window.

- -Clicking - on the underscored pin numbers in the first column of the table will open - a new window displaying the pin layout diagram for the selected pin.  Rolling - your mouse over the colored pin will pop up a tooltip with the signal - name assigned to the pin, the I/O standard,  the - I/O style, the slew rate, and/or any constraints assigned to the pin: - - -

- -

Clicking any underscored signal in the - third column of the table will open a new window displaying the equations - for that particular signal.

- -

Clicking on the button - at the top of the screen will open a new window with a graphical, top - view of all of the pins:  

- -

- -

They are color-coded as follows:

- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-

Color

 -

Signal

-

Green

 -

Input

-

Aqua

 -

Bidirectional

-

Blue

 -

Output

-

Magenta

 -

Clock

-

Red

 -

VCC

-

Black

 -

GND

-

Yellow

 -

TDO

-

Gray

 -

TDI

-

White

 -

Unused Pin

-

Black Outline

 -

No available - Pad

- -

As with the single pin display, rolling - your mouse over any colored pin will pop up a tooltip with the signal - name assigned to the pin, the I/O standard,  the - I/O style, the slew rate, and/or any constraints assigned to the pin.

- - - - diff --git a/address_decoder_html/fit/pinview.jpg b/address_decoder_html/fit/pinview.jpg deleted file mode 100644 index c3a27ca..0000000 Binary files a/address_decoder_html/fit/pinview.jpg and /dev/null differ diff --git a/address_decoder_html/fit/plugin.js b/address_decoder_html/fit/plugin.js deleted file mode 100644 index cc34368..0000000 --- a/address_decoder_html/fit/plugin.js +++ /dev/null @@ -1,96 +0,0 @@ - -function checkJre(){ - -var agt=navigator.userAgent.toLowerCase(); -var is_major = parseInt(navigator.appVersion); - - -var is_nav = ((agt.indexOf('mozilla')!=-1) && (agt.indexOf('spoofer')== -1) -&& (agt.indexOf('compatible') == -1) && (agt.indexOf('opera')== -1) -&& (agt.indexOf('webtv')==-1) && (agt.indexOf('hotjava')== -1)); -var is_nav4up = (is_nav && (is_major >= 4)); - -var is_ie = ((agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1)); -var is_ie5 = (is_ie && (is_major == 4) && (agt.indexOf("msie 5.0")!= -1) ); -var is_ie5_5 = (is_ie && (is_major == 4) && (agt.indexOf("msie 5.5") != -1)); -var is_ie6 = (is_ie && (is_major == 4) && (agt.indexOf("msie 6.0") != -1)); - -var is_ie5up = (is_ie && (is_major == 4) && ( (agt.indexOf("msie 5.0")!=-1) || (agt.indexOf("msie 5.5")!=-1) || (agt.indexOf("msie 6.0")!=-1) ) ); - -var pluginDetected = false; -var activeXDisabled = false; - -// we can check for plugin existence only when browser is 'is_ie5up' or 'is_nav4up' -if(is_nav4up) { - - // Refresh 'navigator.mimeTypes' to get newly installed mimeTypes. - // Use 'navigator.mimeTypes.refresh(false)' to refresh mimeTypes - // without refreshing open documents (browser windows) - - // check for Java plugin in installed mimeTypes - if(navigator.mimeTypes ) { - //window.alert( "length"); - //window.alert( navigator.mimeTypes.length); - for (i=0; i < navigator.mimeTypes.length; i++) { - //window.alert(navigator.mimeTypes[i].type); - if( (navigator.mimeTypes[ i].type != null) - &&(navigator.mimeTypes[ i].type.indexOf( - "application/x-java-applet;jpi-version=1.4") != -1) ) { - - pluginDetected = true; - break; - } - - } - } - -} else if (is_ie5up) { - var javaVersion; - var shell; - try { - // Create WSH(WindowsScriptHost) shell, available on Windows only - shell = new ActiveXObject("WScript.Shell"); - - if (shell != null) { - // Read JRE version from Window Registry - try { - javaVersion = shell.regRead - ("HKEY_LOCAL_MACHINE\\Software\\JavaSoft\\Java Runtime Environment\\CurrentVersion"); - } catch(e) { - // handle exceptions raised by 'shell.regRead(...)' here - // so that the outer try-catch block would receive only - // exceptions raised by 'shell = new ActiveXObject(...)' - } - } - } catch(e) { - window.alert(" Creating ActiveX controls thru script is disabled \n in InternetExplorer security options \n To enable it: \n a. Go to the 'Tools -->; Internet Options' menu\n b. Select the 'Security' tab\n c. Select zone (Internet/Intranet)\n d. Click the 'Custom Level..' button which will display the\n 'Security Settings' window.\n e. Enable the option 'Initialize and script ActiveX controls\n not marked as safe' "); - - activeXDisabled = true; - } - - // Check whether we got required (1.4+) Java Plugin - if ( (javaVersion != null) && (javaVersion.indexOf("1.4") != -1) ) { - pluginDetected = true; - } - -} - - -if (pluginDetected) { - - // show applet page - document.location.href="newappletref.htm"; - -} else if (confirm("Java Plugin 1.4+ not found, Do you want to download it?\n" + - "if you choose not to install the plugin the reports graphical applets will not be available.")) { - - // show install page - document.location.href=XilinxD; - -} else { - // show error page - document.location.href="newappletref.htm"; -} - -} - diff --git a/address_decoder_html/fit/prev.jpg b/address_decoder_html/fit/prev.jpg deleted file mode 100644 index eb29285..0000000 Binary files a/address_decoder_html/fit/prev.jpg and /dev/null differ diff --git a/address_decoder_html/fit/print.jpg b/address_decoder_html/fit/print.jpg deleted file mode 100644 index b558dec..0000000 Binary files a/address_decoder_html/fit/print.jpg and /dev/null differ diff --git a/address_decoder_html/fit/products.gif b/address_decoder_html/fit/products.gif deleted file mode 100644 index 7680404..0000000 Binary files a/address_decoder_html/fit/products.gif and /dev/null differ diff --git a/address_decoder_html/fit/purchase.gif b/address_decoder_html/fit/purchase.gif deleted file mode 100644 index 177f4ba..0000000 Binary files a/address_decoder_html/fit/purchase.gif and /dev/null differ diff --git a/address_decoder_html/fit/report.htm b/address_decoder_html/fit/report.htm deleted file mode 100644 index eceb1bb..0000000 --- a/address_decoder_html/fit/report.htm +++ /dev/null @@ -1,27 +0,0 @@ - - - - - - - diff --git a/address_decoder_html/fit/result.htm b/address_decoder_html/fit/result.htm deleted file mode 100644 index a63a253..0000000 --- a/address_decoder_html/fit/result.htm +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - diff --git a/address_decoder_html/fit/search.gif b/address_decoder_html/fit/search.gif deleted file mode 100644 index 714dc20..0000000 Binary files a/address_decoder_html/fit/search.gif and /dev/null differ diff --git a/address_decoder_html/fit/spacer.gif b/address_decoder_html/fit/spacer.gif deleted file mode 100644 index 0eba199..0000000 Binary files a/address_decoder_html/fit/spacer.gif and /dev/null differ diff --git a/address_decoder_html/fit/style.css b/address_decoder_html/fit/style.css deleted file mode 100644 index 5f32596..0000000 --- a/address_decoder_html/fit/style.css +++ /dev/null @@ -1,19 +0,0 @@ - -.tocRef A:link {font-family:arial black; font-size:14px;} -.tocRef A:visited {font-family:arial black; font-size:14px;} -.tocRef A:active {font-family:arial black; font-size:14px;} -.tocRef A:hover {font-family:arial black; font-size:14px;} -.tocBgnd {background:#CCCCCC;} - - -.pgRef A:link { } -.pgRef A:visited { } -.pgRef A:active { } -.pgRef A:hover { } -.pgHeader {background:#E7CF5A;} -.pgBgnd {background:#FFFFFF;} - - -#tipBox {position: absolute; width: 150px; z-index: 100;border: 1pt black solid; background: white; visibility: hidden;} -.tipBoxCursor {cursor:crosshair;} - diff --git a/address_decoder_html/fit/summary.js b/address_decoder_html/fit/summary.js deleted file mode 100644 index 6fe7722..0000000 --- a/address_decoder_html/fit/summary.js +++ /dev/null @@ -1,26 +0,0 @@ -function popWin(url, w, h) { - var win = window.open(url, 'win', - 'toolbar=no,location=no,directories=no,status=no,menubar=no,scrollbars=yes,resizable=yes,width='+w+',height='+h); - win.focus(); -} - -function showTop() { parent.leftnav.showTop(); } - -function showDoc(device) { - var url = docURL; - - if ((device.indexOf("XC2") != -1) && (device.indexOf("S") != -1)) - url = docCr2sURL; - else if (device.indexOf("XC2") != -1) url = docXbrURL; - else if (device.indexOf("XCR3") != -1) url = docXpla3URL; - else if (device.indexOf("XV") != -1) url = doc95xvURL; - else if (device.indexOf("XL") != -1) url = doc95xlURL; - else url = doc95URL; - - popWin(url); -} - -function priceDev(device) { - var url = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/1816638537/Catalog"; - popWin(url); -} diff --git a/address_decoder_html/fit/summarydoc.htm b/address_decoder_html/fit/summarydoc.htm deleted file mode 100644 index 71bad37..0000000 --- a/address_decoder_html/fit/summarydoc.htm +++ /dev/null @@ -1,102 +0,0 @@ - - - - - - - - - - -Summary - - - - - - - - - - - - - - - - - - - - - - -

Summary

- -

The - Summary section of the WebFITTER XML report contains several tables summarizing - the fitting results for your design.

- -The general - Summary table contains the following: - -
    - -
  • The - design name
    • - -
  • The - fitting status
    • - -
  • The - software version
    • - -
  • The - device used, with a link to a PDF version of the device documentation
    • - -
  • The - time and date of the fitter's completion
    • -
- -The Resources - Summary table includes: - -
    - -
  • The - number and percentage of macrocells used
    • - -
  • The - number and percentage of product terms used
    • - -
  • The - number and percentage of registers used
    • - -
  • The - number and percentage of pins used  
    • - -
  • The - number and percentage of function block inputs used
    • -
- -The tables - that follow give more detailed summaries (when appropriate, depending - on your design and device) of the pin resources, macrocell resources, - global resources, and block resources utilized by the fitter, as well - as the macrocell power data for the design. - - - - diff --git a/address_decoder_html/fit/support.gif b/address_decoder_html/fit/support.gif deleted file mode 100644 index a154620..0000000 Binary files a/address_decoder_html/fit/support.gif and /dev/null differ diff --git a/address_decoder_html/fit/tooltips.js b/address_decoder_html/fit/tooltips.js deleted file mode 100644 index 790ce27..0000000 --- a/address_decoder_html/fit/tooltips.js +++ /dev/null @@ -1,143 +0,0 @@ -/* Your are permitted to reuse this code as long as the following copyright - notice is not removed: - - This HTML tip handling is copyright 1998 by insideDHTML.com, LLC. More information about this - code can be found at Inside Dynamic HTML: HTTP://www.insideDHTML.com -*/ - - -// Support for all collection -var allSupport = document.all!=null; - -function setupEventObject(e) { - // Map NS event object to IEs - if (e==null) return; // IE returns - window.event = e; - window.event.fromElement = e.target; - window.event.toElement = e.target; - window.event.srcElement = e.target; - window.event.x = e.x; - window.event.y = e.y; - // Route the event to the original element - // Necessary to make sure _tip is set. - window.event.srcElement.handleEvent(e); -} - -function checkName(src) { - // Look for tooltip in IE - while ((src!=null) && (src._tip==null)) - src = src.parentElement; - return src; -} - -function getElement(elName) { - // Get an element from its ID - if (allSupport) return document.all[elName]; - else return document.layers[elName]; -} - -function writeContents(el, tip) { - // Replace the contents of the tooltip - if (allSupport) - el.innerHTML = tip; - else { - // In NS, insert a table to work around - // stylesheet rendering bug. - // NS fails to apply style sheets when writing - // contents into a positioned element. - el.document.open(); - el.document.write("
"); - el.document.write(tip); - el.document.write("
"); - el.document.close(); - } -} - -function getOffset(el, which) { - // Function for IE to calculate position - // of an element. - var amount = el["offset"+which]; - if (which=="Top") amount+=el.offsetHeight; - el = el.offsetParent; - while (el!=null) { - amount+=el["offset"+which]; - el = el.offsetParent; - } - return amount; -} - - -function setPosition(el) { - // Set the position of an element - - src = window.event.srcElement - if (allSupport) { - el.style.pixelTop = getOffset(src, "Top"); - el.style.pixelLeft = getOffset(src, "Left"); - } - else { - el.top = src.y + 20; //window.event.y + 15 - el.left = src.x; //window.event.x - } -} - -function setVisibility(el, bDisplay) { - // Hide or show to tip - if (bDisplay) { - if (allSupport) el.style.visibility = "visible"; - else el.visibility = "show"; - } - else { - if (allSupport) el.style.visibility = "hidden"; - else el.visibility = "hidden"; - } -} - - -function displayContents(tip) { - // Display the tooltip. - var el = getElement("tipBox"); - writeContents(el, tip); - setPosition(el); - setVisibility(el, true); -} - - -function doMouseOver(e) { - // Mouse moves over an element - setupEventObject(e); - var el, tip; - if ((el = checkName(window.event.srcElement))!=null) { - if (!el._display) { - displayContents(el._tip); - el._display = true; - } - } -} - -function doMouseOut(e) { - // Mouse leaves an element - setupEventObject(e); - el = checkName(window.event.srcElement); - var el, tip; - if ((el = checkName(window.event.srcElement))!=null) { - if (el._display) { - if ((el.contains==null) || (!el.contains(window.event.toElement))) { - setVisibility(getElement("tipBox"), false); - el._display = false; - } - } - } -} - -function doLoad() { - // Do Loading - if ((window.document.captureEvents==null) && (!allSupport)) - return; // Not IE4 or NS4 - if (window.document.captureEvents!=null) // NS - capture events - window.document.captureEvents(Event.MOUSEOVER | Event.MOUSEOUT) - window.document.onmouseover = doMouseOver; - window.document.onmouseout = doMouseOut; -} - -window.onload = doLoad; diff --git a/address_decoder_html/fit/topnav.js b/address_decoder_html/fit/topnav.js deleted file mode 100644 index 0e85b7b..0000000 --- a/address_decoder_html/fit/topnav.js +++ /dev/null @@ -1,28 +0,0 @@ -function popWin(url) { - var win = window.open(url, 'win', - 'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600'); - win.focus(); -} - -function openTab(type, device) { - var url = rootURL; - switch (type) { - case 0: url = rootURL; break; - case 1: - if (device.indexOf('XC2') != -1) url += prodURL + xbrURL; - else if (device.indexOf('XCR3') != -1) url += prodURL + xpla3URL; - else if (device.indexOf('XV') != -1) url += prodURL + xc9500xvURL; - else if (device.indexOf('XL') != -1) url += prodURL + xc9500xlURL; - else url += prodURL + xc9500URL; - break; - case 2: url += marketURL; break; - case 3: url = supportURL; break; - case 4: url += educationURL; break; - case 5: url = buyURL; break; - case 6: url += contactURL; break; - case 7: url += searchURL; break; - default: url = rootURL; - } - - popWin(url); -} diff --git a/address_decoder_html/fit/unmapinputdoc.htm b/address_decoder_html/fit/unmapinputdoc.htm deleted file mode 100644 index fe242d6..0000000 --- a/address_decoder_html/fit/unmapinputdoc.htm +++ /dev/null @@ -1,65 +0,0 @@ - - - - - - - - - - -unmapinputdoc - - - - - - - - - - - - - - - - - - - - - - - - -

Unmapped Inputs

- -

This page shows - input signals which were either not mapped or not - routed.

- - - - diff --git a/address_decoder_html/fit/unmaplogicdoc.htm b/address_decoder_html/fit/unmaplogicdoc.htm deleted file mode 100644 index 6371313..0000000 --- a/address_decoder_html/fit/unmaplogicdoc.htm +++ /dev/null @@ -1,68 +0,0 @@ - - - - - - - - - - -unmaplogicdoc - - - - - - - - - - - - - - - - - - - - - - - - -

Unmapped Logic

- -

This page shows those equations whose - logic was either not placed or not completely - placed in the specified device.

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Introduction

- -

This report is the result of a static timing analysis of your design - after it has been fit in the device that you selected. The timing values - given represent the worst-case values over the recommended operating conditions - for the part.

- -

Overview

- -

The timing report consists of a series of sections:

- -

Summary

- -

This table summarizes the external timing parameters for your device, - including tPD, - tCO, - tSU, - tCYC, - and fSYSTEM. -  For a more - detailed description of the timing model for your device, please refer - to the application notes linked below.

- -

Timing Constraints

- -

This section reports on any timing constraints that you created for - your design. Timing constraints can be entered using the Constraints Editor - tool, or by editing an Implementation Constraints File directly. For more - information on creating timing constraints, see the Constraints Guide. -

- -

Note that if you - did not define any constraints for your design, then the timing analysis - software will automatically create a default set of constraints for you. - These include pad-to-pad, register-to-register, pad-to-register, and period - constraints. A constraint value of 0 ns - will be used for all of these automatically generated constraints. As - a result, all paths listed under each constraint will violate the constraint, - and will have a negative value for slack.

- -

Note also that to - limit the size of the report, each path endpoint involved in a timing - path will only be listed once, under a single constraint.  

- -

For each timing path listed under a constraint, there is a hyperlink - that can be used to open a window listing the individual internal delay - elements traversed in the path. To understand these delay elements, consult - the Definitions section below, or the following - application notes and white papers:

- -

XAPP375: Understanding - the CoolRunner-II - Timing Model

- -

WP122: - Using the CoolRunner - XPLA3 Timing Model

- -

XAPP071: Using - the XC9500 Timing Model

- -

XAPP111: Using - the XC9500XL Timing Model

- -

XAPP - 362: Using the XC9500XV Timing Model

- -

available in the literature section of www.xilinx.com. -

- -

Data Sheet Report

- -

This section of the report lists the external timing parameters for - your design. This includes; maximum external clock speed for each clock, - setup and hold times for each registered input, clock-to-output pad timing - for each registered output, clock to setup time for each register-to-register - timing path, and pad-to-pad time for each combinatorial path through your - design.

- -

Going Further

- -

To do more advanced timing analysis of your design, select the process - Analyze Post-Fit Static Timing - in iSE. This - will run Xilinx's - Timing Analyzer tool interactively.  The - Timing Analyzer provides a powerful, flexible, and easy way to perform - static timing analysis on FPGA - and CPLD designs. - With Timing Analyzer, analysis can be performed immediately after mapping, - placing or routing an FPGA - design, and after fitting and routing a CPLD - design.

- -

Timing Analyzer verifies that the delay along a given path or paths - meets specified timing requirements. It organizes and displays data that - allows you to analyze critical paths in a circuit, the cycle time of the - circuit, the delay along any specified path(s), - and the path with the greatest delay. It also provides a quick analysis - of the effect different speed grades have on the same design.  

- -

Timing Analyzer performs setup and hold checks (skew analysis). It works - with synchronous systems composed of synchronous elements and combinatorial - logic. In synchronous design, Timing Analyzer takes into account all path - delays, including clock-to-out and setup requirements, while calculating - the worst-case timing of the design.

- -

Timing Analyzer creates timing analysis reports based on existing timing - constraints or user specified paths within the program. Timing reports - have a hierarchical browser to quickly jump to different sections of the - reports. Timing paths in reports can be cross probed to synthesis tools - (Exemplar and Synplicity) - and Floorplanner. -

- -

There are several ways to issue commands in Timing Analyzer. Timing - Analyzer can be controlled through GUI - features (menu commands) or its comprehensive macro command language facility. - You can select from menus, click toolbar buttons, type keyboard commands - in the console window, and run macros.

- -

Definitions

- -

Pad to Pad (tPD) -

- -

Reports pad to pad paths that start at input pads and end at output - pads. The maximum external pad to pad delay.  Combinatorial - pad-to-pad paths begin at input pads, propagate through one or more levels - of combinatorial logic and end at output pads. Combinatorial paths also - trace through the enable inputs of 3-state controlled pads. Combinatorial - paths are not traced through clock, and asynchronous set and reset inputs - of registers. These paths are also broken at bidirectional pins

- -

Clock Pad to Output Pad (tCO) -

- -

The maximum external clock pad to output pad delay.  Reports - paths that start at input  pads - trace through clock inputs of  registers - and end at output pads. Paths are not traced through PRE/CLR -  inputs - of registers.  You - can directly specify tCO - for all registered output paths in your design using the Pad-to-Pad timespec. - Clock-Pad-to-Pad paths for global clocks begin at global clock pads, propagate - through global clock buffers, and propagate through the flip-flop Q - output and any number of levels of combinatorial logic and end at the - output pad. Clock-Pad-to-Pad paths for product term clock paths begin - at input pads, propagate through any number of logic levels feeding into - a clock product term, propagate through the flip-flop Q - output and any number of levels of combinatorial logic and end at the - output pad. Clock-Pad-to-Pad paths also trace through the enable inputs - of 3-state controlled pads.

- -

Setup to Clock at Pad (tSU - or tSUF)

- -

Reports external setup time of data  to - clock at pad. Data path starts at an input pad and ends at register  (Fast - Input Register for tSUF) - D/T  input. - Clock path starts at input pad and ends at the register clock input.  Paths - are not traced through registers. Pin-to-pin setup requirement is not - reported or guaranteed for product-term clocks derived from macrocell - feedback signals.

- -

The minimum required setup time for flip-flops.  You - can specify the tSU - (setup-to-clock) for all inputs in your design relative to a global clock - or product term clock. Each tSU - OFFSET timespec involves an input path and a clock path. Input paths start - at input pads, propagate through input buffers and any number of combinatorial - logic levels before ending at a flip-flop D/T input, including the receiving - flip-flop's tSU.  Input - paths are not traced through flip-flop clock pins, asynchronous set/reset - inputs or bidirectional I/O pins. Global clock paths start at global clock - pads, propagate through global clock buffers and end at the flip-flop - clock pin. Product term clock paths start at input pads, propagate through - a single level of logic implemented in a clock product term and end at - the flip-flop clock pin.

- -

Clock to Setup (tCYC)

- -

Register to register cycle time. Includes source register tCO and destination - register tSU.

- -

Note that when the - computed Maximum Clock Speed is limited by tCYC, it is computed assuming - that all registers are rising-edge sensitive.

- -

fSYSTEM

- -

Maximum clock operating frequency.  You - can specify the fSYSTEM (clock frequency or period) for all registered - paths in your design using a Register-to-Register timespec. Register-to-Register - paths begin at flip-flop clock inputs, propagate through the flip-flop - Q output and any number of levels of combinatorial logic and end at the - receiving flip-flop D/T input, including the receiving flip-flop's tSU. - When these flip-flops are clocked by the same clock, the delay on this - path is equivalent to the cycle time of the clock. Registered paths do - not propagate through clock, and asynchronous set and reset inputs of - registers as shown below. These paths are also broken at bidirectional - pins.

- -

 

- - - - diff --git a/address_decoder_html/tim/cpldta_style.css b/address_decoder_html/tim/cpldta_style.css deleted file mode 100644 index 4b82019..0000000 --- a/address_decoder_html/tim/cpldta_style.css +++ /dev/null @@ -1,144 +0,0 @@ - - - - -.cpldta_text_report_header { - font-style: normal; - font-weight: bold; - font-size: 25pt; - font-family: Arial, Helvetica, sans-serif; - text-align: center;} - -.cpldta_text_section_header { - font-style: normal; - font-weight: bold; - font-size: 15pt; - font-family: Arial, Helvetica, sans-serif; - text-align: center;} - -.cpldta_text_subsection_header { - font-style: normal; - font-weight: bold; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: left;} - - -.cpldta_warnings_header { - font-style: normal; - font-weight: normal; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: center; - background-color: #FFFFCC; } - - -.cpldta_text_normal { - font-style: normal; - font-weight: normal; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: left;} - - -.cpldta_text_normal_bold { - font-style: normal; - font-weight: bold; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: left;} - - -.cpldta_constraint_description_normal { - font-style: normal; - font-weight: normal; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: left;} -.cpldta_constraint_description_bold { - font-style: normal; - font-weight: bold; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: left;} - - -.cpldta_constraint_name { - font-style: normal; - font-weight: normal; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: left;} - - -.cpldta_constraint_name_error { - font-style: normal; - font-weight: normal; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: left; - background-color: #FFCCCC; } - - -.cpldta_time_value { - font-style: normal; - font-weight: normal; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: center;} - - -.cpldta_time_value_error { - font-style: normal; - font-weight: normal; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: center; - background-color: #FFCCCC; } - - -.cpldta_delaytable_header { - font-style: normal; - font-weight: bold; - font-size: 12pt; - font-family: Arial, Helvetica, sans-serif; - text-align: center; - background-color: #FFFFCC; } -.cpldta_constraint_header { - font-style: normal; - font-weight: bold; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: left; - background-color: #FFFFCC; } -.cpldta_time_header { - font-style: normal; - font-weight: bold; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: center; - background-color: #FFFFCC; } -.cpldta_text_caption { - font-style: normal; - font-weight: Bold; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: center;} - - -.cpldta_datasheet_pathname { - font-style: normal; - font-weight: normal; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: left;} -.cpldta_datasheet_time_value { - font-style: normal; - font-weight: normal; - font-size: 10pt; - font-family: Arial, Helvetica, sans-serif; - text-align: center;} - - - - diff --git a/address_decoder_html/tim/genreport.htm b/address_decoder_html/tim/genreport.htm deleted file mode 100644 index 43aca47..0000000 --- a/address_decoder_html/tim/genreport.htm +++ /dev/null @@ -1,17 +0,0 @@ - - -Reports - - -; - - - - - - - -<body bgcolor="#FFFFFF" text="#000000"> -</body> - - diff --git a/address_decoder_html/tim/leftnav.htm b/address_decoder_html/tim/leftnav.htm deleted file mode 100644 index e72761d..0000000 --- a/address_decoder_html/tim/leftnav.htm +++ /dev/null @@ -1,37 +0,0 @@ - - -Timing Navigation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-
Timing Report
-
 Description
 Summary
 Constraints
 Definitions
  
- - diff --git a/address_decoder_html/tim/report.htm b/address_decoder_html/tim/report.htm deleted file mode 100644 index fcd16d4..0000000 --- a/address_decoder_html/tim/report.htm +++ /dev/null @@ -1,14 +0,0 @@ - - -Reports - - -; - - - - -<body bgcolor="#FFFFFF" text="#000000"> -</body> - - diff --git a/address_decoder_html/tim/timing_report.htm b/address_decoder_html/tim/timing_report.htm deleted file mode 100644 index 8dd7141..0000000 --- a/address_decoder_html/tim/timing_report.htm +++ /dev/null @@ -1,10 +0,0 @@ - - -Timing report - -

No timing data is available - for your design.

-

Please double click on the - Generate Timing process in the "Process for Current Sources" - window.

- \ No newline at end of file diff --git a/address_decoder_html/tim/toc.css b/address_decoder_html/tim/toc.css deleted file mode 100644 index 29af0e1..0000000 --- a/address_decoder_html/tim/toc.css +++ /dev/null @@ -1,36 +0,0 @@ -.HEADING { - font-size: 15px; - font-family: Arial, Geneva, Verdana, Helvetica; - font-weight: bold; color: #000000; - text-align: normal; - margin-left: 0px; } -.Fitting { - font-size: 11px; - font-family: Arial, Geneva, Verdana, Helvetica; - font-weight: bold; color: #000000; - text-align: normal; - margin-left: 0px; } -.SECONDARY-NAV { - font-size: 11px; - font-family: Arial, Geneva, Verdana, Helvetica; - font-weight: bold; color: #FFFFFF; - margin-left: 0px; - text-decoration: none; ; - list-style-type: disc ; - list-style-position: inside } -.Timing { - font-size: 11px; - font-family: Arial, Geneva, Verdana, Helvetica; - font-weight: bold; color: #333333; - margin-left: 0px; - text-decoration: none; ; - list-style-type: disc ; - list-style-position: inside } -.Timing-Error { - font-size: 11px; - font-family: Arial, Geneva, Verdana, Helvetica; - font-weight: bold; color: #990000; - margin-left: 0px; - text-decoration: none; ; - list-style-type: disc ; - list-style-position: inside } diff --git a/address_decoder_html/tim/topnav.htm b/address_decoder_html/tim/topnav.htm deleted file mode 100644 index 00e11b8..0000000 --- a/address_decoder_html/tim/topnav.htm +++ /dev/null @@ -1,31 +0,0 @@ - - -CPLD Reports Banner - - - - - - - - - - - - - - -
 
- - - - -   
- - - - - - - - diff --git a/spi6502b.bld b/spi6502b.bld deleted file mode 100644 index 68992fb..0000000 --- a/spi6502b.bld +++ /dev/null @@ -1,23 +0,0 @@ -Release - ngdbuild G.38 -Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. - -Command Line: ngdbuild -dd _ngo -uc SPI6502B.ucf -p xc9500xl spi6502b.ngc -spi6502b.ngd - -Reading NGO file "C:/sources/AppleIISd/spi6502b.ngc" ... -Reading component libraries for design expansion... - -Annotating constraints to design from file "SPI6502B.ucf" ... - -Checking timing specifications ... -Checking expanded design ... - -NGDBUILD Design Results Summary: - Number of errors: 0 - Number of warnings: 0 - -Total memory usage is 58712 kilobytes - -Writing NGD file "spi6502b.ngd" ... - -Writing NGDBUILD log file "spi6502b.bld"... diff --git a/spi6502b.ngc b/spi6502b.ngc deleted file mode 100644 index b81ac5d..0000000 --- a/spi6502b.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.2e 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f5=02Bh96Fkc:k11?6=3`8=6=44oc194?=zj8>26=4<:183!e42k<0Dn;4Hea8m73=831b>;4?::ma7?6=3th:?k4?:383>5}#k:09m6Fl5:Jgg>o5<3:17bl<:188yg76;3:1>7>50z&`7?4f3Ai>7Ejl;h07>5<5<4290;w)m<:99Kg0=Olj1b>84?::k12?6=3fh86=44}c321?6=:3:1m50;194?6|,j9146Fl5:Jgg>o5=3:17d<9:188kg5=831vn>j50;694?6|,j91m6Fl5:Jgg>o5=3:17d<9:188m71=831dn>4?::a7`<72;0;6=u+c281e>Nd=2Boo6g=4;29?jd42900qo=i:180>5<7s-i8655Gc49K`f=n:<0;66g=6;29?jd42900qo7=:180>5<7s-i8655Gc49K`f=n:<0;66g=6;29?jd42900qo7<:181>5<7s-i86?o4Hb78Lae1<75`b283>>{e1=0;6>4?:1y'g67Ejl;h06>5<>{e0m0;6>4?:1y'g67Ejl;h06>5<>{e0l0;6?4?:1y'g6<5i2Bh96Fkc:k10?6=3fh86=44}c:e>5<4290;w)m<:99Kg0=Olj1b>84?::k12?6=3fh86=44}c:;>5<4290;w)m<:99Kg0=Olj1b>84?::k12?6=3fh86=44}c::>5<5290;w)m<:3c8Lf3<@mi0e?:50;9lf6<722wi4l4?:283>5}#k:037Em:;If`?l422900e?850;9lf6<722wi4>4?:283>5}#k:037Em:;If`?l422900e?850;9lf6<722wi494?:383>5}#k:09m6Fl5:Jgg>o5<3:17bl<:188yg>229086=4?{%a0>==Ok<1Chn5f2483>>o5>3:17bl<:188yg1b29086=4?{%a0>==Ok<1Chn5f2483>>o5>3:17bl<:188yg1a29096=4?{%a0>7g<@j?0Dim4i3694?=hj:0;66sm8183>6<729q/o>47;Ia6?Mbd3`8>6=44i3494?=hj:0;66sm7583>6<729q/o>47;Ia6?Mbd3`8>6=44i3494?=hj:0;66sm7483>7<729q/o>4=a:J`1>Nck2c987>5;n`0>5<5;n`0>5<5;n`0>5<4?::a34<72:0;6=u+c28;?Me23Anh7d<::188m70=831dn>4?::ab5<72:0;6=u+c28;?Me23Anh7d<::188m70=831dn>4?::abg<72;0;6=u+c281e>Nd=2Boo6g=4;29?jd42900qo??6;297?6=8r.h?764Hb78Lae>ie;3:17pl>0683>7<729q/o>4=a:J`1>Nck2c987>5;n`0>5<52;294~"d;38j7Em:;If`?l432900co=50;9~f46>29086=4?{%a0>==Ok<1Chn5f2483>>o5>3:17bl<:188yg77i3:1>7>50z&`7?4f3Ai>7Ejl;h07>5<5<4290;w)m<:99Kg0=Olj1b>84?::k12?6=3fh86=44}c33g?6=:3:1l5Gc49K`f=n:=0;66am3;29?xda:3:1>7>50z&`7?4f3Ai>7Ejl;h07>5<94?::ma7?6=3thm87>53;294~"d;320Dn;4Hea8m73=831b>;4?::ma7?6=3thm97>53;294~"d;320Dn;4Hea8m73=831b>;4?::ma7?6=3thm:7>53;294~"d;320Dn;4Hea8m73=831b>;4?::ma7?6=3thm;7>53;294~"d;320Dn;4Hea8m73=831b>;4?::ma7?6=3thm47>53;294~"d;3h=7Em:;If`?l422900e?850;9lf6<722wij44?:283>5}#k:0i:6Fl5:Jgg>o5=3:17d<9:188kg5=831vnko50;194?6|,j91n;5Gc49K`f=n:<0;66g=6;29?jd42900qohl:180>5<7s-i86o84Hb78Lae>ie;3:17plid;297?6=8r.h?764Hb78Lae>ie;3:17plie;297?6=8r.h?764Hb78Lae>ie;3:17plif;297?6=8r.h?764Hb78Lae>ie;3:17pl>0183>6<729q/o>47;Ia6?Mbd3`8>6=44i3494?=hj:0;66sm11394?5=83:p(n=5b79Kg0=Olj1b>84?::k12?6=3fh86=44}c336?6=;3:14?::a555=8391<7>t$b19<>Nd=2Boo6g=5;29?l412900co=50;9~f46329086=4?{%a0>==Ok<1Chn5f2483>>o5>3:17bl<:188yg7413:1>7>50z&`7?4f3Ai>7Ejl;h07>5<5<5290;w)m<:3c8Lf3<@mi0e?:50;9lf6<722wi=><50;094?6|,j91>l5Gc49K`f=n:=0;66am3;29?xd6;:0;6?4?:1y'g6<5i2Bh96Fkc:k10?6=3fh86=44}c31`?6=:3:1i:181>5<7s-i86?o4Hb78Lae1<75`b283>>{e98:1<7=50;2x f5=02Bh96Fkc:k11?6=3`8=6=44oc194?=zj0=1<7=50;2x f5=02Bh96Fkc:k11?6=3`8=6=44oc194?=zj021<7<50;2x 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4>c28l;7c?7c;48yv4703:1>v3l2;34b>;6k903h6*>8e814d=i91i1>6s|2c294?4|5;<:6?l?;<;7>=d<,82o6?l=;o3;g?452z?041<1827hh7?76:&2>;:4:89fb=9>o0(<6k:0d3?k7?k3=0q~"60m09n?5a19a91>{t:9h1<765j4$0:g>76f3g;3o7>4}r07`?6=:r798h4>609>g6<60o1v8b83?xu58>0;6?u2c3823`=:9ko14i5+19f965g5rs3ce>5<5s48=57e3-;3h7744==916>l95519>6`1==916>ho5519>6dg==916>l75519>6=`==916>4>5519>6`?=9?;0qpsr}AB@5ok}ABA5{GHYqvLM \ No newline at end of file diff --git a/spi6502b.prj b/spi6502b.prj deleted file mode 100644 index 7d4ebfb..0000000 --- a/spi6502b.prj +++ /dev/null @@ -1,2 +0,0 @@ -vhdl work address_decoder.vhf -vhdl work SPI6502B1.1.vhd diff --git a/spi6502b.syr b/spi6502b.syr deleted file mode 100644 index 3b0c698..0000000 --- a/spi6502b.syr +++ /dev/null @@ -1,253 +0,0 @@ -Release 6.3.03i - xst G.38 -Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ---> Parameter TMPDIR set to __projnav -CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s - ---> Parameter xsthdpdir set to ./xst -CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s - ---> Reading design: spi6502b.prj - -TABLE OF CONTENTS - 1) Synthesis Options Summary - 2) HDL Compilation - 3) HDL Analysis - 4) HDL Synthesis - 5) Advanced HDL Synthesis - 5.1) HDL Synthesis Report - 6) Low Level Synthesis - 7) Final Report - -========================================================================= -* Synthesis Options Summary * -========================================================================= ----- Source Parameters -Input File Name : spi6502b.prj -Input Format : mixed -Ignore Synthesis Constraint File : NO -Verilog Include Directory : - ----- Target Parameters -Output File Name : spi6502b -Output Format : NGC -Target Device : xc9500xl - ----- Source Options -Top Module Name : spi6502b -Automatic FSM Extraction : YES -FSM Encoding Algorithm : Auto -Mux Extraction : YES -Resource Sharing : YES - ----- Target Options -Add IO Buffers : YES -Equivalent register Removal : YES -MACRO Preserve : YES -XOR Preserve : YES - ----- General Options -Optimization Goal : Speed -Optimization Effort : 1 -Keep Hierarchy : YES -RTL Output : Yes -Hierarchy Separator : _ -Bus Delimiter : <> -Case Specifier : maintain - ----- Other Options -lso : spi6502b.lso -verilog2001 : YES -Clock Enable : YES -wysiwyg : NO - -========================================================================= - - -========================================================================= -* HDL Compilation * -========================================================================= -Compiling vhdl file C:/sources/AppleIISd/address_decoder.vhf in Library work. -Architecture behavioral of Entity fd_mxilinx_address_decoder is up to date. -Architecture behavioral of Entity fdrs_mxilinx_address_decoder is up to date. -Architecture behavioral of Entity address_decoder is up to date. -Compiling vhdl file C:/sources/AppleIISd/SPI6502B1.1.vhd in Library work. -Entity (Architecture ) compiled. - -========================================================================= -* HDL Analysis * -========================================================================= -Analyzing Entity (Architecture ). -INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 240: Mux is complete : default of case is discarded -INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 353: Mux is complete : default of case is discarded -Entity analyzed. Unit generated. - -Analyzing Entity (Architecture ). - Set user-defined property "HU_SET = XLXI_16_1" for instance in unit . -Entity analyzed. Unit generated. - -Analyzing Entity (Architecture ). - Set user-defined property "HU_SET = U0_0" for instance in unit . -Entity analyzed. Unit generated. - -Analyzing Entity (Architecture ). -Entity analyzed. Unit generated. - - -========================================================================= -* HDL Synthesis * -========================================================================= - -Synthesizing Unit . - Related source file is C:/sources/AppleIISd/address_decoder.vhf. -Unit synthesized. - - -Synthesizing Unit . - Related source file is C:/sources/AppleIISd/address_decoder.vhf. -Unit synthesized. - - -Synthesizing Unit . - Related source file is C:/sources/AppleIISd/address_decoder.vhf. -Unit synthesized. - - -Synthesizing Unit . - Related source file is C:/sources/AppleIISd/SPI6502B1.1.vhd. - Found 8-bit tristate buffer for signal . - Found 1-bit tristate buffer for signal . - Found 1-bit tristate buffer for signal . - Found 1-bit xor3 for signal <$n0040> created at line 243. - Found 4-bit adder for signal <$n0047> created at line 197. - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 3-bit down counter for signal . - Found 3-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 4-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 8-bit register for signal . - Found 8-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 24 1-bit 2-to-1 multiplexers. - Summary: - inferred 1 Counter(s). - inferred 20 D-type flip-flop(s). - inferred 1 Adder/Subtracter(s). - inferred 10 Tristate(s). -Unit synthesized. - - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - -Advanced RAM inference ... -Advanced multiplier inference ... -Advanced Registered AddSub inference ... -Dynamic shift register inference ... - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# Adders/Subtractors : 1 - 4-bit adder : 1 -# Registers : 25 - 1-bit register : 22 - 8-bit register : 1 - 3-bit register : 1 - 4-bit register : 1 -# Multiplexers : 12 - 2-to-1 multiplexer : 12 -# Tristates : 3 - 1-bit tristate buffer : 2 - 8-bit tristate buffer : 1 -# Xors : 1 - 1-bit xor3 : 1 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -========================================================================= -* Final Report * -========================================================================= -Final Results -RTL Top Level Output File Name : spi6502b.ngr -Top Level Output File Name : spi6502b -Output Format : NGC -Optimization Goal : Speed -Keep Hierarchy : YES -Target Technology : xc9500xl -Macro Preserve : YES -XOR Preserve : YES -Clock Enable : YES -wysiwyg : NO - -Design Statistics -# IOs : 32 - -Macro Statistics : -# Registers : 60 -# 1-bit register : 60 -# Tristates : 3 -# 1-bit tristate buffer : 2 -# 8-bit tristate buffer : 1 -# Xors : 5 -# 1-bit xor2 : 5 - -Cell Usage : -# BELS : 256 -# AND2 : 120 -# AND3 : 6 -# AND4 : 1 -# GND : 2 -# INV : 76 -# OR2 : 43 -# OR3 : 1 -# VCC : 2 -# XOR2 : 5 -# FlipFlops/Latches : 38 -# FD : 1 -# FDC : 5 -# FDCE : 27 -# FDCP : 2 -# FDP : 1 -# FDPE : 2 -# IO Buffers : 32 -# IBUF : 14 -# IOBUFE : 8 -# OBUF : 8 -# OBUFE : 2 -# Others : 5 -# AND2B1 : 2 -# AND4B1 : 1 -# NAND2 : 2 -========================================================================= -CPU : 1.05 / 1.48 s | Elapsed : 1.00 / 1.00 s - ---> - -Total memory usage is 69656 kilobytes - - diff --git a/spi6502b_pad.csv b/spi6502b_pad.csv deleted file mode 100644 index a1a112e..0000000 --- a/spi6502b_pad.csv +++ /dev/null @@ -1,73 +0,0 @@ -Release 6.1i - Fit G.38 -Copyright(c) 1995-2003 Xilinx Inc. All rights reserved - - 5-11-2017 2:09AM - -NOTE: This file is designed to be imported into a spreadsheet program -such as Microsoft Excel for viewing, printing and sorting. The comma ',' -character is used as the data field separator. -This file is also designed to support parsing. - -Input file: spi6502b.ngd -output file: spi6502b_pad.csv -Part type: xc9572xl -Speed grade: -10 -Package: pc44 - -Pinout by Pin Number: - ------,-----,-----,-----,-----,-----,-----,-----,-----,-----, -Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,{blank},Slew Rate,Termination,{blank},Voltage,Constraint, -P1,TIE,,I/O,,,,,,,,,, -P2,cpu_d<0>,I/O,I/O,BIDIR,,,,,,,,, -P3,cpu_d<1>,I/O,I/O,BIDIR,,,,,,,,, -P4,cpu_d<2>,I/O,I/O,BIDIR,,,,,,,,, -P5,cpu_Nphi2,I,I/O/GCK1,INPUT,,,,,,,,, -P6,extclk,GCK/I,I/O/GCK2,,,,,,,,,, -P7,cpu_rnw,I,I/O/GCK3,INPUT,,,,,,,,, -P8,cpu_d<3>,I/O,I/O,BIDIR,,,,,,,,, -P9,cpu_d<4>,I/O,I/O,BIDIR,,,,,,,,, -P10,GND,,GND,,,,,,,,,, -P11,cpu_d<5>,I/O,I/O,BIDIR,,,,,,,,, -P12,cpu_d<6>,I/O,I/O,BIDIR,,,,,,,,, -P13,cpu_d<7>,I/O,I/O,BIDIR,,,,,,,,, -P14,noe,O,I/O,OUTPUT,,,,,,,,, -P15,TDI,,TDI,,,,,,,,,, -P16,TMS,,TMS,,,,,,,,,, -P17,TCK,,TCK,,,,,,,,,, -P18,Ncs2,I,I/O,INPUT,,,,,,,,, -P19,cpu_Nres,I,I/O,INPUT,,,,,,,,, -P20,ng,O,I/O,OUTPUT,,,,,,,,, -P21,VCC,,VCCINT,,,,,,,,,, -P22,cpu_a<0>,I,I/O,INPUT,,,,,,,,, -P23,GND,,GND,,,,,,,,,, -P24,cpu_a<1>,I,I/O,INPUT,,,,,,,,, -P25,b8,O,I/O,OUTPUT,,,,,,,,, -P26,b9,O,I/O,OUTPUT,,,,,,,,, -P27,b10,O,I/O,OUTPUT,,,,,,,,, -P28,spi_Nsel,O,I/O,OUTPUT,,,,,,,,, -P29,led,O,I/O,OUTPUT,,,,,,,,, -P30,TDO,,TDO,,,,,,,,,, -P31,GND,,GND,,,,,,,,,, -P32,VCC,,VCCIO,,,,,,,,,, -P33,TIE,,I/O,,,,,,,,,, -P34,spi_sclk,O,I/O,OUTPUT,,,,,,,,, -P35,spi_mosi,O,I/O,OUTPUT,,,,,,,,, -P36,a8,I,I/O,INPUT,,,,,,,,, -P37,a9,I,I/O,INPUT,,,,,,,,, -P38,a10,I,I/O,INPUT,,,,,,,,, -P39,cpu_Nirq,O,I/O/GSR,OUTPUT,,,,,,,,, -P40,nio_sel,I,I/O/GTS2,INPUT,,,,,,,,, -P41,VCC,,VCCINT,,,,,,,,,, -P42,spi_int,I,I/O/GTS1,INPUT,,,,,,,,, -P43,nio_stb,I,I/O,INPUT,,,,,,,,, -P44,spi_miso,I,I/O,INPUT,,,,,,,,, - -To preserve the pinout above for future design iterations in -Project Navigator simply execute the (Lock Pins) process -located under the (Implement Design) process in a toolbox named -(Optional Implementation Tools) or invoke PIN2UCF from the -command line. The location constraints will be written into your -specified UCF file - -