diff --git a/.gitignore b/.gitignore
index 3096d2b..0d6d309 100644
--- a/.gitignore
+++ b/.gitignore
@@ -219,3 +219,5 @@ VHDL/_pace\.ucf
 VHDL/AppleIISd\.tim
 
 VHDL/AppleIISd\.jed
+
+Firmware/AppleIISd.bin
diff --git a/ProFile.zip b/Binary/ProFile.zip
similarity index 100%
rename from ProFile.zip
rename to Binary/ProFile.zip
diff --git a/Firmware/src/AppleIISd.inc b/Firmware/src/AppleIISd.inc
index 5659e3e..e1838b9 100644
--- a/Firmware/src/AppleIISd.inc
+++ b/Firmware/src/AppleIISd.inc
@@ -48,7 +48,6 @@ KNOWNRTS    :=    $FF58
 OAPPLE      :=    $C061       ; open apple key
 DATA        :=    $C080
 CTRL        :=    DATA+1
-DIV         :=    DATA+2
 SS          :=    DATA+3
 
 ; Constants
diff --git a/Firmware/src/AppleIISd.s b/Firmware/src/AppleIISd.s
index 7e17e4a..46f08bb 100644
--- a/Firmware/src/AppleIISd.s
+++ b/Firmware/src/AppleIISd.s
@@ -1,10 +1,10 @@
 ;*******************************
 ;
 ; Apple][Sd Firmware
-; Version 1.2.1
+; Version 1.2.2
 ; Main source
 ;
-; (c) Florian Reitz, 2017 - 2018
+; (c) Florian Reitz, 2017 - 2020
 ;
 ; X register usually contains SLOT16
 ; Y register is used for counting or SLOT
@@ -53,7 +53,8 @@
             LDX   #$20
             LDX   #$00
             LDX   #$03
-            LDX   #$00        ; is Smartport controller
+            ;LDX   #$00        ; is Smartport controller
+            LDX   #$3C        ; is a disk controller
 
             SEI               ; find slot
             LDA   #$60        ; opcode for RTS
@@ -65,7 +66,6 @@
             STA   CURSLOT     ; $Cs
             AND   #$0F
             STA   SLOT        ; $0s
-            TAY               ; Y holds now SLOT
             ASL   A
             ASL   A
             ASL   A
@@ -95,7 +95,6 @@
             JMP   (CMDLO)
 
 @INIT:      JSR   INIT
-            CMP   #NO_ERR
             BNE   @NEXTSLOT   ; init not successful
 
 ;*******************************
@@ -228,13 +227,9 @@ DRIVER:     CLC               ; ProDOS entry
 ;*******************************
 
             .segment "EXTROM"
-INIT:       LDA   #$03        ; set SPI mode 3
-            STA   CTRL,X
-            LDA   SS,X
-            ORA   #SS0        ; set CS high
+INIT:       STZ   CTRL,X      ; reset SPI controller
+            LDA   #SS0        ; set CS high
             STA   SS,X
-            LDA   #7          ; set 400 kHz
-            STA   DIV,X
             LDY   #10
             LDA   #DUMMY
 
@@ -362,13 +357,13 @@ INIT:       LDA   #$03        ; set SPI mode 3
 @END1:      LDA   SS,X        ; set CS high
             ORA   #SS0
             STA   SS,X
-            LDA   #0          ; set div to 2
-            STA   DIV,X
             TYA               ; retval in A
             RTS
 
 
-TEXT:       .asciiz " Apple][Sd v1.2.1 (c)2018 Florian Reitz "
+TEXT:       .asciiz " Apple][Sd v1.2.2 (c)2020 Florian Reitz"
+            .assert(*-TEXT)=40, error, "TEXT must be 40 bytes long"
+
 
 CMD0:       .byt $40, $00, $00
             .byt $00, $00, $95
diff --git a/Firmware/src/Smartport.s b/Firmware/src/Smartport.s
index da41235..ce781c3 100644
--- a/Firmware/src/Smartport.s
+++ b/Firmware/src/Smartport.s
@@ -95,8 +95,10 @@ SMARTPORT:  LDY   #SMZPSIZE-1   ; save zeropage area for Smarport
             BCC   @RESTZP
 
             TXA
+;warum feste anzahl an bytes für return wert?
             LDY   #2            ; highbyte of # bytes transferred
             LDX   #0            ; low byte of # bytes transferred
+;warum wird mit #1 verglichen?
             CMP   #1            ; C=1 if A != NO_ERR
             RTS
 
diff --git a/README.md b/README.md
index f946d9b..f5cdc73 100644
--- a/README.md
+++ b/README.md
@@ -112,6 +112,8 @@ The control registers of the *AppleIISd* are mapped to the usual I/O space at **
 
 **DATA** SPI data register - Is used for both input and output. When the register is written to, the controller will output the byte on the SPI bus. When it is read from, it reflects the data that was received over the SPI bus.
 
+**PGMEN** Program Enable - Enable programing of the internal firmware eeprom. Should be reset immediately after writing to the device.
+
 **ECE** External Clock Enable - This bit enables the the external clock input to the SPI controller. In the *AppleIISd*, this effectively switches the SPI clock between 500kHz (ECE = 0) and 3.5MHz (ECE = 1).
 
 **FRX** Fast Receive mode - When set to 1, fast receive mode triggers shifting upon reading or writing the SPI Data register. When set to 0, shifting is only triggered by writing the SPI data register.