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Merge remote-tracking branch 'origin/devel' into devel

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Florian Reitz 2017-10-05 23:12:47 +02:00
commit ff074dc995
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Datasheets/65SPI-B Datasheet V1.1.docx Normal file
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519
VHDL/AddressDecoder.sch
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@ -1,244 +1,275 @@
VERSION 6 <?xml version="1.0" encoding="UTF-8"?>
BEGIN SCHEMATIC <drawing version="7">
BEGIN ATTR DeviceFamilyName "xc9500xl" <attr value="xc9500xl" name="DeviceFamilyName">
DELETE all:0 <trait delete="all:0" />
EDITNAME all:0 <trait editname="all:0" />
EDITTRAIT all:0 <trait edittrait="all:0" />
END ATTR </attr>
BEGIN NETLIST <netlist>
SIGNAL A10 <signal name="A10" />
SIGNAL A9 <signal name="A9" />
SIGNAL A8 <signal name="A8" />
SIGNAL XLXN_10 <signal name="XLXN_10" />
SIGNAL CLK <signal name="CLK" />
SIGNAL XLXN_14 <signal name="XLXN_14" />
SIGNAL B10 <signal name="B10" />
SIGNAL B9 <signal name="B9" />
SIGNAL B8 <signal name="B8" />
SIGNAL NOE <signal name="NIO_SEL" />
SIGNAL XLXN_29 <signal name="NIO_STB" />
SIGNAL NIO_SEL <signal name="XLXN_38" />
SIGNAL NIO_STB <signal name="XLXN_46" />
SIGNAL XLXN_38 <signal name="XLXN_47" />
SIGNAL XLXN_46 <signal name="NDEV_SEL" />
SIGNAL XLXN_47 <signal name="NOE" />
SIGNAL NDEV_SEL <signal name="XLXN_53" />
PORT Input A10 <signal name="RNW" />
PORT Input A9 <signal name="XLXN_55" />
PORT Input A8 <port polarity="Input" name="A10" />
PORT Input CLK <port polarity="Input" name="A9" />
PORT Output B10 <port polarity="Input" name="A8" />
PORT Output B9 <port polarity="Input" name="CLK" />
PORT Output B8 <port polarity="Output" name="B10" />
PORT Output NOE <port polarity="Output" name="B9" />
PORT Input NIO_SEL <port polarity="Output" name="B8" />
PORT Input NIO_STB <port polarity="Input" name="NIO_SEL" />
PORT Input NDEV_SEL <port polarity="Input" name="NIO_STB" />
BEGIN BLOCKDEF fdrs <port polarity="Input" name="NDEV_SEL" />
TIMESTAMP 2001 3 9 11 23 0 <port polarity="Output" name="NOE" />
LINE N 0 -128 64 -128 <port polarity="Input" name="RNW" />
LINE N 0 -256 64 -256 <blockdef name="fdrs">
LINE N 384 -256 320 -256 <timestamp>2001-3-9T11:23:0</timestamp>
LINE N 0 -32 64 -32 <line x2="64" y1="-128" y2="-128" x1="0" />
LINE N 0 -352 64 -352 <line x2="64" y1="-256" y2="-256" x1="0" />
RECTANGLE N 64 -320 320 -64 <line x2="320" y1="-256" y2="-256" x1="384" />
LINE N 192 -64 192 -32 <line x2="64" y1="-32" y2="-32" x1="0" />
LINE N 192 -32 64 -32 <line x2="64" y1="-352" y2="-352" x1="0" />
LINE N 64 -112 80 -128 <rect width="256" x="64" y="-320" height="256" />
LINE N 80 -128 64 -144 <line x2="192" y1="-64" y2="-32" x1="192" />
LINE N 192 -320 192 -352 <line x2="64" y1="-32" y2="-32" x1="192" />
LINE N 192 -352 64 -352 <line x2="80" y1="-112" y2="-128" x1="64" />
END BLOCKDEF <line x2="64" y1="-128" y2="-144" x1="80" />
BEGIN BLOCKDEF inv <line x2="192" y1="-320" y2="-352" x1="192" />
TIMESTAMP 2001 3 9 11 23 50 <line x2="64" y1="-352" y2="-352" x1="192" />
LINE N 0 -32 64 -32 </blockdef>
LINE N 224 -32 160 -32 <blockdef name="inv">
LINE N 64 -64 128 -32 <timestamp>2001-3-9T11:23:50</timestamp>
LINE N 128 -32 64 0 <line x2="64" y1="-32" y2="-32" x1="0" />
LINE N 64 0 64 -64 <line x2="160" y1="-32" y2="-32" x1="224" />
CIRCLE N 128 -48 160 -16 <line x2="128" y1="-64" y2="-32" x1="64" />
END BLOCKDEF <line x2="64" y1="-32" y2="0" x1="128" />
BEGIN BLOCKDEF vcc <line x2="64" y1="0" y2="-64" x1="64" />
TIMESTAMP 2001 3 9 11 23 11 <circle r="16" cx="144" cy="-32" />
LINE N 96 -64 32 -64 </blockdef>
LINE N 64 0 64 -32 <blockdef name="vcc">
LINE N 64 -32 64 -64 <timestamp>2001-3-9T11:23:11</timestamp>
END BLOCKDEF <line x2="32" y1="-64" y2="-64" x1="96" />
BEGIN BLOCKDEF and2 <line x2="64" y1="0" y2="-32" x1="64" />
TIMESTAMP 2001 5 11 10 41 37 <line x2="64" y1="-32" y2="-64" x1="64" />
LINE N 0 -64 64 -64 </blockdef>
LINE N 0 -128 64 -128 <blockdef name="and2">
LINE N 256 -96 192 -96 <timestamp>2001-5-11T10:41:37</timestamp>
ARC N 96 -144 192 -48 144 -48 144 -144 <line x2="64" y1="-64" y2="-64" x1="0" />
LINE N 144 -48 64 -48 <line x2="64" y1="-128" y2="-128" x1="0" />
LINE N 64 -144 144 -144 <line x2="192" y1="-96" y2="-96" x1="256" />
LINE N 64 -48 64 -144 <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
END BLOCKDEF <line x2="64" y1="-48" y2="-48" x1="144" />
BEGIN BLOCKDEF and4 <line x2="144" y1="-144" y2="-144" x1="64" />
TIMESTAMP 2001 5 11 10 43 14 <line x2="64" y1="-48" y2="-144" x1="64" />
LINE N 144 -112 64 -112 </blockdef>
ARC N 96 -208 192 -112 144 -112 144 -208 <blockdef name="and4">
LINE N 64 -208 144 -208 <timestamp>2001-5-11T10:43:14</timestamp>
LINE N 64 -64 64 -256 <line x2="64" y1="-112" y2="-112" x1="144" />
LINE N 256 -160 192 -160 <arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
LINE N 0 -256 64 -256 <line x2="144" y1="-208" y2="-208" x1="64" />
LINE N 0 -192 64 -192 <line x2="64" y1="-64" y2="-256" x1="64" />
LINE N 0 -128 64 -128 <line x2="192" y1="-160" y2="-160" x1="256" />
LINE N 0 -64 64 -64 <line x2="64" y1="-256" y2="-256" x1="0" />
END BLOCKDEF <line x2="64" y1="-192" y2="-192" x1="0" />
BEGIN BLOCKDEF nand2 <line x2="64" y1="-128" y2="-128" x1="0" />
TIMESTAMP 2001 3 9 11 23 50 <line x2="64" y1="-64" y2="-64" x1="0" />
LINE N 0 -64 64 -64 </blockdef>
LINE N 0 -128 64 -128 <blockdef name="nand2">
LINE N 256 -96 216 -96 <timestamp>2001-3-9T11:23:50</timestamp>
CIRCLE N 192 -108 216 -84 <line x2="64" y1="-64" y2="-64" x1="0" />
LINE N 64 -48 64 -144 <line x2="64" y1="-128" y2="-128" x1="0" />
LINE N 64 -144 144 -144 <line x2="216" y1="-96" y2="-96" x1="256" />
LINE N 144 -48 64 -48 <circle r="12" cx="204" cy="-96" />
ARC N 96 -144 192 -48 144 -48 144 -144 <line x2="64" y1="-48" y2="-144" x1="64" />
END BLOCKDEF <line x2="144" y1="-144" y2="-144" x1="64" />
BEGIN BLOCK XLXI_16 fdrs <line x2="64" y1="-48" y2="-48" x1="144" />
PIN C CLK <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
PIN D XLXN_14 </blockdef>
PIN R XLXN_10 <blockdef name="or2">
PIN S XLXN_46 <timestamp>2000-1-1T10:10:10</timestamp>
PIN Q XLXN_47 <line x2="64" y1="-64" y2="-64" x1="0" />
END BLOCK <line x2="64" y1="-128" y2="-128" x1="0" />
BEGIN BLOCK XLXI_17 vcc <line x2="192" y1="-96" y2="-96" x1="256" />
PIN P XLXN_14 <arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
END BLOCK <arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
BEGIN BLOCK XLXI_18 and2 <line x2="48" y1="-144" y2="-144" x1="112" />
PIN I0 A10 <arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
PIN I1 XLXN_38 <line x2="48" y1="-48" y2="-48" x1="112" />
PIN O B10 </blockdef>
END BLOCK <block symbolname="fdrs" name="XLXI_16">
BEGIN BLOCK XLXI_19 and2 <blockpin signalname="CLK" name="C" />
PIN I0 A9 <blockpin signalname="XLXN_14" name="D" />
PIN I1 XLXN_38 <blockpin signalname="XLXN_10" name="R" />
PIN O B9 <blockpin signalname="XLXN_46" name="S" />
END BLOCK <blockpin signalname="XLXN_47" name="Q" />
BEGIN BLOCK XLXI_20 and2 </block>
PIN I0 A8 <block symbolname="vcc" name="XLXI_17">
PIN I1 XLXN_38 <blockpin signalname="XLXN_14" name="P" />
PIN O B8 </block>
END BLOCK <block symbolname="and2" name="XLXI_18">
BEGIN BLOCK XLXI_22 inv <blockpin signalname="A10" name="I0" />
PIN I NIO_SEL <blockpin signalname="XLXN_38" name="I1" />
PIN O XLXN_46 <blockpin signalname="B10" name="O" />
END BLOCK </block>
BEGIN BLOCK XLXI_30 and4 <block symbolname="and2" name="XLXI_19">
PIN I0 A8 <blockpin signalname="A9" name="I0" />
PIN I1 A9 <blockpin signalname="XLXN_38" name="I1" />
PIN I2 A10 <blockpin signalname="B9" name="O" />
PIN I3 XLXN_38 </block>
PIN O XLXN_10 <block symbolname="and2" name="XLXI_20">
END BLOCK <blockpin signalname="A8" name="I0" />
BEGIN BLOCK XLXI_31 inv <blockpin signalname="XLXN_38" name="I1" />
PIN I NIO_STB <blockpin signalname="B8" name="O" />
PIN O XLXN_38 </block>
END BLOCK <block symbolname="inv" name="XLXI_22">
BEGIN BLOCK XLXI_32 nand2 <blockpin signalname="NIO_SEL" name="I" />
PIN I0 XLXN_47 <blockpin signalname="XLXN_46" name="O" />
PIN I1 NDEV_SEL </block>
PIN O NOE <block symbolname="and4" name="XLXI_30">
END BLOCK <blockpin signalname="A8" name="I0" />
END NETLIST <blockpin signalname="A9" name="I1" />
BEGIN SHEET 1 3520 2720 <blockpin signalname="A10" name="I2" />
BEGIN BRANCH A10 <blockpin signalname="XLXN_38" name="I3" />
WIRE 320 704 592 704 <blockpin signalname="XLXN_10" name="O" />
WIRE 592 704 704 704 </block>
WIRE 592 704 592 992 <block symbolname="inv" name="XLXI_31">
WIRE 592 992 1088 992 <blockpin signalname="NIO_STB" name="I" />
END BRANCH <blockpin signalname="XLXN_38" name="O" />
BEGIN BRANCH A9 </block>
WIRE 320 768 528 768 <block symbolname="nand2" name="XLXI_32">
WIRE 528 768 704 768 <blockpin signalname="XLXN_47" name="I0" />
WIRE 528 768 528 1136 <blockpin signalname="NDEV_SEL" name="I1" />
WIRE 528 1136 1088 1136 <blockpin signalname="XLXN_55" name="O" />
END BRANCH </block>
BEGIN BRANCH A8 <block symbolname="inv" name="XLXI_33">
WIRE 320 832 464 832 <blockpin signalname="RNW" name="I" />
WIRE 464 832 704 832 <blockpin signalname="XLXN_53" name="O" />
WIRE 464 832 464 1280 </block>
WIRE 464 1280 1088 1280 <block symbolname="or2" name="XLXI_34">
END BRANCH <blockpin signalname="XLXN_55" name="I0" />
IOMARKER 320 704 A10 R180 28 <blockpin signalname="XLXN_53" name="I1" />
IOMARKER 320 768 A9 R180 28 <blockpin signalname="NOE" name="O" />
IOMARKER 320 832 A8 R180 28 </block>
BEGIN BRANCH CLK </netlist>
WIRE 320 576 912 576 <sheet sheetnum="1" width="3520" height="2720">
WIRE 912 576 912 640 <branch name="A10">
WIRE 912 640 992 640 <wire x2="592" y1="704" y2="704" x1="320" />
END BRANCH <wire x2="704" y1="704" y2="704" x1="592" />
BEGIN BRANCH B10 <wire x2="592" y1="704" y2="992" x1="592" />
WIRE 1344 960 1360 960 <wire x2="1088" y1="992" y2="992" x1="592" />
WIRE 1360 960 1664 960 </branch>
END BRANCH <branch name="A9">
BEGIN BRANCH B9 <wire x2="528" y1="768" y2="768" x1="320" />
WIRE 1344 1104 1360 1104 <wire x2="704" y1="768" y2="768" x1="528" />
WIRE 1360 1104 1664 1104 <wire x2="528" y1="768" y2="1136" x1="528" />
END BRANCH <wire x2="1088" y1="1136" y2="1136" x1="528" />
BEGIN BRANCH B8 </branch>
WIRE 1344 1248 1360 1248 <branch name="A8">
WIRE 1360 1248 1664 1248 <wire x2="464" y1="832" y2="832" x1="320" />
END BRANCH <wire x2="704" y1="832" y2="832" x1="464" />
BEGIN BRANCH NOE <wire x2="464" y1="832" y2="1280" x1="464" />
WIRE 1680 336 1696 336 <wire x2="1088" y1="1280" y2="1280" x1="464" />
END BRANCH </branch>
BEGIN BRANCH NIO_SEL <iomarker fontsize="28" x="320" y="704" name="A10" orien="R180" />
WIRE 320 368 352 368 <iomarker fontsize="28" x="320" y="768" name="A9" orien="R180" />
END BRANCH <iomarker fontsize="28" x="320" y="832" name="A8" orien="R180" />
BEGIN BRANCH NIO_STB <branch name="CLK">
WIRE 320 640 336 640 <wire x2="912" y1="576" y2="576" x1="320" />
END BRANCH <wire x2="912" y1="576" y2="640" x1="912" />
IOMARKER 320 368 NIO_SEL R180 28 <wire x2="992" y1="640" y2="640" x1="912" />
IOMARKER 320 640 NIO_STB R180 28 </branch>
INSTANCE XLXI_31 336 672 R0 <branch name="B10">
BEGIN BRANCH XLXN_38 <wire x2="1664" y1="960" y2="960" x1="1344" />
WIRE 560 640 672 640 </branch>
WIRE 672 640 704 640 <branch name="B9">
WIRE 672 640 672 928 <wire x2="1664" y1="1104" y2="1104" x1="1344" />
WIRE 672 928 1088 928 </branch>
WIRE 672 928 672 1072 <branch name="B8">
WIRE 672 1072 1088 1072 <wire x2="1664" y1="1248" y2="1248" x1="1344" />
WIRE 672 1072 672 1216 </branch>
WIRE 672 1216 1088 1216 <branch name="NIO_SEL">
END BRANCH <wire x2="352" y1="368" y2="368" x1="320" />
INSTANCE XLXI_30 704 896 R0 </branch>
BEGIN BRANCH XLXN_10 <branch name="NIO_STB">
WIRE 960 736 976 736 <wire x2="336" y1="640" y2="640" x1="320" />
WIRE 976 736 992 736 </branch>
END BRANCH <iomarker fontsize="28" x="320" y="368" name="NIO_SEL" orien="R180" />
BEGIN BRANCH XLXN_14 <iomarker fontsize="28" x="320" y="640" name="NIO_STB" orien="R180" />
WIRE 848 496 848 512 <instance x="336" y="672" name="XLXI_31" orien="R0" />
WIRE 848 512 992 512 <branch name="XLXN_38">
END BRANCH <wire x2="672" y1="640" y2="640" x1="560" />
IOMARKER 320 576 CLK R180 28 <wire x2="704" y1="640" y2="640" x1="672" />
INSTANCE XLXI_17 784 496 R0 <wire x2="672" y1="640" y2="928" x1="672" />
INSTANCE XLXI_22 352 400 R0 <wire x2="1088" y1="928" y2="928" x1="672" />
BEGIN BRANCH XLXN_46 <wire x2="672" y1="928" y2="1072" x1="672" />
WIRE 576 368 592 368 <wire x2="1088" y1="1072" y2="1072" x1="672" />
WIRE 592 368 992 368 <wire x2="672" y1="1072" y2="1216" x1="672" />
WIRE 992 368 992 416 <wire x2="1088" y1="1216" y2="1216" x1="672" />
END BRANCH </branch>
INSTANCE XLXI_16 992 768 R0 <instance x="704" y="896" name="XLXI_30" orien="R0" />
INSTANCE XLXI_18 1088 1056 R0 <branch name="XLXN_10">
INSTANCE XLXI_19 1088 1200 R0 <wire x2="992" y1="736" y2="736" x1="960" />
INSTANCE XLXI_20 1088 1344 R0 </branch>
IOMARKER 1664 960 B10 R0 28 <branch name="XLXN_14">
IOMARKER 1664 1104 B9 R0 28 <wire x2="848" y1="496" y2="512" x1="848" />
IOMARKER 1664 1248 B8 R0 28 <wire x2="992" y1="512" y2="512" x1="848" />
INSTANCE XLXI_32 1424 432 R0 </branch>
BEGIN BRANCH XLXN_47 <iomarker fontsize="28" x="320" y="576" name="CLK" orien="R180" />
WIRE 1376 512 1392 512 <instance x="784" y="496" name="XLXI_17" orien="R0" />
WIRE 1392 368 1424 368 <instance x="352" y="400" name="XLXI_22" orien="R0" />
WIRE 1392 368 1392 512 <branch name="XLXN_46">
END BRANCH <wire x2="992" y1="368" y2="368" x1="576" />
IOMARKER 1696 336 NOE R0 28 <wire x2="992" y1="368" y2="416" x1="992" />
BEGIN BRANCH NDEV_SEL </branch>
WIRE 320 304 1408 304 <instance x="992" y="768" name="XLXI_16" orien="R0" />
WIRE 1408 304 1424 304 <instance x="1088" y="1056" name="XLXI_18" orien="R0" />
END BRANCH <instance x="1088" y="1200" name="XLXI_19" orien="R0" />
IOMARKER 320 304 NDEV_SEL R180 28 <instance x="1088" y="1344" name="XLXI_20" orien="R0" />
END SHEET <iomarker fontsize="28" x="1664" y="960" name="B10" orien="R0" />
END SCHEMATIC <iomarker fontsize="28" x="1664" y="1104" name="B9" orien="R0" />
<iomarker fontsize="28" x="1664" y="1248" name="B8" orien="R0" />
<instance x="1424" y="432" name="XLXI_32" orien="R0" />
<branch name="XLXN_47">
<wire x2="1392" y1="512" y2="512" x1="1376" />
<wire x2="1424" y1="368" y2="368" x1="1392" />
<wire x2="1392" y1="368" y2="512" x1="1392" />
</branch>
<branch name="NDEV_SEL">
<wire x2="1424" y1="304" y2="304" x1="320" />
</branch>
<iomarker fontsize="28" x="320" y="304" name="NDEV_SEL" orien="R180" />
<instance x="352" y="272" name="XLXI_33" orien="R0" />
<branch name="NOE">
<wire x2="2016" y1="272" y2="272" x1="2000" />
</branch>
<branch name="XLXN_53">
<wire x2="1744" y1="240" y2="240" x1="576" />
</branch>
<branch name="RNW">
<wire x2="352" y1="240" y2="240" x1="320" />
</branch>
<iomarker fontsize="28" x="320" y="240" name="RNW" orien="R180" />
<instance x="1744" y="368" name="XLXI_34" orien="R0" />
<branch name="XLXN_55">
<wire x2="1696" y1="336" y2="336" x1="1680" />
<wire x2="1744" y1="304" y2="304" x1="1696" />
<wire x2="1696" y1="304" y2="336" x1="1696" />
</branch>
<iomarker fontsize="28" x="2016" y="272" name="NOE" orien="R0" />
</sheet>
</drawing>

1012
VHDL/AppleIISd.jed
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4
VHDL/AppleIISd.ucf
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@ -18,14 +18,14 @@ NET "data<4>" LOC = "P7" ;
NET "data<5>" LOC = "P9" ; NET "data<5>" LOC = "P9" ;
NET "data<6>" LOC = "P11" ; NET "data<6>" LOC = "P11" ;
NET "data<7>" LOC = "P13" ; NET "data<7>" LOC = "P13" ;
NET "extclk" LOC = "P43" ; NET "clk_7m" LOC = "P43" ;
NET "led" LOC = "P29" ; NET "led" LOC = "P29" ;
NET "ndev_sel" LOC = "P24" ; NET "ndev_sel" LOC = "P24" ;
NET "ng" LOC = "P12" ; NET "ng" LOC = "P12" ;
NET "nio_sel" LOC = "P14" ; NET "nio_sel" LOC = "P14" ;
NET "nio_stb" LOC = "P42" ; NET "nio_stb" LOC = "P42" ;
NET "noe" LOC = "P25" ; NET "noe" LOC = "P25" ;
NET "nphi2" LOC = "P8" ; NET "clk_phi0" LOC = "P8" ;
NET "nreset" LOC = "P20" ; NET "nreset" LOC = "P20" ;
NET "nrw" LOC = "P1" ; NET "nrw" LOC = "P1" ;
NET "spi_miso" LOC = "P40" ; NET "spi_miso" LOC = "P40" ;

110
VHDL/AppleIISd.vhd
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@ -38,12 +38,11 @@ entity AppleIISd is
Port ( Port (
data : inout STD_LOGIC_VECTOR (7 downto 0); data : inout STD_LOGIC_VECTOR (7 downto 0);
nrw : in STD_LOGIC; nrw : in STD_LOGIC;
nirq : out STD_LOGIC;
nreset : in STD_LOGIC; nreset : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (1 downto 0); addr : in STD_LOGIC_VECTOR (1 downto 0);
nphi2 : in STD_LOGIC; clk_phi0 : in STD_LOGIC;
ndev_sel : in STD_LOGIC; ndev_sel : in STD_LOGIC;
extclk : in STD_LOGIC; clk_7m : in STD_LOGIC;
spi_miso: in std_logic; spi_miso: in std_logic;
spi_mosi : out STD_LOGIC; spi_mosi : out STD_LOGIC;
spi_sclk : out STD_LOGIC; spi_sclk : out STD_LOGIC;
@ -73,7 +72,6 @@ architecture Behavioral of AppleIISd is
-- interface signals -- interface signals
signal selected: std_logic; signal selected: std_logic;
signal reset: std_logic; signal reset: std_logic;
signal int_out: std_logic;
signal is_read: std_logic; signal is_read: std_logic;
signal int_din: std_logic_vector (7 downto 0); signal int_din: std_logic_vector (7 downto 0);
signal int_dout: std_logic_vector (7 downto 0); signal int_dout: std_logic_vector (7 downto 0);
@ -86,16 +84,11 @@ architecture Behavioral of AppleIISd is
-- internal state -- internal state
signal spidatain: std_logic_vector (7 downto 0); signal spidatain: std_logic_vector (7 downto 0);
signal spidataout: std_logic_vector (7 downto 0); signal spidataout: std_logic_vector (7 downto 0);
signal spiint: std_logic; -- spi interrupt state
signal inited: std_logic; -- card initialized signal inited: std_logic; -- card initialized
signal inited_set: std_logic; signal inited_set: std_logic;
signal inited_reset: std_logic;
signal inited_int: std_logic;
signal inited_intff: std_logic;
-- spi register flags -- spi register flags
signal tc: std_logic; -- transmission complete; cleared on spi data read signal tc: std_logic; -- transmission complete; cleared on spi data read
signal ier: std_logic; -- enable general SPI interrupts
signal bsy: std_logic; -- SPI busy signal bsy: std_logic; -- SPI busy
signal frx: std_logic; -- fast receive mode signal frx: std_logic; -- fast receive mode
signal tmo: std_logic; -- tri-state mosi signal tmo: std_logic; -- tri-state mosi
@ -104,9 +97,7 @@ architecture Behavioral of AppleIISd is
signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0); signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
signal slavesel: std_logic; -- slave select output (0=selected) signal slavesel: std_logic; -- slave select output (0=selected)
signal slaveinten: std_logic; -- slave interrupt enable (1=enabled)
-------------------------- --------------------------
-- helper signals -- helper signals
@ -118,7 +109,7 @@ architecture Behavioral of AppleIISd is
signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit) signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
-- spi clock -- spi clock
signal clksrc: std_logic; -- clock source (phi2 or extclk) signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
-- TODO divcnt is not used at all?? -- TODO divcnt is not used at all??
signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
signal shiftclk : std_logic; signal shiftclk : std_logic;
@ -132,6 +123,7 @@ architecture Behavioral of AppleIISd is
NDEV_SEL : in std_logic; NDEV_SEL : in std_logic;
NIO_SEL : in std_logic; NIO_SEL : in std_logic;
NIO_STB : in std_logic; NIO_STB : in std_logic;
RNW : in std_logic;
B8 : out std_logic; B8 : out std_logic;
B9 : out std_logic; B9 : out std_logic;
B10 : out std_logic; B10 : out std_logic;
@ -139,44 +131,36 @@ architecture Behavioral of AppleIISd is
); );
end component; end component;
component SR_Latch
port (
S,R : in std_logic;
Q, Q_n : inout std_logic;
Reset : in std_logic;
Clk : in std_logic
);
end component;
begin begin
add_dec : AddressDecoder add_dec : AddressDecoder
port map ( port map (
A8 => a8, A8 => a8,
A9 => a9, A9 => a9,
A10 => a10, A10 => a10,
CLK => extclk, CLK => clk_7m,
NDEV_SEL => ndev_sel, NDEV_SEL => ndev_sel,
NIO_SEL => nio_sel, NIO_SEL => nio_sel,
NIO_STB => nio_stb, NIO_STB => nio_stb,
RNW => nrw,
B8 => b8, B8 => b8,
B9 => b9, B9 => b9,
B10 => b10, B10 => b10,
NOE => noe); NOE => noe);
sr_inited : SR_Latch led <= not (inited_set);
port map ( --led <= not (bsy or not slavesel);
S => inited_set,
R => inited_reset,
Q => inited,
Q_n => open,
Reset => reset,
Clk => extclk);
led <= not (bsy or not slavesel);
ng <= ndev_sel and nio_sel and nio_stb; ng <= ndev_sel and nio_sel and nio_stb;
inited_reset <= card;
bsy <= start_shifting or shifting2; bsy <= start_shifting or shifting2;
process(clk_7m, reset, card, inited_set)
begin
if(reset = '1' or card = '1') then
inited <= '0';
elsif rising_edge(inited_set) then
inited <= '1';
end if;
end process;
process(start_shifting, shiftdone, shiftclk) process(start_shifting, shiftdone, shiftclk)
begin begin
if (rising_edge(shiftclk)) then if (rising_edge(shiftclk)) then
@ -275,7 +259,7 @@ begin
-------------------------- --------------------------
-- spiclk - spi clock generation -- spiclk - spi clock generation
-- spiclk is still 2 times the freq. than sclk -- spiclk is still 2 times the freq. than sclk
clksrc <= nphi2 when (ece = '0') else extclk; clksrc <= clk_phi0 when (ece = '0') else clk_7m;
-- is a pulse signal to allow for divisor==0 -- is a pulse signal to allow for divisor==0
--shiftclk <= clksrc when divcnt = "000000" else '0'; --shiftclk <= clksrc when divcnt = "000000" else '0';
@ -294,27 +278,30 @@ begin
end if; end if;
end process; end process;
--------------------------
-- interrupt generation
int_out <= spiint and slaveinten;
-------------------------- --------------------------
-- interface section -- interface section
-- inputs -- inputs
reset <= not (nreset); reset <= not (nreset);
selected <= not(ndev_sel); selected <= not(ndev_sel);
is_read <= selected and nphi2 and nrw;
int_din <= data; int_din <= data;
int_miso <= (spi_miso and not slavesel); int_miso <= (spi_miso and not slavesel);
process(selected, clk_7m)
begin
if(selected = '0') then
is_read <= '0';
elsif(rising_edge(clk_7m) and selected = '1' and clk_phi0 = '1' and nrw = '1') then
is_read <= '1';
end if;
end process;
-- outputs -- outputs
data <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate data <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
nirq <= '0' when (int_out='1') else 'Z'; -- wired-or
spi_sclk <= int_sclk; spi_sclk <= int_sclk;
spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state
spi_Nsel <= slavesel; spi_Nsel <= slavesel;
tc_proc: process (selected, shiftdone) tc_proc: process (selected, shiftdone)
begin begin
if (shiftdone = '1') then if (shiftdone = '1') then
@ -324,29 +311,12 @@ begin
end if; end if;
end process; end process;
spiint <= tc and ier;
-- inited_set pulse
process(extclk, reset)
begin
if(reset = '1') then
inited_set <= '0';
elsif falling_edge(extclk) then
inited_intff <= inited_int; -- one cycle delayed version
inited_set <= '0'; -- default value
if (inited_int = '1') and (inited_intff = '0') then
inited_set <= '1';
end if;
end if;
end process;
-------------------------- --------------------------
-- cpu register section -- cpu register section
-- cpu read -- cpu read
cpu_read: process (is_read, addr, cpu_read: process (is_read, addr,
spidatain, tc, ier, bsy, frx, tmo, ece, cpol, cpha, divisor, spidatain, tc, bsy, frx, tmo, ece, cpol, cpha, divisor,
slavesel, slaveinten, wp, card, inited) slavesel, wp, card, inited)
begin begin
if (is_read = '1') then if (is_read = '1') then
case addr is case addr is
@ -359,15 +329,14 @@ begin
int_dout(3) <= tmo; int_dout(3) <= tmo;
int_dout(4) <= frx; int_dout(4) <= frx;
int_dout(5) <= bsy; int_dout(5) <= bsy;
int_dout(6) <= ier; int_dout(6) <= '0';
int_dout(7) <= tc; int_dout(7) <= tc;
when "10" => -- read sclk divisor when "10" => -- read sclk divisor
int_dout(DIV_WIDTH-1 downto 0) <= divisor; int_dout(DIV_WIDTH-1 downto 0) <= divisor;
int_dout(7 downto 3) <= (others => '0'); int_dout(7 downto 3) <= (others => '0');
when "11" => -- read slave select / slave interrupt state when "11" => -- read slave select / slave interrupt state
int_dout(0) <= slavesel; int_dout(0) <= slavesel;
int_dout(3 downto 1) <= (others => '0'); int_dout(4 downto 1) <= (others => '0');
int_dout(4) <= slaveinten;
int_dout(5) <= wp; int_dout(5) <= wp;
int_dout(6) <= card; int_dout(6) <= card;
int_dout(7) <= inited; int_dout(7) <= inited;
@ -380,7 +349,7 @@ begin
end process; end process;
-- cpu write -- cpu write
cpu_write: process(reset, selected, nrw, addr, int_din) cpu_write: process(reset, selected, nrw, addr, int_din, card, inited)
begin begin
if (reset = '1') then if (reset = '1') then
cpha <= '0'; cpha <= '0';
@ -388,11 +357,12 @@ begin
ece <= '0'; ece <= '0';
tmo <= '0'; tmo <= '0';
frx <= '0'; frx <= '0';
ier <= '0';
slavesel <= '1'; slavesel <= '1';
slaveinten <= '0';
divisor <= (others => '0'); divisor <= (others => '0');
spidataout <= (others => '1'); spidataout <= (others => '1');
inited_set <= '0';
elsif (card = '1') then
inited_set <= '0';
elsif (falling_edge(selected) and nrw = '0') then elsif (falling_edge(selected) and nrw = '0') then
case addr is case addr is
when "00" => -- write SPI data out (see other process above) when "00" => -- write SPI data out (see other process above)
@ -403,15 +373,13 @@ begin
ece <= int_din(2); ece <= int_din(2);
tmo <= int_din(3); tmo <= int_din(3);
frx <= int_din(4); frx <= int_din(4);
-- no bit 5 -- no bit 5 - 7
ier <= int_din(6);
-- no bit 7;
when "10" => -- write divisor when "10" => -- write divisor
divisor <= int_din(DIV_WIDTH-1 downto 0); divisor <= int_din(DIV_WIDTH-1 downto 0);
when "11" => -- write slave select / slave interrupt enable when "11" => -- write slave select / slave interrupt enable
slavesel <= int_din(0); slavesel <= int_din(0);
slaveinten <= int_din(4); -- no bit 1 - 6
inited_int <= int_din(7); inited_set <= int_din(7);
when others => when others =>
end case; end case;
end if; end if;

15
VHDL/AppleIISd.xise
View File

@ -17,19 +17,15 @@
<files> <files>
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC"> <file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="sr_latch.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
</files> </files>
<properties> <properties>
@ -59,6 +55,7 @@
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/> <property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
@ -127,6 +124,7 @@
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
@ -138,7 +136,8 @@
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/SR_Latch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SR_Latch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
@ -148,7 +147,7 @@
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SR_Latch" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>

55
VHDL/sr_latch.vhd
View File

@ -1,55 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:26:04 09/09/2017
-- Design Name:
-- Module Name: sr_latch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SR_Latch is
Port ( S,R : in STD_LOGIC;
Q : inout STD_LOGIC;
Q_n : inout STD_LOGIC;
Reset : in STD_LOGIC;
Clk : in STD_LOGIC);
end SR_Latch;
architecture SR_Latch_arch of SR_Latch is
begin
process (S,R,Q,Q_n, Reset, Clk)
begin
if(rising_edge(Clk)) then
if(Reset = '1') then
Q <= '0';
Q_n <= '1';
else
Q <= R NOR Q_n;
Q_n <= S NOR Q;
end if;
end if;
end process;
end SR_Latch_arch;