Release 6.3.03i - xst G.38 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s --> Reading design: spi6502b.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : spi6502b.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : spi6502b Output Format : NGC Target Device : xc9500xl ---- Source Options Top Module Name : spi6502b Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES Equivalent register Removal : YES MACRO Preserve : YES XOR Preserve : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : YES RTL Output : Yes Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain ---- Other Options lso : spi6502b.lso verilog2001 : YES Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/sources/AppleIISd/address_decoder.vhf in Library work. Architecture behavioral of Entity fd_mxilinx_address_decoder is up to date. Architecture behavioral of Entity fdrs_mxilinx_address_decoder is up to date. Architecture behavioral of Entity address_decoder is up to date. Compiling vhdl file C:/sources/AppleIISd/SPI6502B1.1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 240: Mux is complete : default of case is discarded INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 353: Mux is complete : default of case is discarded Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set user-defined property "HU_SET = XLXI_16_1" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set user-defined property "HU_SET = U0_0" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/sources/AppleIISd/address_decoder.vhf. Unit synthesized. Synthesizing Unit . Related source file is C:/sources/AppleIISd/address_decoder.vhf. Unit synthesized. Synthesizing Unit . Related source file is C:/sources/AppleIISd/address_decoder.vhf. Unit synthesized. Synthesizing Unit . Related source file is C:/sources/AppleIISd/SPI6502B1.1.vhd. Found 8-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit tristate buffer for signal . Found 1-bit xor3 for signal <$n0040> created at line 243. Found 4-bit adder for signal <$n0047> created at line 197. Found 1-bit register for signal . Found 1-bit register for signal . Found 3-bit down counter for signal . Found 3-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 24 1-bit 2-to-1 multiplexers. Summary: inferred 1 Counter(s). inferred 20 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 10 Tristate(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 4-bit adder : 1 # Registers : 25 1-bit register : 22 8-bit register : 1 3-bit register : 1 4-bit register : 1 # Multiplexers : 12 2-to-1 multiplexer : 12 # Tristates : 3 1-bit tristate buffer : 2 8-bit tristate buffer : 1 # Xors : 1 1-bit xor3 : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : spi6502b.ngr Top Level Output File Name : spi6502b Output Format : NGC Optimization Goal : Speed Keep Hierarchy : YES Target Technology : xc9500xl Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 32 Macro Statistics : # Registers : 60 # 1-bit register : 60 # Tristates : 3 # 1-bit tristate buffer : 2 # 8-bit tristate buffer : 1 # Xors : 5 # 1-bit xor2 : 5 Cell Usage : # BELS : 256 # AND2 : 120 # AND3 : 6 # AND4 : 1 # GND : 2 # INV : 76 # OR2 : 43 # OR3 : 1 # VCC : 2 # XOR2 : 5 # FlipFlops/Latches : 38 # FD : 1 # FDC : 5 # FDCE : 27 # FDCP : 2 # FDP : 1 # FDPE : 2 # IO Buffers : 32 # IBUF : 14 # IOBUFE : 8 # OBUF : 8 # OBUFE : 2 # Others : 5 # AND2B1 : 2 # AND4B1 : 1 # NAND2 : 2 ========================================================================= CPU : 1.05 / 1.48 s | Elapsed : 1.00 / 1.00 s --> Total memory usage is 69656 kilobytes