117 lines
3.8 KiB
VHDL
117 lines
3.8 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 22:03:22 10/10/2017
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-- Design Name:
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-- Module Name: AddressDecoder - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity AddressDecoder is
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Port ( A : in std_logic_vector (11 downto 8);
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B : out std_logic_vector (10 downto 8); -- to EEPROM
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CLK : in std_logic;
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PHI0 : in std_logic;
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RNW : in std_logic;
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NDEV_SEL : in std_logic; -- $C0n0 - $C0nF, CPLD registers
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NIO_SEL : in std_logic; -- $Cs00 - $CsFF, EEPROM bank 0
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NIO_STB : in std_logic; -- $C800 - $CFFF, EEPROM banks 1 to 7
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NRESET : in std_logic;
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DATA_EN : out std_logic; -- to CPLD
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PGM_EN : in std_logic; -- from CPLD;
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NG : out std_logic; -- to bus transceiver
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NOE : out std_logic; -- to EEPROM
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NWE : out std_logic); -- to EEPROM
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end AddressDecoder;
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architecture Behavioral of AddressDecoder is
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signal cfxx : std_logic; -- $C800 - $CFFF disable
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signal ndev_sel_int : std_logic;
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signal nio_sel_int : std_logic;
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signal nio_stb_int : std_logic;
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signal ncs : std_logic; -- $C800 - $CFFE enabled
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signal a_int : std_logic_vector (11 downto 8);
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begin
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-- According to Apple IIgs Tech Note #68
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-- in order to prevent bus fights with video data,
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-- data from peripheral to CPU shall be valid on the bus
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-- only from the first rising edge of 7M when any select
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-- line is low (Phi0 high) to the falling edge of Phi0
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-- $C0xx to $C7xx is mapped to EEPROM bank 0
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-- $C8xx to $CExx is mapped to banks 1 to 7
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B(8) <= (a_int(11) and not a_int(8))
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or (a_int(11) and a_int(10) and a_int(9));
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B(9) <= (a_int(11) and not a_int(9) and a_int(8))
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or (a_int(11) and a_int(9) and not a_int(8))
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or (a_int(11) and a_int(10) and a_int(9));
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B(10) <= (a_int(11) and a_int(10))
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or (a_int(11) and a_int(9) and a_int(8));
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DATA_EN <= RNW and not NDEV_SEL;
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NG <= (ndev_sel_int and nio_sel_int and nio_stb_int)
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or (ndev_sel_int and nio_sel_int and ncs)
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or not PHI0;
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NOE <= not RNW
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or (not NIO_SEL and not NIO_STB)
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or (NIO_SEL and NIO_STB)
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or (NIO_SEL and ncs);
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NWE <= RNW
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or (not NIO_SEL and not NIO_STB)
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or (NIO_SEL and NIO_STB)
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or (NIO_SEL and ncs)
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or not PGM_EN;
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cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;
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process(NRESET, nio_sel_int, cfxx)
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begin
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if (NRESET = '0' or cfxx = '1') then
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ncs <= '1';
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elsif falling_edge(nio_sel_int) then
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ncs <= '0';
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end if;
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end process;
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process(NRESET, CLK)
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begin
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if(NRESET = '0') then
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ndev_sel_int <= '1';
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nio_sel_int <= '1';
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nio_stb_int <= '1';
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a_int <= "0000";
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elsif rising_edge(CLK) then
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ndev_sel_int <= NDEV_SEL;
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nio_sel_int <= NIO_SEL;
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nio_stb_int <= NIO_STB;
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a_int <= A;
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end if;
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end process;
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end Behavioral;
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