358 lines
9.7 KiB
VHDL
358 lines
9.7 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 00:42:59 10/10/2017
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-- Design Name:
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-- Module Name: U:/AppleIISd/VHDL/IO_Test.vhd
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-- Project Name: AppleIISd
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: IO
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY AppleIISd_Test IS
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END AppleIISd_Test;
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ARCHITECTURE behavior OF AppleIISd_Test IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT AppleIISd
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PORT(
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ADD_HIGH : IN std_logic_vector(11 downto 8);
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ADD_LOW : IN std_logic_vector(1 downto 0);
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B : OUT std_logic_vector(10 downto 8);
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CARD : IN std_logic;
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DATA : INOUT std_logic_vector(7 downto 0);
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CLK : IN std_logic;
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LED : OUT std_logic;
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NDEV_SEL : IN std_logic;
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NG : OUT std_logic;
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NIO_SEL : IN std_logic;
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NIO_STB : IN std_logic;
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NOE : OUT std_logic;
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PHI0 : IN std_logic;
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NRESET : IN std_logic;
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RNW : IN std_logic;
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MISO : IN std_logic;
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MOSI : OUT std_logic;
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NSEL : OUT std_logic;
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SCLK : OUT std_logic;
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WP : IN std_logic;
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data_dbg : out std_logic_vector (7 downto 0);
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add_dbg : out std_logic_vector (1 downto 0);
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data_en_dbg : out std_logic
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);
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END COMPONENT;
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--Inputs
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signal ADD_HIGH : std_logic_vector(11 downto 8) := (others => '0');
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signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U');
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signal CARD : std_logic := '0';
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signal CLK : std_logic := '0';
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signal NDEV_SEL : std_logic := '1';
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signal NIO_SEL : std_logic := '1';
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signal NIO_STB : std_logic := '1';
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signal PHI0 : std_logic := '1';
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signal NRESET : std_logic := '1';
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signal RNW : std_logic := '1';
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signal MISO : std_logic := '1';
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signal WP : std_logic := '0';
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--BiDirs
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signal DATA : std_logic_vector(7 downto 0) := (others => 'Z');
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--Outputs
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signal B : std_logic_vector(10 downto 8);
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signal LED : std_logic;
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signal NG : std_logic;
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signal NOE : std_logic;
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signal MOSI : std_logic;
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signal NSEL : std_logic;
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signal SCLK : std_logic;
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signal data_dbg : std_logic_vector (7 downto 0);
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signal add_dbg : std_logic_vector (1 downto 0);
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signal data_en_dbg : std_logic;
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-- Clock period definitions
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constant CLK_period : time := 142 ns;
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-- Bus timings
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-- worst case
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constant ADD_valid : time := 300 ns; -- II+
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constant DATA_valid : time := 200 ns; -- II+
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constant ADD_hold : time := 15 ns; -- IIgs
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--best case
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--constant ADD_valid : time := 100 ns; -- IIgs
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--constant DATA_valid : time := 30 ns; -- IIgs
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--constant ADD_hold : time := 15 ns; -- IIgs
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: AppleIISd PORT MAP (
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ADD_HIGH => ADD_HIGH,
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ADD_LOW => ADD_LOW,
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B => B,
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CARD => CARD,
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DATA => DATA,
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CLK => CLK,
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LED => LED,
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NDEV_SEL => NDEV_SEL,
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NG => NG,
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NIO_SEL => NIO_SEL,
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NIO_STB => NIO_STB,
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NOE => NOE,
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PHI0 => PHI0,
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NRESET => NRESET,
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RNW => RNW,
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MISO => MISO,
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MOSI => MOSI,
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NSEL => NSEL,
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SCLK => SCLK,
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WP => WP,
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data_dbg => data_dbg,
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add_dbg => add_dbg,
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data_en_dbg => data_en_dbg
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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PHI0_process :process(CLK)
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variable counter : integer range 0 to 7;
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begin
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if rising_edge(CLK) or falling_edge(CLK) then
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counter := counter + 1;
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if counter = 7 then
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PHI0 <= not PHI0;
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counter := 0;
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end if;
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end if;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state.
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wait for CLK_period * 10;
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NRESET <= '0';
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wait for CLK_period * 20;
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NRESET <= '1';
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wait for CLK_period * 10;
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DATA <= (others => 'Z');
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ADD_LOW <= (others => 'U');
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-- read reg 3
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '1');
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RNW <= '1';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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DATA <= (others => 'Z');
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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wait for ADD_hold;
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ADD_LOW <= (others => 'U');
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-- select card
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '1');
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RNW <= '0';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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DATA <= (others => 'Z');
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wait for DATA_valid;
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DATA <= X"00";
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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wait for ADD_hold;
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--wait for CLK_period;
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ADD_LOW <= (others => 'U');
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RNW <= '1';
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DATA <= (others => 'Z');
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-- send data
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '0');
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RNW <= '0';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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DATA <= (others => 'Z');
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wait for DATA_valid;
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DATA <= X"AA";
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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wait for ADD_hold;
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--wait for CLK_period;
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ADD_LOW <= (others => 'U');
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RNW <= '1';
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DATA <= (others => 'Z');
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wait for 20 us;
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-- deselect card
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '1');
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RNW <= '0';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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DATA <= (others => 'Z');
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wait for DATA_valid;
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DATA <= X"01";
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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wait for ADD_hold;
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--wait for CLK_period;
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ADD_LOW <= (others => 'U');
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RNW <= '1';
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DATA <= (others => 'Z');
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-- write ece
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= "01";
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RNW <= '0';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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DATA <= (others => 'Z');
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wait for DATA_valid;
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DATA <= x"04";
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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wait for ADD_hold;
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--wait for CLK_period;
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ADD_LOW <= (others => 'U');
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RNW <= '1';
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DATA <= (others => 'Z');
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-- send data
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '0');
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RNW <= '0';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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DATA <= (others => 'Z');
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wait for DATA_valid;
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DATA <= X"AA";
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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wait for ADD_hold;
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--wait for CLK_period;
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ADD_LOW <= (others => 'U');
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RNW <= '1';
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DATA <= (others => 'Z');
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-- read eprom low
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wait for 3 us;
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '0');
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ADD_HIGH <= "0100"; -- must become "111"
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RNW <= '1';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NIO_SEL <= '0';
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DATA <= (others => 'Z');
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wait until falling_edge(PHI0);
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NIO_SEL <= '1';
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wait for ADD_hold;
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ADD_LOW <= (others => 'U');
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ADD_HIGH <= (others => 'U');
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-- read eprom high, selected
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '0');
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ADD_HIGH <= "1001"; -- must become "001"
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RNW <= '1';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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DATA <= (others => 'Z');
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait for ADD_hold;
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ADD_LOW <= (others => 'U');
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ADD_HIGH <= (others => 'U');
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-- read $CFFF
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '1');
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ADD_HIGH <= "1111";
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RNW <= '1';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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DATA <= (others => 'Z');
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait for ADD_hold;
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ADD_LOW <= (others => 'U');
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ADD_HIGH <= (others => 'U');
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-- read eprom high, deselected
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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ADD_LOW <= (others => '0');
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ADD_HIGH <= "1101"; -- must become "101"
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RNW <= '1';
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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DATA <= (others => 'Z');
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait for ADD_hold;
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ADD_LOW <= (others => 'U');
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ADD_HIGH <= (others => 'U');
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wait;
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end process;
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END;
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