AppleIISd/VHDL/SPI6502B.ucf

35 lines
930 B
Plaintext

#net "diag" loc="P29";
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "cpu_a<0>" LOC = "P22" ;
NET "cpu_a<1>" LOC = "P24" ;
NET "cpu_d<0>" LOC = "P2" ;
NET "cpu_d<1>" LOC = "P3" ;
NET "cpu_d<2>" LOC = "P4" ;
NET "cpu_d<3>" LOC = "P8" ;
NET "cpu_d<4>" LOC = "P9" ;
NET "cpu_d<5>" LOC = "P11" ;
NET "cpu_d<6>" LOC = "P12" ;
NET "cpu_d<7>" LOC = "P13" ;
NET "cpu_Nirq" LOC = "P14" ;
NET "cpu_Nphi2" LOC = "P5" ;
NET "cpu_Nres" LOC = "P19" ;
NET "cpu_rnw" LOC = "P7" ;
NET "cs1" LOC = "P20" ;
NET "led" LOC = "P29" ;
NET "extclk" LOC = "P6" ;
NET "Ncs2" LOC = "P18" ;
NET "spi_int" LOC = "P42" ;
NET "spi_miso" LOC = "P44" ;
NET "spi_mosi" LOC = "P35" ;
NET "spi_Nsel" LOC = "P28" ;
NET "spi_sclk" LOC = "P34" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE