364 lines
10 KiB
VHDL
364 lines
10 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company: n/a
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-- Engineer: A. Fachat
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--
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-- Create Date: 12:37:11 05/07/2011
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-- Design Name: SPI65B
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-- Module Name: SPI6502B - Behavioral
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-- Project Name: CS/A NETUSB 2.0
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-- Target Devices: CS/A NETUSB 2.0
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-- Tool versions:
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-- Description: An SPI interface for 6502-based computers (or compatible).
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-- modelled after the SPI65 interface by Daryl Rictor
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-- (see http://sbc.rictor.org/io/65spi.html )
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-- This implementation here, however, is a complete reimplementation
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-- as the ABEL language of the original implementation is not supported
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-- by ISE anymore.
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-- Also I added the interrupt input handling, replacing four of the
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-- original SPI select outputs with four interrupt inputs
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-- Also folded out the single MISO input into one input for each of the
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-- four supported devices, reducing external parts count again by one.
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination,
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-- to drive up SPI clock to half of input clock (and not one fourth only as before)
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-- unfortunately that costed one divisor bit to fit into the CPLD
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity SPI6502B is
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Port ( cpu_d : inout STD_LOGIC_VECTOR (7 downto 0);
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cpu_rnw : in STD_LOGIC;
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cpu_Nirq : out STD_LOGIC;
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cpu_Nres : in STD_LOGIC;
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cpu_a : in STD_LOGIC_VECTOR (1 downto 0);
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cpu_Nphi2 : in STD_LOGIC;
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cs1 : in STD_LOGIC;
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Ncs2 : in STD_LOGIC;
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extclk : in STD_LOGIC;
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spi_miso: in std_logic;
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spi_mosi : out STD_LOGIC;
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spi_sclk : out STD_LOGIC;
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spi_Nsel : out STD_LOGIC;
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spi_int : in STD_LOGIC;
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led : out std_logic
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);
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constant DIV_WIDTH : integer := 3;
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end SPI6502B;
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architecture Behavioral of SPI6502B is
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-- interface signals
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signal selected: std_logic;
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signal reset: std_logic;
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signal int_out: std_logic;
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signal is_read: std_logic;
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signal int_din: std_logic_vector (7 downto 0);
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signal int_dout: std_logic_vector (7 downto 0);
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signal int_mosi: std_logic;
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signal int_miso: std_logic;
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signal int_sclk: std_logic;
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--------------------------
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-- internal state
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signal spidatain: std_logic_vector (7 downto 0);
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signal spidataout: std_logic_vector (7 downto 0);
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signal spiint: std_logic; -- spi interrupt state
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-- spi register flags
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signal tc: std_logic; -- transmission complete; cleared on spi data read
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signal ier: std_logic; -- enable general SPI interrupts
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signal bsy: std_logic; -- SPI busy
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signal frx: std_logic; -- fast receive mode
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signal tmo: std_logic; -- tri-state mosi
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signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
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signal cpol: std_logic; -- shift clock polarity; 0=rising edge, 1=falling edge
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signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge
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signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
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signal slavesel: std_logic; -- slave select output (0=selected)
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signal slaveinten: std_logic; -- slave interrupt enable (1=enabled)
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signal slaveint: std_logic; -- slave interrupt inputs
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--------------------------
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-- helper signals
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-- shift engine
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signal start_shifting: std_logic; -- shifting data
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signal shifting2: std_logic; -- shifting data
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signal shiftdone: std_logic; -- shifting data done
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signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
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-- spi clock
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signal clksrc: std_logic; -- clock source (phi2 or extclk)
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signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
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signal shiftclk : std_logic;
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begin
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led <= not (bsy or not slavesel); --'0'; --shifting2; --shiftdone; --shiftcnt(2);
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--------------------------
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bsy <= start_shifting or shifting2;
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process(start_shifting, shiftdone, shiftclk)
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begin
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if (rising_edge(shiftclk)) then
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if (shiftdone = '1') then
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shifting2 <= '0';
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else
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shifting2 <= start_shifting;
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end if;
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end if;
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end process;
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process(shiftcnt, reset, shiftclk)
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begin
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if (reset = '1') then
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shiftdone <= '0';
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elsif (rising_edge(shiftclk)) then
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if (shiftcnt = "1111") then
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shiftdone <= '1';
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else
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shiftdone <= '0';
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end if;
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end if;
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end process;
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process(reset, shifting2, shiftcnt, shiftclk)
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begin
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if (reset='1') then
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shiftcnt <= (others => '0');
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elsif (rising_edge(shiftclk)) then
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if (shifting2 = '1') then
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-- count phase
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shiftcnt <= shiftcnt + 1;
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else
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shiftcnt <= (others => '0');
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end if;
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end if;
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end process;
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inproc: process(reset, shifting2,
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shiftcnt, shiftclk, spidatain, int_miso)
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begin
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if (reset='1') then
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spidatain <= (others => '0');
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elsif (rising_edge(shiftclk)) then
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if (shifting2 = '1' and shiftcnt(0) = '1') then
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-- shift in to input register
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spidatain (7 downto 1) <= spidatain (6 downto 0);
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spidatain (0) <= int_miso;
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end if;
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end if;
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end process;
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outproc: process(reset, shifting2, spidataout, cpol, cpha,
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shiftcnt, shiftclk)
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begin
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if (reset='1') then
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int_mosi <= '1';
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int_sclk <= cpol;
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else
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-- clock is sync'd
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if (rising_edge(shiftclk)) then
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if (shifting2='0' or shiftdone = '1') then
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int_mosi <= '1';
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int_sclk <= cpol;
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else
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-- output data directly from output register
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case shiftcnt(3 downto 1) is
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when "000" => int_mosi <= spidataout(7);
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when "001" => int_mosi <= spidataout(6);
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when "010" => int_mosi <= spidataout(5);
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when "011" => int_mosi <= spidataout(4);
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when "100" => int_mosi <= spidataout(3);
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when "101" => int_mosi <= spidataout(2);
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when "110" => int_mosi <= spidataout(1);
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when "111" => int_mosi <= spidataout(0);
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when others => int_mosi <= '1';
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end case;
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int_sclk <= cpol xor cpha xor shiftcnt(0);
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end if;
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end if;
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end if;
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end process;
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-- shift operation enable
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shiften: process(reset, selected, cpu_rnw, cpu_a, frx, shiftdone)
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begin
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-- start shifting
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if (reset='1' or shiftdone='1') then
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start_shifting <= '0';
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elsif (falling_edge(selected) and cpu_a="00" and (frx='1' or cpu_rnw='0')) then
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-- access to register 00, either write (cpu_rnw=0) or fast receive bit set (frx)
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-- then both types of access (write but also read)
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start_shifting <= '1';
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end if;
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end process;
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--------------------------
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-- spiclk - spi clock generation
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-- spiclk is still 2 times the freq. than sclk
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clksrc <= cpu_Nphi2 when (ece = '0') else extclk;
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-- is a pulse signal to allow for divisor==0
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--shiftclk <= clksrc when divcnt = "000000" else '0';
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shiftclk <= clksrc when bsy = '1' else '0';
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clkgen: process(reset, divisor, clksrc)
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begin
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if (reset='1') then
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divcnt <= divisor;
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--spiclk <= '0';
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elsif (falling_edge(clksrc)) then
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if (shiftclk = '1') then
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divcnt <= divisor;
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--spiclk <= not(spiclk);
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else
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divcnt <= divcnt - 1;
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end if;
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end if;
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end process;
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--------------------------
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-- interrupt generation
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int_out <= spiint
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or (slaveint and slaveinten);
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--------------------------
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-- interface section
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-- inputs
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reset <= not (cpu_Nres);
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selected <= cs1 and not(Ncs2); -- and cpu_phi2;
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is_read <= selected and cpu_Nphi2 and cpu_rnw;
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int_din <= cpu_d;
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slaveint <= not(spi_int); -- active low interrupt inputs
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int_miso <= (spi_miso and not slavesel);
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-- outputs
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cpu_d <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
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cpu_Nirq <= '0' when (int_out='1') else 'Z'; -- wired-or
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spi_sclk <= int_sclk;
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spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state
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spi_Nsel <= slavesel;
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tc_proc: process (selected, shiftdone)
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begin
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if (shiftdone = '1') then
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tc <= '1';
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elsif (falling_edge(selected) and cpu_a="00"
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--elsif (falling_edge(cpu_phi2) and selected='1' and cpu_a="00"
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--and cpu_rnw='1' -- both reads _and_ writes clear the interrupt
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) then
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tc <= '0';
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end if;
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end process;
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spiint <= tc and ier;
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--------------------------
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-- cpu register section
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-- cpu read
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cpu_read: process (is_read, cpu_a,
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spidatain, tc, ier, bsy, frx, tmo, ece, cpol, cpha, divisor,
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slavesel, slaveint, slaveinten)
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begin
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if (is_read = '1') then
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case cpu_a is
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when "00" => -- read SPI data in
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int_dout <= spidatain;
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when "01" => -- read status register
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int_dout(0) <= cpha;
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int_dout(1) <= cpol;
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int_dout(2) <= ece;
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int_dout(3) <= tmo;
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int_dout(4) <= frx;
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int_dout(5) <= bsy;
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int_dout(6) <= ier;
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int_dout(7) <= tc;
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when "10" => -- read sclk divisor
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int_dout(DIV_WIDTH-1 downto 0) <= divisor;
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int_dout(3) <= '0';
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int_dout(4) <= slaveint;
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int_dout(7 downto 5) <= (others => '0');
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when "11" => -- read slave select / slave interrupt state
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int_dout(0) <= slavesel;
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int_dout(3 downto 1) <= (others => '0');
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int_dout(4) <= slaveinten;
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int_dout(7 downto 5) <= (others => '0');
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when others =>
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int_dout <= (others => '0');
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end case;
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else
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int_dout <= (others => '0');
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end if;
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end process;
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-- cpu write
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cpu_write: process(reset, selected, cpu_rnw, cpu_a, int_din)
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begin
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if (reset = '1') then
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cpha <= '0';
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cpol <= '0';
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ece <= '0';
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tmo <= '0';
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frx <= '0';
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ier <= '0';
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slavesel <= '1';
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slaveinten <= '0';
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divisor <= (others => '0');
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elsif (falling_edge(selected) and cpu_rnw = '0') then
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--elsif (falling_edge(cpu_phi2) and selected='1' and cpu_rnw='0') then
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case cpu_a is
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when "00" => -- write SPI data out (see other process above)
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spidataout <= int_din;
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when "01" => -- write status register
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cpha <= int_din(0);
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cpol <= int_din(1);
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ece <= int_din(2);
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tmo <= int_din(3);
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frx <= int_din(4);
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-- no bit 5
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ier <= int_din(6);
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-- no bit 7;
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when "10" => -- write divisor
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divisor <= int_din(DIV_WIDTH-1 downto 0);
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when "11" => -- write slave select / slave interrupt enable
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slavesel <= int_din(0);
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slaveinten <= int_din(4);
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when others =>
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end case;
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end if;
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end process;
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end Behavioral;
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