4 lines
55 KiB
XML
4 lines
55 KiB
XML
<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE document SYSTEM "file:///C:/Xilinx/xc9500xl/data/xmlReport9kxl.dtd">
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<document><ascFile>spi6502b.rpt</ascFile><devFile>C:/Xilinx/xc9500xl/data/xc9572xl.chp</devFile><mfdFile>spi6502b.mfd</mfdFile><htmlFile logo="xc9500xl_logo.jpg" pin_legend="pinlegend.htm" logic_legend="logiclegend.htm"/><header pkg="PC44" date=" 5- 6-2017" time=" 5:47PM" speed="-10" design="spi6502b" device="XC9572XL" status="1" eqnType="1" version="1.0" statusStr="Successful" swVersion="G.38"/><inputs id="cpu_Nres"/><inputs id="cpu_rnw"/><inputs id="Ncs2"/><inputs id="cs1"/><inputs id="cpu_d0PIN_SPECSIG"/><inputs id="cpu_a0_SPECSIG"/><inputs id="cpu_a1_SPECSIG"/><inputs id="cpu_d1PIN_SPECSIG"/><inputs id="cpu_d2PIN_SPECSIG"/><inputs id="cpu_d4PIN_SPECSIG"/><inputs id="cpu_d6PIN_SPECSIG"/><inputs id="cpu_d3PIN_SPECSIG"/><inputs id="spi_miso"/><inputs id="cpu_Nphi2"/><inputs id="cpu_d5PIN_SPECSIG"/><inputs id="cpu_d7PIN_SPECSIG"/><inputs id="spi_int"/><inputs id="extclk"/><pin id="FB1_MC2_PIN1" use="b_SPECSIG" pinnum="1" signal="spidataout2_SPECSIG"/><pin id="FB1_MC5_PIN2" use="IO_SPECSIG" pinnum="2" signal="cpu_d0_SPECSIG"/><pin id="FB1_MC6_PIN3" use="IO_SPECSIG" pinnum="3" signal="cpu_d1_SPECSIG"/><pin id="FB1_MC8_PIN4" use="IO_SPECSIG" pinnum="4" signal="cpu_d2_SPECSIG"/><pin id="FB1_MC9_PIN5" use="I" pinnum="5" signal="cpu_Nphi2"/><pin id="FB1_MC11_PIN6" use="I" pinnum="6" signal="extclk"/><pin id="FB1_MC14_PIN7" use="I" pinnum="7" signal="cpu_rnw"/><pin id="FB1_MC15_PIN8" use="IO_SPECSIG" pinnum="8" signal="cpu_d3_SPECSIG"/><pin id="FB1_MC17_PIN9" use="IO_SPECSIG" pinnum="9" signal="cpu_d4_SPECSIG"/><pin id="FB2_MC2_PIN35" use="O" pinnum="35" signal="spi_mosi"/><pin id="FB2_MC5_PIN36" use="b_SPECSIG" pinnum="36" signal="shiftcnt0_SPECSIG"/><pin id="FB2_MC6_PIN37" use="b_SPECSIG" pinnum="37" signal="OpTxINV22__INT_SPECSIG"/><pin id="FB2_MC8_PIN38" use="b_SPECSIG" pinnum="38" signal="spidatain6_SPECSIG"/><pin id="FB2_MC9_PIN39" use="b_SPECSIG" pinnum="39" signal="spidatain5_SPECSIG"/><pin id="FB2_MC11_PIN40" use="b_SPECSIG" pinnum="40" signal="spidatain3_SPECSIG"/><pin id="FB2_MC14_PIN42" use="I" pinnum="42" signal="spi_int"/><pin id="FB2_MC15_PIN43" use="b_SPECSIG" pinnum="43" signal="shiftcnt3_SPECSIG"/><pin id="FB2_MC17_PIN44" use="I" pinnum="44" signal="spi_miso"/><pin id="FB3_MC2_PIN11" use="IO_SPECSIG" pinnum="11" signal="cpu_d5_SPECSIG"/><pin id="FB3_MC5_PIN12" use="IO_SPECSIG" pinnum="12" signal="cpu_d6_SPECSIG"/><pin id="FB3_MC8_PIN13" use="IO_SPECSIG" pinnum="13" signal="cpu_d7_SPECSIG"/><pin id="FB3_MC9_PIN14" use="O" pinnum="14" signal="cpu_Nirq"/><pin id="FB3_MC11_PIN18" use="I" pinnum="18" signal="Ncs2"/><pin id="FB3_MC14_PIN19" use="I" pinnum="19" signal="cpu_Nres"/><pin id="FB3_MC15_PIN20" use="I" pinnum="20" signal="cs1"/><pin id="FB3_MC16_PIN24" use="I" pinnum="24" signal="cpu_a1_SPECSIG"/><pin id="FB3_MC17_PIN22" use="I" pinnum="22" signal="cpu_a0_SPECSIG"/><pin id="FB4_MC2_PIN25" use="b_SPECSIG" pinnum="25" signal="tc"/><pin id="FB4_MC5_PIN26" use="b_SPECSIG" pinnum="26" signal="spidataout6_SPECSIG"/><pin id="FB4_MC8_PIN27" use="b_SPECSIG" pinnum="27" signal="spidataout3_SPECSIG"/><pin id="FB4_MC11_PIN28" use="O" pinnum="28" signal="spi_Nsel"/><pin id="FB4_MC14_PIN29" use="O" pinnum="29" signal="led"/><pin id="FB4_MC15_PIN33" pinnum="33"/><pin id="FB4_MC17_PIN34" use="O" pinnum="34" signal="spi_sclk"/><fblock id="FB1" pinUse="8" inputUse="31"><macrocell id="FB1_MC1"/><macrocell id="FB1_MC2" pin="FB1_MC2_PIN1" sigUse="8" signal="spidataout2_SPECSIG"><pterms pt1="FB1_2_1" pt2="FB1_2_2" pt3="FB1_2_3" pt4="FB1_2_4"/></macrocell><macrocell id="FB1_MC3" sigUse="8" signal="spidataout1_SPECSIG"><pterms pt1="FB1_3_1" pt2="FB1_3_2" pt3="FB1_3_3" pt4="FB1_3_4"/></macrocell><macrocell id="FB1_MC4" sigUse="8" signal="spidataout0_SPECSIG"><pterms pt1="FB1_4_1" pt2="FB1_4_2" pt3="FB1_4_3" pt4="FB1_4_4"/></macrocell><macrocell id="FB1_MC5" pin="FB1_MC5_PIN2" sigUse="10" signal="cpu_d0_SPECSIG"><pterms pt1="FB1_5_1" pt2="FB1_5_2" pt3="FB1_5_3" pt4="FB1_5_4" pt5="FB1_5_5"/></macrocell><macrocell id="FB1_MC6" pin="FB1_MC6_PIN3" sigUse="9" signal="cpu_d1_SPECSIG"><pterms pt1="FB1_6_1" pt2="FB1_6_2" pt3="FB1_6_3" pt4="FB1_6_4"/></macrocell><macrocell id="FB1_MC7" sigUse="8" signal="tmo"><pterms pt1="FB1_7_1" pt2="FB1_7_2" pt3="FB1_7_3" pt4="FB1_7_4" pt5="FB1_7_5"/></macrocell><macrocell id="FB1_MC8" pin="FB1_MC8_PIN4" sigUse="9" signal="cpu_d2_SPECSIG"><pterms pt1="FB1_8_1" pt2="FB1_8_2" pt3="FB1_8_3" pt4="FB1_8_4"/></macrocell><macrocell id="FB1_MC9" pin="FB1_MC9_PIN5" sigUse="8" signal="slaveinten"><pterms pt1="FB1_9_1" pt2="FB1_9_2" pt3="FB1_9_3" pt4="FB1_9_4" pt5="FB1_9_5"/></macrocell><macrocell id="FB1_MC10" sigUse="8" signal="frx"><pterms pt1="FB1_10_1" pt2="FB1_10_2" pt3="FB1_10_3" pt4="FB1_10_4" pt5="FB1_10_5"/></macrocell><macrocell id="FB1_MC11" pin="FB1_MC11_PIN6" sigUse="8" signal="ece"><pterms pt1="FB1_11_1" pt2="FB1_11_2" pt3="FB1_11_3" pt4="FB1_11_4" pt5="FB1_11_5"/></macrocell><macrocell id="FB1_MC12" sigUse="8" signal="divisor2_SPECSIG"><pterms pt1="FB1_12_1" pt2="FB1_12_2" pt3="FB1_12_3" pt4="FB1_12_4" pt5="FB1_12_5"/></macrocell><macrocell id="FB1_MC13" sigUse="8" signal="divisor1_SPECSIG"><pterms pt1="FB1_13_1" pt2="FB1_13_2" pt3="FB1_13_3" pt4="FB1_13_4" pt5="FB1_13_5"/></macrocell><macrocell id="FB1_MC14" pin="FB1_MC14_PIN7" sigUse="8" signal="divisor0_SPECSIG"><pterms pt1="FB1_14_1" pt2="FB1_14_2" pt3="FB1_14_3" pt4="FB1_14_4" pt5="FB1_14_5"/></macrocell><macrocell id="FB1_MC15" pin="FB1_MC15_PIN8" sigUse="8" signal="cpu_d3_SPECSIG"><pterms pt1="FB1_15_1" pt2="FB1_15_2" pt3="FB1_15_3"/></macrocell><macrocell id="FB1_MC16" sigUse="8" signal="cpol"><pterms pt1="FB1_16_1" pt2="FB1_16_2" pt3="FB1_16_3" pt4="FB1_16_4" pt5="FB1_16_5"/></macrocell><macrocell id="FB1_MC17" pin="FB1_MC17_PIN9" sigUse="10" signal="cpu_d4_SPECSIG"><pterms pt1="FB1_17_1" pt2="FB1_17_2" pt3="FB1_17_3" pt4="FB1_17_4" pt5="FB1_17_5"/></macrocell><macrocell id="FB1_MC18" sigUse="8" signal="cpha"><pterms pt1="FB1_18_1" pt2="FB1_18_2" pt3="FB1_18_3" pt4="FB1_18_4" pt5="FB1_18_5"/></macrocell><fbinput id="FB1_I1" fbk="PIN" signal="cpu_d0PIN_SPECSIG"/><fbinput id="FB1_I2" fbk="PIN" signal="cpu_d1PIN_SPECSIG"/><fbinput id="FB1_I3" fbk="PIN" signal="cpu_d2PIN_SPECSIG"/><fbinput id="FB1_I4" fbk="PIN" signal="cpu_d3PIN_SPECSIG"/><fbinput id="FB1_I5" fbk="PIN" signal="cpu_d4PIN_SPECSIG"/><fbinput id="FB1_I6" signal="Ncs2"/><fbinput id="FB1_I7" signal="cpha"/><fbinput id="FB1_I8" signal="cpol"/><fbinput id="FB1_I9" signal="cpu_Nphi2"/><fbinput id="FB1_I10" signal="cpu_Nres"/><fbinput id="FB1_I11" signal="cpu_a0_SPECSIG"/><fbinput id="FB1_I12" signal="cpu_a1_SPECSIG"/><fbinput id="FB1_I13" signal="cpu_rnw"/><fbinput id="FB1_I14" signal="cs1"/><fbinput id="FB1_I15" signal="divisor0_SPECSIG"/><fbinput id="FB1_I16" signal="divisor1_SPECSIG"/><fbinput id="FB1_I17" signal="divisor2_SPECSIG"/><fbinput id="FB1_I18" signal="ece"/><fbinput id="FB1_I19" signal="frx"/><fbinput id="FB1_I20" signal="slaveinten"/><fbinput id="FB1_I21" signal="spi_Nsel"/><fbinput id="FB1_I22" signal="spi_int"/><fbinput id="FB1_I23" signal="spidatain0_SPECSIG"/><fbinput id="FB1_I24" signal="spidatain1_SPECSIG"/><fbinput id="FB1_I25" signal="spidatain2_SPECSIG"/><fbinput id="FB1_I26" signal="spidatain3_SPECSIG"/><fbinput id="FB1_I27" signal="spidatain4_SPECSIG"/><fbinput id="FB1_I28" signal="spidataout0_SPECSIG"/><fbinput id="FB1_I29" signal="spidataout1_SPECSIG"/><fbinput id="FB1_I30" signal="spidataout2_SPECSIG"/><fbinput id="FB1_I31" signal="tmo"/><pterm id="FB1_2_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout2_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_2_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout2_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG"/></pterm><pterm id="FB1_2_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_2_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_3_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_3_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG"/></pterm><pterm id="FB1_3_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_3_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_4_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout0_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_4_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout0_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB1_4_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_4_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_5_1"><signal id="cpu_rnw"/><signal id="spi_Nsel"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_2"><signal id="cpu_rnw"/><signal id="cpha"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_3"><signal id="cpu_rnw"/><signal id="divisor0_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_4"><signal id="cpu_rnw"/><signal id="spidatain0_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_5_5"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_1"><signal id="cpu_rnw"/><signal id="cpol"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_2"><signal id="cpu_rnw"/><signal id="divisor1_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_3"><signal id="cpu_rnw"/><signal id="spidatain1_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_6_4"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_7_1"><signal id="tmo"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d3PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_7_2"><signal id="tmo" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d3PIN_SPECSIG"/></pterm><pterm id="FB1_7_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_7_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_7_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_8_1"><signal id="cpu_rnw"/><signal id="ece"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_8_2"><signal id="cpu_rnw"/><signal id="divisor2_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_8_3"><signal id="cpu_rnw"/><signal id="spidatain2_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_8_4"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_9_1"><signal id="slaveinten"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_9_2"><signal id="slaveinten" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG"/></pterm><pterm id="FB1_9_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_9_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_9_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_10_1"><signal id="frx"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_10_2"><signal id="frx" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d4PIN_SPECSIG"/></pterm><pterm id="FB1_10_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_10_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_10_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_11_1"><signal id="ece"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d2PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_11_2"><signal id="ece" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d2PIN_SPECSIG"/></pterm><pterm id="FB1_11_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_11_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_11_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_12_1"><signal id="divisor2_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_12_2"><signal id="divisor2_SPECSIG" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d2PIN_SPECSIG"/></pterm><pterm id="FB1_12_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_12_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_12_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_13_1"><signal id="divisor1_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_13_2"><signal id="divisor1_SPECSIG" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d1PIN_SPECSIG"/></pterm><pterm id="FB1_13_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_13_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_13_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_14_1"><signal id="divisor0_SPECSIG"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_14_2"><signal id="divisor0_SPECSIG" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB1_14_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_14_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_14_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_15_1"><signal id="cpu_rnw"/><signal id="tmo"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_15_2"><signal id="cpu_rnw"/><signal id="spidatain3_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_15_3"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_16_1"><signal id="cpol"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d1PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_16_2"><signal id="cpol" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d1PIN_SPECSIG"/></pterm><pterm id="FB1_16_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_16_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_16_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB1_17_1"><signal id="cpu_rnw"/><signal id="frx"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_2"><signal id="cpu_rnw"/><signal id="slaveinten"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_3"><signal id="cpu_rnw"/><signal id="spidatain4_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_4"><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="spi_int" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_17_5"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB1_18_1"><signal id="cpha"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB1_18_2"><signal id="cpha" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB1_18_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB1_18_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB1_18_5"><signal id="cpu_rnw" negated="ON"/></pterm><equation id="spidataout2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_2_1"/><eq_pterm ptindx="FB1_2_2"/></d2><clk><eq_pterm ptindx="FB1_2_3"/></clk><ce><eq_pterm ptindx="FB1_2_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout1_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_3_1"/><eq_pterm ptindx="FB1_3_2"/></d2><clk><eq_pterm ptindx="FB1_3_3"/></clk><ce><eq_pterm ptindx="FB1_3_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout0_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_4_1"/><eq_pterm ptindx="FB1_4_2"/></d2><clk><eq_pterm ptindx="FB1_4_3"/></clk><ce><eq_pterm ptindx="FB1_4_4"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d0_SPECSIG"><d2><eq_pterm ptindx="FB1_5_1"/><eq_pterm ptindx="FB1_5_2"/><eq_pterm ptindx="FB1_5_3"/><eq_pterm ptindx="FB1_5_4"/></d2><oe><eq_pterm ptindx="FB1_5_5"/></oe></equation><equation id="cpu_d1_SPECSIG"><d2><eq_pterm ptindx="FB1_6_1"/><eq_pterm ptindx="FB1_6_2"/><eq_pterm ptindx="FB1_6_3"/></d2><oe><eq_pterm ptindx="FB1_6_4"/></oe></equation><equation id="tmo" regUse="T"><d2><eq_pterm ptindx="FB1_7_1"/><eq_pterm ptindx="FB1_7_2"/></d2><clk><eq_pterm ptindx="FB1_7_4"/></clk><reset><eq_pterm ptindx="FB1_7_3"/></reset><ce><eq_pterm ptindx="FB1_7_5"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d2_SPECSIG"><d2><eq_pterm ptindx="FB1_8_1"/><eq_pterm ptindx="FB1_8_2"/><eq_pterm ptindx="FB1_8_3"/></d2><oe><eq_pterm ptindx="FB1_8_4"/></oe></equation><equation id="slaveinten" regUse="T"><d2><eq_pterm ptindx="FB1_9_1"/><eq_pterm ptindx="FB1_9_2"/></d2><clk><eq_pterm ptindx="FB1_9_4"/></clk><reset><eq_pterm ptindx="FB1_9_3"/></reset><ce><eq_pterm ptindx="FB1_9_5"/></ce><prld ptindx="GND"/></equation><equation id="frx" regUse="T"><d2><eq_pterm ptindx="FB1_10_1"/><eq_pterm ptindx="FB1_10_2"/></d2><clk><eq_pterm ptindx="FB1_10_4"/></clk><reset><eq_pterm ptindx="FB1_10_3"/></reset><ce><eq_pterm ptindx="FB1_10_5"/></ce><prld ptindx="GND"/></equation><equation id="ece" regUse="T"><d2><eq_pterm ptindx="FB1_11_1"/><eq_pterm ptindx="FB1_11_2"/></d2><clk><eq_pterm ptindx="FB1_11_4"/></clk><reset><eq_pterm ptindx="FB1_11_3"/></reset><ce><eq_pterm ptindx="FB1_11_5"/></ce><prld ptindx="GND"/></equation><equation id="divisor2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_12_1"/><eq_pterm ptindx="FB1_12_2"/></d2><clk><eq_pterm ptindx="FB1_12_4"/></clk><reset><eq_pterm ptindx="FB1_12_3"/></reset><ce><eq_pterm ptindx="FB1_12_5"/></ce><prld ptindx="GND"/></equation><equation id="divisor1_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_13_1"/><eq_pterm ptindx="FB1_13_2"/></d2><clk><eq_pterm ptindx="FB1_13_4"/></clk><reset><eq_pterm ptindx="FB1_13_3"/></reset><ce><eq_pterm ptindx="FB1_13_5"/></ce><prld ptindx="GND"/></equation><equation id="divisor0_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_14_1"/><eq_pterm ptindx="FB1_14_2"/></d2><clk><eq_pterm ptindx="FB1_14_4"/></clk><reset><eq_pterm ptindx="FB1_14_3"/></reset><ce><eq_pterm ptindx="FB1_14_5"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d3_SPECSIG"><d2><eq_pterm ptindx="FB1_15_1"/><eq_pterm ptindx="FB1_15_2"/></d2><oe><eq_pterm ptindx="FB1_15_3"/></oe></equation><equation id="cpol" regUse="T"><d2><eq_pterm ptindx="FB1_16_1"/><eq_pterm ptindx="FB1_16_2"/></d2><clk><eq_pterm ptindx="FB1_16_4"/></clk><reset><eq_pterm ptindx="FB1_16_3"/></reset><ce><eq_pterm ptindx="FB1_16_5"/></ce><prld ptindx="GND"/></equation><equation id="cpu_d4_SPECSIG"><d2><eq_pterm ptindx="FB1_17_1"/><eq_pterm ptindx="FB1_17_2"/><eq_pterm ptindx="FB1_17_3"/><eq_pterm ptindx="FB1_17_4"/></d2><oe><eq_pterm ptindx="FB1_17_5"/></oe></equation><equation id="cpha" regUse="T"><d2><eq_pterm ptindx="FB1_18_1"/><eq_pterm ptindx="FB1_18_2"/></d2><clk><eq_pterm ptindx="FB1_18_4"/></clk><reset><eq_pterm ptindx="FB1_18_3"/></reset><ce><eq_pterm ptindx="FB1_18_5"/></ce><prld ptindx="GND"/></equation></fblock><fblock id="FB2" pinUse="3" inputUse="30"><macrocell id="FB2_MC1"><pterms pt1="FB2_1_1" pt2="FB2_1_2" pt3="FB2_1_3" pt4="FB2_1_4" pt5="FB2_1_5"/></macrocell><macrocell id="FB2_MC2" pin="FB2_MC2_PIN35" sigUse="16" signal="spi_mosi"><pterms pt1="FB2_2_1" pt2="FB2_2_2" pt3="FB2_2_3" pt4="FB2_2_4" pt5="FB2_2_5"/></macrocell><macrocell id="FB2_MC3" sigUse="3" signal="shifting2"><pterms pt1="FB2_3_1" pt2="FB2_3_2" pt3="FB2_3_3"/></macrocell><macrocell id="FB2_MC4" sigUse="6" signal="shiftdone"><pterms pt1="FB2_4_1" pt2="FB2_4_2" pt3="FB2_4_3"/></macrocell><macrocell id="FB2_MC5" pin="FB2_MC5_PIN36" sigUse="4" signal="shiftcnt0_SPECSIG"><pterms pt1="FB2_5_1" pt2="FB2_5_2" pt3="FB2_5_3"/></macrocell><macrocell id="FB2_MC6" pin="FB2_MC6_PIN37" sigUse="5" signal="OpTxINV22__INT_SPECSIG"><pterms pt1="FB2_6_1" pt2="FB2_6_2" pt3="FB2_6_3"/></macrocell><macrocell id="FB2_MC7" sigUse="5" signal="spidatain7_SPECSIG"><pterms pt1="FB2_7_1" pt2="FB2_7_2" pt3="FB2_7_3" pt4="FB2_7_4"/></macrocell><macrocell id="FB2_MC8" pin="FB2_MC8_PIN38" sigUse="5" signal="spidatain6_SPECSIG"><pterms pt1="FB2_8_1" pt2="FB2_8_2" pt3="FB2_8_3" pt4="FB2_8_4"/></macrocell><macrocell id="FB2_MC9" pin="FB2_MC9_PIN39" sigUse="5" signal="spidatain5_SPECSIG"><pterms pt1="FB2_9_1" pt2="FB2_9_2" pt3="FB2_9_3" pt4="FB2_9_4"/></macrocell><macrocell id="FB2_MC10" sigUse="5" signal="spidatain4_SPECSIG"><pterms pt1="FB2_10_1" pt2="FB2_10_2" pt3="FB2_10_3" pt4="FB2_10_4"/></macrocell><macrocell id="FB2_MC11" pin="FB2_MC11_PIN40" sigUse="5" signal="spidatain3_SPECSIG"><pterms pt1="FB2_11_1" pt2="FB2_11_2" pt3="FB2_11_3" pt4="FB2_11_4"/></macrocell><macrocell id="FB2_MC12" sigUse="5" signal="spidatain2_SPECSIG"><pterms pt1="FB2_12_1" pt2="FB2_12_2" pt3="FB2_12_3" pt4="FB2_12_4"/></macrocell><macrocell id="FB2_MC13" sigUse="5" signal="spidatain1_SPECSIG"><pterms pt1="FB2_13_1" pt2="FB2_13_2" pt3="FB2_13_3" pt4="FB2_13_4"/></macrocell><macrocell id="FB2_MC14" pin="FB2_MC14_PIN42" sigUse="6" signal="spidatain0_SPECSIG"><pterms pt1="FB2_14_1" pt2="FB2_14_2" pt3="FB2_14_3" pt4="FB2_14_4"/></macrocell><macrocell id="FB2_MC15" pin="FB2_MC15_PIN43" sigUse="7" signal="shiftcnt3_SPECSIG"><pterms pt1="FB2_15_1" pt2="FB2_15_2" pt3="FB2_15_3" pt4="FB2_15_4"/></macrocell><macrocell id="FB2_MC16" sigUse="6" signal="shiftcnt2_SPECSIG"><pterms pt1="FB2_16_1" pt2="FB2_16_2" pt3="FB2_16_3" pt4="FB2_16_4"/></macrocell><macrocell id="FB2_MC17" pin="FB2_MC17_PIN44" sigUse="5" signal="shiftcnt1_SPECSIG"><pterms pt1="FB2_17_1" pt2="FB2_17_2" pt3="FB2_17_3" pt4="FB2_17_4"/></macrocell><macrocell id="FB2_MC18" sigUse="2" signal="start_shiftingstart_shifting_RSTF__INT_SPECSIG"><pterms pt1="FB2_18_1"/></macrocell><fbinput id="FB2_I1" signal="OpTxINV22__INT_SPECSIG"/><fbinput id="FB2_I2" signal="cpu_Nphi2"/><fbinput id="FB2_I3" signal="cpu_Nres"/><fbinput id="FB2_I4" signal="ece"/><fbinput id="FB2_I5" signal="extclk"/><fbinput id="FB2_I6" signal="shiftcnt0_SPECSIG"/><fbinput id="FB2_I7" signal="shiftcnt1_SPECSIG"/><fbinput id="FB2_I8" signal="shiftcnt2_SPECSIG"/><fbinput id="FB2_I9" signal="shiftcnt3_SPECSIG"/><fbinput id="FB2_I10" signal="shiftdone"/><fbinput id="FB2_I11" signal="shifting2"/><fbinput id="FB2_I12" signal="spi_Nsel"/><fbinput id="FB2_I13" signal="spi_miso"/><fbinput id="FB2_I14" signal="spidatain0_SPECSIG"/><fbinput id="FB2_I15" signal="spidatain1_SPECSIG"/><fbinput id="FB2_I16" signal="spidatain2_SPECSIG"/><fbinput id="FB2_I17" signal="spidatain3_SPECSIG"/><fbinput id="FB2_I18" signal="spidatain4_SPECSIG"/><fbinput id="FB2_I19" signal="spidatain5_SPECSIG"/><fbinput id="FB2_I20" signal="spidatain6_SPECSIG"/><fbinput id="FB2_I21" signal="spidataout0_SPECSIG"/><fbinput id="FB2_I22" signal="spidataout1_SPECSIG"/><fbinput id="FB2_I23" signal="spidataout2_SPECSIG"/><fbinput id="FB2_I24" signal="spidataout3_SPECSIG"/><fbinput id="FB2_I25" signal="spidataout4_SPECSIG"/><fbinput id="FB2_I26" signal="spidataout5_SPECSIG"/><fbinput id="FB2_I27" signal="spidataout6_SPECSIG"/><fbinput id="FB2_I28" signal="spidataout7_SPECSIG"/><fbinput id="FB2_I29" signal="start_shifting"/><fbinput id="FB2_I30" signal="tmo"/><pterm id="FB2_1_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout0_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_2"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout2_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_3"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout3_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_4"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout4_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_1_5"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout7_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_2_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout1_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_2_2"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="spidataout5_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_2_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_2_4"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_2_5"><signal id="tmo" negated="ON"/></pterm><pterm id="FB2_3_1"><signal id="shiftdone" negated="ON"/><signal id="start_shifting"/></pterm><pterm id="FB2_3_2"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_3_3"><signal id="shiftcnt3_SPECSIG" negated="ON"/><signal id="shiftcnt2_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="spidataout6_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_4_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/></pterm><pterm id="FB2_4_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_4_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_5_1"><signal id="shiftcnt0_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_5_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_5_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_6_1"><signal id="ece"/><signal id="extclk" negated="ON"/></pterm><pterm id="FB2_6_2"><signal id="ece" negated="ON"/><signal id="cpu_Nphi2" negated="ON"/></pterm><pterm id="FB2_6_3"><signal id="start_shifting" negated="ON"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB2_7_1"><signal id="spidatain6_SPECSIG"/></pterm><pterm id="FB2_7_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_7_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_7_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_8_1"><signal id="spidatain5_SPECSIG"/></pterm><pterm id="FB2_8_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_8_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_8_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_9_1"><signal id="spidatain4_SPECSIG"/></pterm><pterm id="FB2_9_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_9_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_9_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_10_1"><signal id="spidatain3_SPECSIG"/></pterm><pterm id="FB2_10_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_10_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_10_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_11_1"><signal id="spidatain2_SPECSIG"/></pterm><pterm id="FB2_11_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_11_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_11_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_12_1"><signal id="spidatain1_SPECSIG"/></pterm><pterm id="FB2_12_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_12_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_12_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_13_1"><signal id="spidatain0_SPECSIG"/></pterm><pterm id="FB2_13_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_13_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_13_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_14_1"><signal id="spi_Nsel" negated="ON"/><signal id="spi_miso"/></pterm><pterm id="FB2_14_2"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_14_3"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_14_4"><signal id="shiftcnt0_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_15_1"><signal id="shiftcnt3_SPECSIG"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB2_15_2"><signal id="shiftcnt2_SPECSIG"/><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_15_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_15_4"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_16_1"><signal id="shiftcnt2_SPECSIG"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB2_16_2"><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_16_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_16_4"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_17_1"><signal id="shiftcnt0_SPECSIG"/><signal id="shiftcnt1_SPECSIG" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB2_17_2"><signal id="shiftcnt0_SPECSIG" negated="ON"/><signal id="shiftcnt1_SPECSIG"/><signal id="shifting2"/></pterm><pterm id="FB2_17_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB2_17_4"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB2_18_1"><signal id="cpu_Nres"/><signal id="shiftdone" negated="ON"/></pterm><equation id="spi_mosi" regUse="D" negated="ON"><d2><eq_pterm ptindx="FB2_2_1"/><eq_pterm ptindx="FB2_2_2"/><eq_pterm import="1" ptindx="FB2_1_1"/><eq_pterm import="1" ptindx="FB2_1_2"/><eq_pterm import="1" ptindx="FB2_1_3"/><eq_pterm import="1" ptindx="FB2_1_4"/><eq_pterm import="1" ptindx="FB2_1_5"/><eq_pterm import="1" ptindx="FB2_3_3"/></d2><clk><eq_pterm ptindx="FB2_2_4"/></clk><set><eq_pterm ptindx="FB2_2_3"/></set><oe><eq_pterm ptindx="FB2_2_5"/></oe><prld ptindx="GND"/></equation><equation id="shifting2" regUse="D"><d2><eq_pterm ptindx="FB2_3_1"/></d2><clk><eq_pterm ptindx="FB2_3_2"/></clk><prld ptindx="GND"/></equation><equation id="shiftdone" regUse="D"><d2><eq_pterm ptindx="FB2_4_1"/></d2><clk><eq_pterm ptindx="FB2_4_3"/></clk><reset><eq_pterm ptindx="FB2_4_2"/></reset><prld ptindx="GND"/></equation><equation id="shiftcnt0_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_5_1"/></d2><clk><eq_pterm ptindx="FB2_5_3"/></clk><reset><eq_pterm ptindx="FB2_5_2"/></reset><prld ptindx="GND"/></equation><equation id="OpTxINV22__INT_SPECSIG"><d2><eq_pterm ptindx="FB2_6_1"/><eq_pterm ptindx="FB2_6_2"/><eq_pterm ptindx="FB2_6_3"/></d2></equation><equation id="spidatain7_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_7_1"/></d2><clk><eq_pterm ptindx="FB2_7_3"/></clk><reset><eq_pterm ptindx="FB2_7_2"/></reset><ce><eq_pterm ptindx="FB2_7_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain6_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_8_1"/></d2><clk><eq_pterm ptindx="FB2_8_3"/></clk><reset><eq_pterm ptindx="FB2_8_2"/></reset><ce><eq_pterm ptindx="FB2_8_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain5_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_9_1"/></d2><clk><eq_pterm ptindx="FB2_9_3"/></clk><reset><eq_pterm ptindx="FB2_9_2"/></reset><ce><eq_pterm ptindx="FB2_9_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain4_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_10_1"/></d2><clk><eq_pterm ptindx="FB2_10_3"/></clk><reset><eq_pterm ptindx="FB2_10_2"/></reset><ce><eq_pterm ptindx="FB2_10_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain3_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_11_1"/></d2><clk><eq_pterm ptindx="FB2_11_3"/></clk><reset><eq_pterm ptindx="FB2_11_2"/></reset><ce><eq_pterm ptindx="FB2_11_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain2_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_12_1"/></d2><clk><eq_pterm ptindx="FB2_12_3"/></clk><reset><eq_pterm ptindx="FB2_12_2"/></reset><ce><eq_pterm ptindx="FB2_12_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain1_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_13_1"/></d2><clk><eq_pterm ptindx="FB2_13_3"/></clk><reset><eq_pterm ptindx="FB2_13_2"/></reset><ce><eq_pterm ptindx="FB2_13_4"/></ce><prld ptindx="GND"/></equation><equation id="spidatain0_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_14_1"/></d2><clk><eq_pterm ptindx="FB2_14_3"/></clk><reset><eq_pterm ptindx="FB2_14_2"/></reset><ce><eq_pterm ptindx="FB2_14_4"/></ce><prld ptindx="GND"/></equation><equation id="shiftcnt3_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_15_1"/><eq_pterm ptindx="FB2_15_2"/></d2><clk><eq_pterm ptindx="FB2_15_4"/></clk><reset><eq_pterm ptindx="FB2_15_3"/></reset><prld ptindx="GND"/></equation><equation id="shiftcnt2_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB2_16_1"/><eq_pterm ptindx="FB2_16_2"/></d2><clk><eq_pterm ptindx="FB2_16_4"/></clk><reset><eq_pterm ptindx="FB2_16_3"/></reset><prld ptindx="GND"/></equation><equation id="shiftcnt1_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_17_1"/><eq_pterm ptindx="FB2_17_2"/></d2><clk><eq_pterm ptindx="FB2_17_4"/></clk><reset><eq_pterm ptindx="FB2_17_3"/></reset><prld ptindx="GND"/></equation><equation id="start_shiftingstart_shifting_RSTF__INT_SPECSIG"><d2><eq_pterm ptindx="FB2_18_1"/></d2></equation></fblock><fblock id="FB3" pinUse="9" inputUse="14"><macrocell id="FB3_MC1"/><macrocell id="FB3_MC2" pin="FB3_MC2_PIN11" sigUse="9" signal="cpu_d5_SPECSIG"><pterms pt1="FB3_2_1" pt2="FB3_2_2" pt3="FB3_2_3" pt4="FB3_2_4"/></macrocell><macrocell id="FB3_MC3"/><macrocell id="FB3_MC4"/><macrocell id="FB3_MC5" pin="FB3_MC5_PIN12" sigUse="8" signal="cpu_d6_SPECSIG"><pterms pt1="FB3_5_1" pt2="FB3_5_2" pt3="FB3_5_3"/></macrocell><macrocell id="FB3_MC6"/><macrocell id="FB3_MC7"/><macrocell id="FB3_MC8" pin="FB3_MC8_PIN13" sigUse="8" signal="cpu_d7_SPECSIG"><pterms pt1="FB3_8_1" pt2="FB3_8_2" pt3="FB3_8_3"/></macrocell><macrocell id="FB3_MC9" pin="FB3_MC9_PIN14" sigUse="1" signal="cpu_Nirq"><pterms pt1="FB3_9_1"/></macrocell><macrocell id="FB3_MC10"/><macrocell id="FB3_MC11" pin="FB3_MC11_PIN18"/><macrocell id="FB3_MC12"/><macrocell id="FB3_MC13"/><macrocell id="FB3_MC14" pin="FB3_MC14_PIN19"/><macrocell id="FB3_MC15" pin="FB3_MC15_PIN20"/><macrocell id="FB3_MC16" pin="FB3_MC16_PIN24"/><macrocell id="FB3_MC17" pin="FB3_MC17_PIN22"/><macrocell id="FB3_MC18"/><fbinput id="FB3_I1" signal="Ncs2"/><fbinput id="FB3_I2" signal="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"/><fbinput id="FB3_I3" signal="cpu_Nphi2"/><fbinput id="FB3_I4" signal="cpu_a0_SPECSIG"/><fbinput id="FB3_I5" signal="cpu_a1_SPECSIG"/><fbinput id="FB3_I6" signal="cpu_rnw"/><fbinput id="FB3_I7" signal="cs1"/><fbinput id="FB3_I8" signal="ier"/><fbinput id="FB3_I9" signal="shifting2"/><fbinput id="FB3_I10" signal="spidatain5_SPECSIG"/><fbinput id="FB3_I11" signal="spidatain6_SPECSIG"/><fbinput id="FB3_I12" signal="spidatain7_SPECSIG"/><fbinput id="FB3_I13" signal="start_shifting"/><fbinput id="FB3_I14" signal="tc"/><pterm id="FB3_2_1"><signal id="cpu_rnw"/><signal id="spidatain5_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_2_2"><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="start_shifting"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_2_3"><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="shifting2"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_2_4"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_5_1"><signal id="cpu_rnw"/><signal id="ier"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_5_2"><signal id="cpu_rnw"/><signal id="spidatain6_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_5_3"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_8_1"><signal id="cpu_rnw"/><signal id="spidatain7_SPECSIG"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_8_2"><signal id="cpu_rnw"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="tc"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_8_3"><signal id="cpu_rnw"/><signal id="cs1"/><signal id="Ncs2" negated="ON"/><signal id="cpu_Nphi2"/></pterm><pterm id="FB3_9_1"><signal id="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"/></pterm><equation id="cpu_d5_SPECSIG"><d2><eq_pterm ptindx="FB3_2_1"/><eq_pterm ptindx="FB3_2_2"/><eq_pterm ptindx="FB3_2_3"/></d2><oe><eq_pterm ptindx="FB3_2_4"/></oe></equation><equation id="cpu_d6_SPECSIG"><d2><eq_pterm ptindx="FB3_5_1"/><eq_pterm ptindx="FB3_5_2"/></d2><oe><eq_pterm ptindx="FB3_5_3"/></oe></equation><equation id="cpu_d7_SPECSIG"><d2><eq_pterm ptindx="FB3_8_1"/><eq_pterm ptindx="FB3_8_2"/></d2><oe><eq_pterm ptindx="FB3_8_3"/></oe></equation><equation id="cpu_Nirq"><d2><eq_pterm ptindx="GND"/></d2><oe><eq_pterm ptindx="FB3_9_1"/></oe></equation></fblock><fblock id="FB4" pinUse="3" inputUse="31"><macrocell id="FB4_MC1" sigUse="4" signal="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"><pterms pt1="FB4_1_1" pt2="FB4_1_2"/></macrocell><macrocell id="FB4_MC2" pin="FB4_MC2_PIN25" sigUse="5" signal="tc"><pterms pt1="FB4_2_1" pt2="FB4_2_2" pt3="FB4_2_3"/></macrocell><macrocell id="FB4_MC3" sigUse="8" signal="start_shifting"><pterms pt1="FB4_3_1" pt2="FB4_3_2" pt3="FB4_3_3" pt4="FB4_3_4"/></macrocell><macrocell id="FB4_MC4" sigUse="8" signal="spidataout7_SPECSIG"><pterms pt1="FB4_4_1" pt2="FB4_4_2" pt3="FB4_4_3" pt4="FB4_4_4"/></macrocell><macrocell id="FB4_MC5" pin="FB4_MC5_PIN26" sigUse="8" signal="spidataout6_SPECSIG"><pterms pt1="FB4_5_1" pt2="FB4_5_2" pt3="FB4_5_3" pt4="FB4_5_4"/></macrocell><macrocell id="FB4_MC6" sigUse="8" signal="spidataout5_SPECSIG"><pterms pt1="FB4_6_1" pt2="FB4_6_2" pt3="FB4_6_3" pt4="FB4_6_4"/></macrocell><macrocell id="FB4_MC7" sigUse="8" signal="spidataout4_SPECSIG"><pterms pt1="FB4_7_1" pt2="FB4_7_2" pt3="FB4_7_3" pt4="FB4_7_4"/></macrocell><macrocell id="FB4_MC8" pin="FB4_MC8_PIN27" sigUse="8" signal="spidataout3_SPECSIG"><pterms pt1="FB4_8_1" pt2="FB4_8_2" pt3="FB4_8_3" pt4="FB4_8_4"/></macrocell><macrocell id="FB4_MC9" sigUse="8" signal="ier"><pterms pt1="FB4_9_1" pt2="FB4_9_2" pt3="FB4_9_3" pt4="FB4_9_4" pt5="FB4_9_5"/></macrocell><macrocell id="FB4_MC10"/><macrocell id="FB4_MC11" pin="FB4_MC11_PIN28" sigUse="8" signal="spi_Nsel"><pterms pt1="FB4_11_1" pt2="FB4_11_2" pt3="FB4_11_3" pt4="FB4_11_4" pt5="FB4_11_5"/></macrocell><macrocell id="FB4_MC12"/><macrocell id="FB4_MC13"/><macrocell id="FB4_MC14" pin="FB4_MC14_PIN29" sigUse="3" signal="led"><pterms pt1="FB4_14_1"/></macrocell><macrocell id="FB4_MC15" pin="FB4_MC15_PIN33"/><macrocell id="FB4_MC16"><pterms pt1="FB4_16_1"/></macrocell><macrocell id="FB4_MC17" pin="FB4_MC17_PIN34" sigUse="7" signal="spi_sclk"><pterms pt1="FB4_17_1" pt2="FB4_17_2" pt3="FB4_17_3" pt4="FB4_17_4" pt5="FB4_17_5"/></macrocell><macrocell id="FB4_MC18"/><fbinput id="FB4_I1" signal="OpTxINV22__INT_SPECSIG"/><fbinput id="FB4_I2" fbk="PIN" signal="cpu_d0PIN_SPECSIG"/><fbinput id="FB4_I3" fbk="PIN" signal="cpu_d3PIN_SPECSIG"/><fbinput id="FB4_I4" fbk="PIN" signal="cpu_d4PIN_SPECSIG"/><fbinput id="FB4_I5" fbk="PIN" signal="cpu_d5PIN_SPECSIG"/><fbinput id="FB4_I6" fbk="PIN" signal="cpu_d6PIN_SPECSIG"/><fbinput id="FB4_I7" fbk="PIN" signal="cpu_d7PIN_SPECSIG"/><fbinput id="FB4_I8" signal="Ncs2"/><fbinput id="FB4_I9" signal="cpha"/><fbinput id="FB4_I10" signal="cpol"/><fbinput id="FB4_I11" signal="cpu_Nres"/><fbinput id="FB4_I12" signal="cpu_a0_SPECSIG"/><fbinput id="FB4_I13" signal="cpu_a1_SPECSIG"/><fbinput id="FB4_I14" signal="cpu_rnw"/><fbinput id="FB4_I15" signal="cs1"/><fbinput id="FB4_I16" signal="frx"/><fbinput id="FB4_I17" signal="ier"/><fbinput id="FB4_I18" signal="shiftcnt0_SPECSIG"/><fbinput id="FB4_I19" signal="shiftdone"/><fbinput id="FB4_I20" signal="shifting2"/><fbinput id="FB4_I21" signal="slaveinten"/><fbinput id="FB4_I22" signal="spi_Nsel"/><fbinput id="FB4_I23" signal="spi_int"/><fbinput id="FB4_I24" signal="spidataout3_SPECSIG"/><fbinput id="FB4_I25" signal="spidataout4_SPECSIG"/><fbinput id="FB4_I26" signal="spidataout5_SPECSIG"/><fbinput id="FB4_I27" signal="spidataout6_SPECSIG"/><fbinput id="FB4_I28" signal="spidataout7_SPECSIG"/><fbinput id="FB4_I29" signal="start_shifting"/><fbinput id="FB4_I30" signal="start_shiftingstart_shifting_RSTF__INT_SPECSIG"/><fbinput id="FB4_I31" signal="tc"/><pterm id="FB4_1_1"><signal id="ier"/><signal id="tc"/></pterm><pterm id="FB4_1_2"><signal id="slaveinten"/><signal id="spi_int" negated="ON"/></pterm><pterm id="FB4_2_1"><signal id="shiftdone"/></pterm><pterm id="FB4_2_2"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_2_3"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_1"><signal id="cpu_rnw" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="start_shifting" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_2"><signal id="frx"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="start_shifting" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_3"><signal id="start_shiftingstart_shifting_RSTF__INT_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_4_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout7_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d7PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_4_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout7_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d7PIN_SPECSIG"/></pterm><pterm id="FB4_4_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_4_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_5_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout6_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d6PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_5_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout6_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d6PIN_SPECSIG"/></pterm><pterm id="FB4_5_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_5_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_6_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout5_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d5PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_6_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout5_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d5PIN_SPECSIG"/></pterm><pterm id="FB4_6_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_6_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_7_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout4_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d4PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_7_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout4_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d4PIN_SPECSIG"/></pterm><pterm id="FB4_7_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_7_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_8_1"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout3_SPECSIG"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d3PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_8_2"><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="spidataout3_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG" negated="ON"/><signal id="cpu_d3PIN_SPECSIG"/></pterm><pterm id="FB4_8_3"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_8_4"><signal id="cpu_Nres"/><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_9_1"><signal id="ier"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d6PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_9_2"><signal id="ier" negated="ON"/><signal id="cpu_a1_SPECSIG" negated="ON"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d6PIN_SPECSIG"/></pterm><pterm id="FB4_9_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_9_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_9_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_11_1"><signal id="spi_Nsel"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG" negated="ON"/></pterm><pterm id="FB4_11_2"><signal id="spi_Nsel" negated="ON"/><signal id="cpu_a1_SPECSIG"/><signal id="cpu_a0_SPECSIG"/><signal id="cpu_d0PIN_SPECSIG"/></pterm><pterm id="FB4_11_3"><signal id="cpu_Nres" negated="ON"/></pterm><pterm id="FB4_11_4"><signal id="cs1"/><signal id="Ncs2" negated="ON"/></pterm><pterm id="FB4_11_5"><signal id="cpu_rnw" negated="ON"/></pterm><pterm id="FB4_14_1"><signal id="spi_Nsel"/><signal id="start_shifting" negated="ON"/><signal id="shifting2" negated="ON"/></pterm><pterm id="FB4_16_1"><signal id="cpu_Nres"/><signal id="cpha"/><signal id="shiftcnt0_SPECSIG" negated="ON"/><signal id="shiftdone" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB4_17_1"><signal id="cpol"/></pterm><pterm id="FB4_17_2"><signal id="cpu_Nres"/><signal id="cpha" negated="ON"/><signal id="shiftcnt0_SPECSIG"/><signal id="shiftdone" negated="ON"/><signal id="shifting2"/></pterm><pterm id="FB4_17_3"><signal id="cpu_Nres" negated="ON"/><signal id="cpol" negated="ON"/></pterm><pterm id="FB4_17_4"><signal id="cpu_Nres" negated="ON"/><signal id="cpol"/></pterm><pterm id="FB4_17_5"><signal id="OpTxINV22__INT_SPECSIG" negated="ON"/></pterm><equation id="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"><d2><eq_pterm ptindx="FB4_1_1"/><eq_pterm ptindx="FB4_1_2"/></d2></equation><equation id="tc" regUse="D"><d2><eq_pterm ptindx="GND"/></d2><clk><eq_pterm ptindx="FB4_2_2"/></clk><set><eq_pterm ptindx="FB4_2_1"/></set><ce><eq_pterm ptindx="FB4_2_3"/></ce><prld ptindx="GND"/></equation><equation id="start_shifting" regUse="T"><d2><eq_pterm ptindx="FB4_3_1"/><eq_pterm ptindx="FB4_3_2"/></d2><clk><eq_pterm ptindx="FB4_3_4"/></clk><reset><eq_pterm ptindx="FB4_3_3"/></reset><prld ptindx="GND"/></equation><equation id="spidataout7_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_4_1"/><eq_pterm ptindx="FB4_4_2"/></d2><clk><eq_pterm ptindx="FB4_4_3"/></clk><ce><eq_pterm ptindx="FB4_4_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout6_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_5_1"/><eq_pterm ptindx="FB4_5_2"/></d2><clk><eq_pterm ptindx="FB4_5_3"/></clk><ce><eq_pterm ptindx="FB4_5_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout5_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_6_1"/><eq_pterm ptindx="FB4_6_2"/></d2><clk><eq_pterm ptindx="FB4_6_3"/></clk><ce><eq_pterm ptindx="FB4_6_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout4_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_7_1"/><eq_pterm ptindx="FB4_7_2"/></d2><clk><eq_pterm ptindx="FB4_7_3"/></clk><ce><eq_pterm ptindx="FB4_7_4"/></ce><prld ptindx="GND"/></equation><equation id="spidataout3_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB4_8_1"/><eq_pterm ptindx="FB4_8_2"/></d2><clk><eq_pterm ptindx="FB4_8_3"/></clk><ce><eq_pterm ptindx="FB4_8_4"/></ce><prld ptindx="GND"/></equation><equation id="ier" regUse="T"><d2><eq_pterm ptindx="FB4_9_1"/><eq_pterm ptindx="FB4_9_2"/></d2><clk><eq_pterm ptindx="FB4_9_4"/></clk><reset><eq_pterm ptindx="FB4_9_3"/></reset><ce><eq_pterm ptindx="FB4_9_5"/></ce><prld ptindx="GND"/></equation><equation id="spi_Nsel" regUse="T"><d2><eq_pterm ptindx="FB4_11_1"/><eq_pterm ptindx="FB4_11_2"/></d2><clk><eq_pterm ptindx="FB4_11_4"/></clk><set><eq_pterm ptindx="FB4_11_3"/></set><ce><eq_pterm ptindx="FB4_11_5"/></ce><prld ptindx="GND"/></equation><equation id="led"><d2><eq_pterm ptindx="FB4_14_1"/></d2></equation><equation id="spi_sclk" regUse="D"><d1><eq_pterm ptindx="FB4_17_1"/></d1><d2><eq_pterm ptindx="FB4_17_2"/><eq_pterm import="1" ptindx="FB4_16_1"/></d2><clk><eq_pterm ptindx="FB4_17_5"/></clk><set><eq_pterm ptindx="FB4_17_4"/></set><reset><eq_pterm ptindx="FB4_17_3"/></reset><prld ptindx="GND"/></equation></fblock><vcc/><gnd/><compOpts loc="ON" part="xc9572xl-10-PC44" prld="LOW" slew="FAST" mlopt="ON" power="STD" gsropt="ON" gtsopt="ON" inputs="54" keepio="OFF" pterms="25" unused="FLOAT" exhaust="OFF" gclkopt="ON" wysiwyg="OFF" ignorets="OFF" optimize="SPEED" terminate="KEEPER"/><specSig value="cpu_d<0>.PIN" signal="cpu_d0PIN_SPECSIG"/><specSig value="cpu_a<0>" signal="cpu_a0_SPECSIG"/><specSig value="cpu_a<1>" signal="cpu_a1_SPECSIG"/><specSig value="cpu_d<1>.PIN" signal="cpu_d1PIN_SPECSIG"/><specSig value="cpu_d<2>.PIN" signal="cpu_d2PIN_SPECSIG"/><specSig value="cpu_d<4>.PIN" signal="cpu_d4PIN_SPECSIG"/><specSig value="cpu_d<6>.PIN" signal="cpu_d6PIN_SPECSIG"/><specSig value="cpu_d<3>.PIN" signal="cpu_d3PIN_SPECSIG"/><specSig value="cpu_d<5>.PIN" signal="cpu_d5PIN_SPECSIG"/><specSig value="cpu_d<7>.PIN" signal="cpu_d7PIN_SPECSIG"/><specSig value="(b)" signal="b_SPECSIG"/><specSig value="spidataout<2>" signal="spidataout2_SPECSIG"/><specSig value="I/O" signal="IO_SPECSIG"/><specSig value="cpu_d<0>" signal="cpu_d0_SPECSIG"/><specSig value="cpu_d<1>" signal="cpu_d1_SPECSIG"/><specSig value="cpu_d<2>" signal="cpu_d2_SPECSIG"/><specSig value="cpu_d<3>" signal="cpu_d3_SPECSIG"/><specSig value="cpu_d<4>" signal="cpu_d4_SPECSIG"/><specSig value="shiftcnt<0>" signal="shiftcnt0_SPECSIG"/><specSig value="$OpTx$INV$22__$INT" signal="OpTxINV22__INT_SPECSIG"/><specSig value="spidatain<6>" signal="spidatain6_SPECSIG"/><specSig value="spidatain<5>" signal="spidatain5_SPECSIG"/><specSig value="spidatain<3>" signal="spidatain3_SPECSIG"/><specSig value="shiftcnt<3>" signal="shiftcnt3_SPECSIG"/><specSig value="cpu_d<5>" signal="cpu_d5_SPECSIG"/><specSig value="cpu_d<6>" signal="cpu_d6_SPECSIG"/><specSig value="cpu_d<7>" signal="cpu_d7_SPECSIG"/><specSig value="spidataout<6>" signal="spidataout6_SPECSIG"/><specSig value="spidataout<3>" signal="spidataout3_SPECSIG"/><specSig value="spidataout<1>" signal="spidataout1_SPECSIG"/><specSig value="spidataout<0>" signal="spidataout0_SPECSIG"/><specSig value="divisor<2>" signal="divisor2_SPECSIG"/><specSig value="divisor<1>" signal="divisor1_SPECSIG"/><specSig value="divisor<0>" signal="divisor0_SPECSIG"/><specSig value="spidatain<0>" signal="spidatain0_SPECSIG"/><specSig value="spidatain<1>" signal="spidatain1_SPECSIG"/><specSig value="spidatain<2>" signal="spidatain2_SPECSIG"/><specSig value="spidatain<4>" signal="spidatain4_SPECSIG"/><specSig value="spidatain<7>" signal="spidatain7_SPECSIG"/><specSig value="shiftcnt<2>" signal="shiftcnt2_SPECSIG"/><specSig value="shiftcnt<1>" signal="shiftcnt1_SPECSIG"/><specSig value="start_shifting/start_shifting_RSTF__$INT" signal="start_shiftingstart_shifting_RSTF__INT_SPECSIG"/><specSig value="spidataout<4>" signal="spidataout4_SPECSIG"/><specSig value="spidataout<5>" signal="spidataout5_SPECSIG"/><specSig value="spidataout<7>" signal="spidataout7_SPECSIG"/><specSig value="cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST" signal="cpu_Nirq_OBUFEcpu_Nirq_OBUFE_TRST_SPECSIG"/></document>
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