173 lines
4.5 KiB
VHDL
173 lines
4.5 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 23:42:22 10/10/2017
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-- Design Name:
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-- Module Name: C:/Git/AppleIISd/VHDL/AddressDecoder_Test.vhd
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-- Project Name: AppleIISd
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: AddressDecoder
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY AddressDecoder_old_Test IS
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END AddressDecoder_old_Test;
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ARCHITECTURE behavior OF AddressDecoder_old_Test IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT AddressDecoder_old
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PORT(
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A8 : IN std_logic;
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A9 : IN std_logic;
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A10 : IN std_logic;
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B8 : OUT std_logic;
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B9 : OUT std_logic;
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B10 : OUT std_logic;
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RNW : IN std_logic;
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CLK : IN std_logic;
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NDEV_SEL : IN std_logic;
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NIO_SEL : IN std_logic;
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NIO_STB : IN std_logic;
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NOE : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal A : std_logic_vector(10 downto 8) := "101";
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signal RNW : std_logic := '1';
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signal NDEV_SEL : std_logic := '1';
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signal NIO_SEL : std_logic := '1';
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signal NIO_STB : std_logic := '1';
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signal NRESET : std_logic := '1';
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signal CLK : std_logic := '0';
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signal PHI0 : std_logic := '1';
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--Outputs
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signal B : std_logic_vector(10 downto 8);
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signal DATA_EN : std_logic;
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signal NG : std_logic;
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signal NOE : std_logic;
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-- Clock period definitions
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constant CLK_period : time := 142 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: AddressDecoder_old PORT MAP (
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A8 => A(8),
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A9 => A(9),
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A10 => A(10),
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B8 => B(8),
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B9 => B(9),
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B10 => B(10),
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RNW => RNW,
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CLK => CLK,
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NDEV_SEL => NDEV_SEL,
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NIO_SEL => NIO_SEL,
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NIO_STB => NIO_STB,
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NOE => NOE
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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PHI0_process :process(CLK)
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variable counter : integer range 0 to 7;
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begin
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if rising_edge(CLK) or falling_edge(CLK) then
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counter := counter + 1;
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if counter = 7 then
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PHI0 <= not PHI0;
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counter := 0;
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end if;
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end if;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state.
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wait for CLK_period * 10;
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NRESET <= '0';
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wait for CLK_period * 20;
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NRESET <= '1';
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wait for CLK_period * 10;
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-- insert stimulus here
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-- CPLD access
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- CnXX access
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NIO_SEL <= '0';
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wait until falling_edge(PHI0);
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NIO_SEL <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- C8xx access, selected
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NIO_STB <= '0';
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- CPLD access
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NDEV_SEL <= '0';
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- CFFF access
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A <= "111";
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NIO_STB <= '0';
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wait until falling_edge(PHI0);
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A <= "000";
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- C8xx access, unselected
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NIO_STB <= '0';
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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wait;
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end process;
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END;
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