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https://github.com/freitz85/AppleIISd.git
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80 lines
2.3 KiB
VHDL
80 lines
2.3 KiB
VHDL
-- Vhdl test bench created from schematic U:\AppleIISd\VHDL\AddressDecoder.sch - Mon Oct 09 20:12:16 2017
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--
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-- Notes:
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-- 1) This testbench template has been automatically generated using types
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-- std_logic and std_logic_vector for the ports of the unit under test.
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-- Xilinx recommends that these types always be used for the top-level
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-- I/O of a design in order to guarantee that the testbench will bind
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-- correctly to the timing (post-route) simulation model.
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-- 2) To use this template as your testbench, change the filename to any
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-- name of your choice with the extension .vhd, and use the "Source->Add"
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-- menu in Project Navigator to import the testbench. Then
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-- edit the user defined section below, adding code to generate the
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-- stimulus for your design.
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY UNISIM;
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USE UNISIM.Vcomponents.ALL;
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ENTITY AddressDecoder_AddressDecoder_sch_tb IS
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END AddressDecoder_AddressDecoder_sch_tb;
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ARCHITECTURE behavioral OF AddressDecoder_AddressDecoder_sch_tb IS
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COMPONENT AddressDecoder
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PORT( A10 : IN STD_LOGIC;
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A9 : IN STD_LOGIC;
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A8 : IN STD_LOGIC;
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B10 : OUT STD_LOGIC;
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B9 : OUT STD_LOGIC;
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B8 : OUT STD_LOGIC;
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NIO_SEL : IN STD_LOGIC;
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NDEV_SEL : IN STD_LOGIC;
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NOE : OUT STD_LOGIC;
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RNW : IN STD_LOGIC;
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NG : OUT STD_LOGIC;
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DATA_EN : OUT STD_LOGIC;
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NIO_STB : IN STD_LOGIC);
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END COMPONENT;
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SIGNAL A10 : STD_LOGIC := '0';
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SIGNAL A9 : STD_LOGIC := '0';
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SIGNAL A8 : STD_LOGIC := '0';
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SIGNAL B10 : STD_LOGIC;
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SIGNAL B9 : STD_LOGIC;
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SIGNAL B8 : STD_LOGIC;
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SIGNAL NIO_SEL : STD_LOGIC := '1';
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SIGNAL NDEV_SEL : STD_LOGIC := '1';
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SIGNAL NOE : STD_LOGIC;
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SIGNAL RNW : STD_LOGIC := '1';
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SIGNAL NG : STD_LOGIC;
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SIGNAL DATA_EN : STD_LOGIC;
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SIGNAL NIO_STB : STD_LOGIC := '1';
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BEGIN
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UUT: AddressDecoder PORT MAP(
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A10 => A10,
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A9 => A9,
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A8 => A8,
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B10 => B10,
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B9 => B9,
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B8 => B8,
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NIO_SEL => NIO_SEL,
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NDEV_SEL => NDEV_SEL,
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NOE => NOE,
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RNW => RNW,
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NG => NG,
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DATA_EN => DATA_EN,
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NIO_STB => NIO_STB
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);
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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BEGIN
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WAIT; -- will wait forever
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END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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END;
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